JPH04355949A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device capable of operating at a high speed. CONSTITUTION:Single crystal element regions 34 and 35 provided onto one of the primary surfaces of a substrate, a polycrystalline region 11 provided to the other surface as surrounded with insulating films 10 and 10', and wirings 81-85 formed on the upside of the polycrystalline region 11' through the intermediary of the insulating film 10' provided to the other surface are provided.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to semiconductor devices, and particularly to high-speed, high-precision LSI (Large Scale Integrated) devices.
SOI (Silicon o) suitable for
n Insulator) type semiconductor device.

0002

[Prior Art] In an SOI type semiconductor device, an insulating film is provided on a silicon single crystal substrate, polycrystalline silicon is applied on the insulating film, and then the polycrystalline silicon is melted and made into a single crystal. Conventional methods for forming active or passive devices on layers are promising because they can use the same conventional manufacturing processes. In order to make the crystal orientation of the single crystal layer constant, a method is used in which the insulating film is formed into an island shape, the substrate single crystal surface is exposed, and the single crystal layer is formed from there in the same orientation as the substrate.

0003

[Problem to be solved by the invention] However, since stress occurs in the recrystallized layer at the edge of the insulating film, it is not always possible to obtain a homogeneous single crystal layer, and due to crystal defects, non-uniform mobility due to internal stress, etc. However, the characteristics of the device formed in the crystal layer are impaired, making it difficult to obtain sufficient characteristics in terms of speed, precision, yield, etc.

An object of the present invention is to provide a semiconductor device that enables higher speed operation.

[0005]

[Means for Solving the Problems] The above object includes a single crystal element region provided on one main surface side, a polycrystalline region provided on the one main surface side and surrounded by an insulating film, This is achieved by including a wiring provided on the one main surface side and formed on the upper surface of the polycrystalline region via the insulating film.

[0006]

[Operation] The present invention reduces the parasitic capacitance of wiring by ensuring insulation from the substrate not only in the element region but also in the wiring region.

[0007]

[Embodiment] An embodiment of the present invention will be explained below with reference to FIG. 1. FIG. 1 is a sectional view showing the manufacturing process of a semiconductor device according to the present invention.

FIG. 7 shows a plan view of FIG. 1 showing the first embodiment. In FIG. 7, the same reference numerals as in FIG. 1 indicate the same components. Further, FIGS. 7(a) to (d) correspond to FIGS. 1(a) to (d). However, FIG. 7(d) is shown with the surface insulating layer removed in order to make the element configuration, insulating structure, etc. easier to understand. The explanation will be given in sequence according to the figures.

(a) 1 is a silicon single crystal wafer (hereinafter referred to as a wafer) that will become a semiconductor substrate; 2 is an oxide film; after uniformly oxidizing the entire surface of the wafer 1, a part of the oxide film is removed by etching; Then, an exposed surface portion 3 of the wafer 1 is provided. As a result, the oxide film 2 is formed into an island shape surrounded by the wafer exposed portion 3. Conversely, the island-shaped oxide film 2 can also be formed by selective oxidation.

(b) A low-concentration polysilicon layer 4 is provided by a CVD method or the like, and if necessary, the surface is uniformly covered with an oxide film again, and then polysilicon is formed by a laser beam or a zone melting method. The silicon layer 4 is melted and solidified. At this time, the wafer exposed portion 3 becomes a seed, and the polysilicon layer 4 becomes a single crystal layer in the same orientation as the wafer 1. If an oxide film is formed on the surface, it is removed, and then, if necessary, P ions or the like are selectively implanted using a photoresist to form a high impurity concentration layer 5.

(c) An epitaxial layer 8 is uniformly provided on the single crystal layer 4. Next, element isolation regions 9 are formed by RIE (reactive ion etching) or the like. Thereafter, the surface of the single crystal layer is oxidized by thermal oxidation or the like. At this time, the ion-implanted high impurity concentration layer 5 is thermally diffused into a so-called buried layer 6.
form. 7 is the remaining epitaxial layer with low concentration. The remaining epitaxial region mainly forms an element region.

(d) If necessary, the oxide film formed on the bottom of the element isolation region 9 is removed by RIE or the like to expose the wafer surface 12, and then the inside of the element isolation region is coated with polysilicon 11 and 13 by CVD or the like. Fill in and level the surface. Region 13 where the substrate surface oxide film was then removed as necessary.
By diffusing impurities into the polysilicon of substrate 1 to make it low resistance,
Used to connect to a surface conductor (not shown). Naturally, it is better for the low resistance region 13 not to be directly adjacent to the element region to reduce the influence of parasitic capacitance on the element, so it may be better to provide the isolation region 11 between the low resistance region 13 and the element region. Thereafter, the oxide film on the surfaces of regions 30 to 33, which will become device regions, is uniformly or selectively removed to form active or passive devices in the same manner as in the normal device formation process. For example, 7 is the collector, 1
4 is a base, 16 is an emitter, 15 is a highly impurity region for connecting the collector electrode, 17 is a collector, 18 is a base, 1
9 is each electrode of the emitter. In this way, bipolar elements 30 and 31 are formed. Further, 20 is a gate oxide film, 21 is a source, 22 is a drain region, 23 is a gate, 24 is a source electrode, 25 is a drain, and 26 is a gate electrode. In this way, the MOS transistor 32
, 33 are formed. The conductivity type of the MOS transistors 32 and 33 is reversed (from N type to P type or from P type to N type) by selectively impurity diffusion or ion implantation while the surface portion of the thermal oxide film 10 is removed. Correspondingly, by using materials of opposite conductivity type as impurity types for the source 21 and drain 22, NMOS and PMOS transistors can be simultaneously mixed, resulting in a so-called CMOS configuration. Similarly, the bipolar elements 30 and 31 are
The impurities in the ion-implanted region 5 are selectively implanted with ions of opposite conductivity type to remove the surface thermal oxide film 10 and reverse the conductivity type of the epitaxial layer 7, as in the case of MOS formation. By performing diffusion, reversing the conductivity type of the collector, and correspondingly changing the impurity conductivity types of the emitter layer 14, base layer 16, and collector electrode layer 15 using materials opposite to those described above, NPN and PNP vertical transistors can be simultaneously formed. Can be mixed.

In the above structure, the relationship between the island-shaped oxide film 2 and the element regions 30 to 33 is particularly important. When the polysilicon layer 4 attached to the top of the island-like oxide film 2 melts and solidifies,
The substrate single crystal appearing on the exposed portion of the substrate 1 is used as a seed to grow into a single crystal. Therefore, the quality of the single crystal is affected by the melting processing conditions at this time, and the presence or absence of crystal defects, the magnitude of internal stress, etc. are influenced.

FIG. 2 is a diagram showing an example of the zone melting method for monocrystalizing the polysilicon layer 4. This figure shows the relationship between a wafer 40 and a carbon heater 41 in the induction heating furnace, and the furnace body, wafer susceptor, etc. are not shown. In (A), the polysilicon layer 4 on the wafer 40 is melted in a band shape by the protrusion 42 of the carbon heater 41 . Wafer 40 and carbon heater 4
The relative position of 1 moves in the direction of the arrow. The melting conditions are determined by the moving speed, the temperature and width of the melting protrusion 42 (with respect to the wafer moving direction), the distance from the wafer, the temperature of the susceptor, etc. In this case, polysilicon is made into a single crystal by one melted protrusion 42 . In the same figure (b), the carbon heater 41 has two
Zone melting is performed twice at regular time intervals using a device provided with two melting protrusions 42 and 43. This results in
Better single crystallinity can be obtained.

(c) shows yet another method in which a preheating protrusion 44 is placed before the melting protrusion 42 of the carbon heater.
Further, a preheating protrusion 45 is provided later, and the width of the preheating/preheating protrusion 44 and 45 is narrower than that of the melting protrusion 42. FIG. 4(d) shows yet another method, in which the preheating section 46 and preheating section 47 of the carbon heater 41 are controlled by the distance from the wafer 40.

Since single crystal growth occurs from the exposed wafer surface portion 3 exposed around the island oxide film 2, there is a close relationship between the size of the island oxide film 2 and the quality of the single crystal. Although the peripheral part of the film 2 has better crystallinity and a lower defect density, internal stress often remains due to the step difference caused by the oxide film 2. Figure 1
The active elements 32 and 33 shown in (d) have one active element provided on the island-like oxide film 2, and the island-like oxide film 2 has a shape corresponding to the outer shape of the active element. In this case, the density of crystal defects present in the active element can be reduced and the yield can be improved. The active elements 30 and 31 are two active elements arranged on one island-like oxide film, and are effective in improving the degree of integration. Furthermore, in the active element 30, the collector electrode portion is provided at the outer edge of the island-shaped oxide film 2, and the active region immediately below the emitter 16 is arranged at the inner edge, so that the stress due to the step difference in the island-shaped oxide film 2 has no effect on the element characteristics. The impact can be reduced. Furthermore, the active element 31 is arranged avoiding the vicinity of the outer edge of the island-like oxide film, and the same effect can be obtained. Further, by arranging the active elements 32 and 33 on adjacent island-like oxide films, and furthermore on the same island-like oxide film like the active elements 30 and 31, the consistency of device characteristics can be improved. In this case, it is important to arrange the active region, which has an important influence on the device characteristics as described above, in the same relative position as the island-like oxide film in order to obtain better matching.

FIG. 3 is a diagram showing another embodiment of the present invention, and FIG. 3(A) shows a differential amplifier circuit, in which transistors Q1 and Q
2 are placed on the same island region 50, and resistors R1 and R
2 is also arranged on the same island-like oxide film region 51 as described above. This causes transistors Q1, Q2 and resistors R1, R
2 can be obtained, and offset voltage etc. can be reduced. Figure (b) shows an example of a CMOS logic circuit in which PMOS M1 to M3 are arranged on the same island-like oxide film 52 and NMOS M4 to M6 are arranged on the same island-like oxide film 53. , PMOS
Good matching of device characteristics between M1 and M3 and between NMOS M4 and M6 is obtained, and as a result, PMOS and NM
Good consistency between logic gates configured in a pair of OSs can be obtained. FIG. 2C shows an example of an IIL logic gate in which an injector Q1 and an output transistor Q2 are arranged on the same island-like oxide film 54. Further, FIG. 4(D) shows an example of a TTL logic gate, in which an input transistor Q1 and an output transistor Q2 are arranged on the same island-like oxide film 55. By arranging the logic gates on the same island-like oxide film in this way, good consistency in delay time, parasitic capacitance, power consumption, etc. between the logic gates can be obtained, and good results can also be obtained in terms of the degree of integration. It will be done. Furthermore, the shape of the island-like oxide film can be considered over a larger area, improving design efficiency.

FIG. 4 is a diagram showing a third embodiment of the present invention.
Reference numeral 60 indicates an LSI chip, and 61 to 65 indicate functional blocks constructed on the chip 60, such as functional blocks such as an arithmetic unit, a register group, and a memory unit of a microcomputer. 66 is a line indicating the boundary of the island-shaped oxide film, and 67 is a bonding pad. In this way, function block 61~
By matching the outer shape of the island oxide film 65 with the outer shape of the island oxide film, a higher degree of integration can be obtained without reducing the yield. Furthermore, the outer shape of the island-like oxide film can be designed in units of functional blocks, which further improves design efficiency.

FIG. 5 is a diagram showing a fourth embodiment of the present invention.
70 is an LSI chip, 71 is a boundary between island-like oxide films, and 72 is a bonding pad. By arranging all the elements on the same chip on the same island-shaped oxide film in this way, the best degree of integration and design efficiency can be obtained. Note that the present invention does not include forming a hole in the island-like oxide film 2 to provide an electrically conductive portion with the element surface for connection with the potential of the substrate 1 or wiring provided under the island-like oxide film 2. does not become an obstacle.

FIG. 6 is a diagram showing a fifth embodiment of the present invention.
The same reference numerals as in FIG. 1 indicate the same components. In Figure 5, 3
4 and 35 are element regions, 10' is a field oxide film, and 81
89 is wiring made of aluminum or the like. In the figure, only the first layer wiring is shown, and the second or third layer wiring provided with an insulating material in between is omitted.

In the structure of FIG. 6, the epitaxial layer 8'
The polysilicon layer 11' is surrounded by an oxide film and is insulated. Therefore, the wirings 81 to 85 are conductive parts,
For example, it is in contact with the substrate 1 or the element region 34 through the extremely thick dielectric field oxide film 10', polysilicon 11', and oxide film 10, and the parasitic capacitance therebetween is extremely small. Almost the same thing can be said about the wirings 86 to 89, but the epitaxial layer 8' has conductivity and has a slightly larger parasitic capacitance than the former.

By providing a thick dielectric region in this manner and using its upper surface as a wiring region for passing relatively long wires, the parasitic capacitance of the wiring can be significantly reduced, and the logic gate The delay time between analog circuits or between analog circuits can be reduced. This effect is particularly noticeable in MOS or CMOS structures with low driving capability.

In the first to fifth embodiments above, the insulating film portion has been described as an oxide film, but it may also be made of other materials, such as a nitride film, or a composite film of two or more layers of different materials. good.

[0024] Also, in the manufacturing method using the ion implantation method in which an island-like oxide film is formed by implanting oxygen ions into a silicon single crystal, there is a similar problem that existed before the present invention due to the volume expansion of the oxide film layer. The present invention can also be applied to a semiconductor device having an SOI structure manufactured by a manufacturing method.

According to this embodiment, since a wiring area is provided that is separated from the conductive part by a thick dielectric material, it is possible to reduce the parasitic capacitance of the wiring, especially in long wiring such as microcomputers, memories, or gate arrays. This is highly effective in LSIs where wiring exists, and enables high-speed operation.

[0026]

As described above, according to the present invention, a semiconductor device capable of high-speed operation can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a manufacturing method of an apparatus to which the present invention is applied.

FIG. 3 is a diagram showing another embodiment of the present invention.

FIG. 4 is a diagram showing another embodiment of the present invention.

FIG. 5 is a diagram showing another embodiment of the present invention.

FIG. 6 is a diagram showing another embodiment of the present invention.

FIG. 7 is a plan view corresponding to the cross-sectional view of FIG. 1;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Island-shaped insulating film, 7, 8... Epitaxial layer.

Claims (1)

[Claims] Claims: 1. A single crystal element region provided on one main surface side; a polycrystalline region provided on the one main surface side and surrounded by an insulating film; , and a wiring formed on the upper surface of the polycrystalline region via the insulating film.