JPH04354348A - Insulating film for inspection of semiconductor element and inspection device and inspection method - Google Patents

Insulating film for inspection of semiconductor element and inspection device and inspection method

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Publication number
JPH04354348A
JPH04354348A JP3157491A JP15749191A JPH04354348A JP H04354348 A JPH04354348 A JP H04354348A JP 3157491 A JP3157491 A JP 3157491A JP 15749191 A JP15749191 A JP 15749191A JP H04354348 A JPH04354348 A JP H04354348A
Authority
JP
Japan
Prior art keywords
inspection
insulating film
semiconductor element
testing
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3157491A
Other languages
Japanese (ja)
Inventor
Hitoshi Ishizaka
整 石坂
Kazuo Ouchi
一男 大内
Munekazu Tanaka
田中 宗和
Naoharu Morita
尚治 森田
Masakazu Sugimoto
正和 杉本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nitto Denko Corp
Original Assignee
Nitto Denko Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nitto Denko Corp filed Critical Nitto Denko Corp
Priority to JP3157491A priority Critical patent/JPH04354348A/en
Publication of JPH04354348A publication Critical patent/JPH04354348A/en
Pending legal-status Critical Current

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  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To provide an insulating film for inspection of a semiconductor element and an inspecting device and an inspecting method which can solve the theme of a conventional inspecting device wherein a mechanical probe is used, and can perform the inspection of a semiconductor element simply, and can prevent short circuit even in inspection, and can easily perform the matching of impedance, too. CONSTITUTION:A semiconductor element is placed on an inspection circuit 5 and is connected by inserting a metallic projection in this through hole 4, using an insulating film 3 where a through hole 4 in which to insert the metallic projection 2 of the semiconductor element 1, and then it is inspected whether the semiconductor element is good or bad.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は半導体素子を検査するた
めの絶縁フィルムおよび半導体素子の検査装置ならびに
検査方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulating film for testing semiconductor devices, an apparatus for testing semiconductor devices, and a method for testing semiconductor devices.

【0002】0002

【従来の技術】近年、電子機器の発達によって半導体装
置を多く用いるデバイスや機器は、小型薄型化や軽量化
に伴い、半導体素子を一定面積の基板上に高密度実装す
る必要がある。そこで、用いる半導体素子は従来のよう
な素子周縁部に電極パッドを有するものではなく、素子
内面にもパッドを形成した所謂、エリアチップが開発さ
れている。
2. Description of the Related Art In recent years, with the development of electronic equipment, devices and equipment that use many semiconductor devices have become smaller, thinner, and lighter, and as a result, it is necessary to mount semiconductor elements at a high density on a substrate of a certain area. Therefore, a so-called area chip has been developed in which the semiconductor device used does not have electrode pads on the periphery of the device as in conventional devices, but pads are also formed on the inner surface of the device.

【0003】従来、半導体素子の検査には針式のメカニ
カルプローブが用いられているが、高密度の半導体素子
に対しては1万〜2万回の接触回数の寿命しかなく、ま
た、針を挟むブレードと針が簡単に位置ずれを起こした
り、曲がったり、短絡したりして検査できなくなること
がある。特に、上記高密度のエリアチップに対しては針
の配置が不可能に近い。さらに、メカニカルプローブで
は検査の際、針の接触部に大きな応力がかかるので、半
導体素子上の金属突起に針やブレードが刺さり、検査中
に金属突起が損傷して不良品を作りだすこともある。ま
た、針自体でインピーダンスの整合を行うことが困難で
あるので、複雑な検査回路構造を採ることができないも
のである。
Conventionally, needle-type mechanical probes have been used to test semiconductor devices, but they have a lifespan of only 10,000 to 20,000 contacts for high-density semiconductor devices, and The pinching blade and needle can easily become misaligned, bent, or short-circuited, making inspection impossible. In particular, it is almost impossible to arrange needles for the above-mentioned high-density area chips. Furthermore, with mechanical probes, large stress is applied to the contact area of the needle during inspection, so the needle or blade may pierce the metal protrusions on the semiconductor element, damaging the metal protrusions during inspection and producing defective products. Further, since it is difficult to perform impedance matching using the needle itself, a complicated test circuit structure cannot be adopted.

【0004】0004

【発明が解決しようとする課題】本発明は上記従来のメ
カニカルプローブを用いた半導体素子の検査における種
々の課題を解決し、半導体素子の電極部(被検査部)と
検査回路とを比較的簡単に位置合わせでき、しかも検査
時に好ましくない短絡や損傷をなくした検査システムを
提供することを目的としてなされたものである。
[Problems to be Solved by the Invention] The present invention solves various problems in testing semiconductor devices using the above-mentioned conventional mechanical probe, and makes it possible to relatively easily inspect the electrode section (tested section) of the semiconductor device and the inspection circuit. The purpose of this invention is to provide an inspection system that can be aligned to the target position and eliminate undesirable short circuits and damage during inspection.

【0005】[0005]

【課題を解決するための手段】そこで、本発明者らは上
記目的を達成するために鋭意検討を重ねた結果、半導体
素子の電極パッド上の金属突起と相対する位置に貫通孔
を設けた絶縁フィルムを用い、この貫通孔に金属突起を
挿入することによって、半導体素子を搬送することがで
き、しかもこの搬送体は検査回路基板上の配線パターン
に載置するだけで、検査回路と金属突起とを精確にかつ
位置合わせして接続できることを見い出し、本発明を完
成するに至った。
[Means for Solving the Problems] In order to achieve the above object, the inventors of the present invention have made extensive studies and have developed an insulator with a through hole in a position facing a metal protrusion on an electrode pad of a semiconductor element. Semiconductor elements can be transported by using a film and inserting metal protrusions into the through holes.Moreover, by simply placing this carrier on the wiring pattern on the test circuit board, the test circuit and the metal protrusions can be transferred. The present invention was completed based on the discovery that it is possible to accurately and align the connections.

【0006】即ち、本発明は半導体素子の電極パッド上
の金属突起を挿入しうる貫通孔が形成されており、かつ
該金属突起の高さよりも小さい厚みを有することを特徴
とする半導体素子検査用絶縁フィルムの提供と、これを
用いて半導体素子を検査回路上に搬送して検査回路と接
続を行う検査方法の提供、ならびに上記絶縁フィルムの
片面に半導体素子を検査するための回路が形成されてい
る検査装置の提供と、これに半導体素子を載置して検査
回路と接続を行う検査方法の提供を行うものである。
That is, the present invention provides a semiconductor device for testing semiconductor devices characterized by having a through hole into which a metal protrusion on an electrode pad of a semiconductor device can be inserted, and having a thickness smaller than the height of the metal protrusion. The present invention provides an insulating film, a testing method using the insulating film to transport a semiconductor device onto a test circuit and connecting it to the test circuit, and a circuit for testing the semiconductor device formed on one side of the insulating film. The purpose of the present invention is to provide a testing device including a semiconductor device, and a testing method in which a semiconductor element is placed on the testing device and connected to a testing circuit.

【0007】[0007]

【実施例】以下に本発明の実施例を図面を用いて具体的
に説明する。
EXAMPLES Examples of the present invention will be explained in detail below with reference to the drawings.

【0008】図1は本発明の半導体素子検査用絶縁フィ
ルムを用いて半導体素子を搬送、検査回路へ接続する工
程を説明するための断面図であり、図2は本発明の絶縁
性フィルムの貫通孔に半導体素子の金属突起を挿入、載
置して搬送する際の状態の断面図、図3はこの搬送体を
検査回路に位置合わせして、加圧プレスによって接続し
た状態を示す断面図である。
FIG. 1 is a cross-sectional view for explaining the process of transporting a semiconductor device and connecting it to a test circuit using the insulating film for testing semiconductor devices of the present invention, and FIG. A cross-sectional view of the state in which a metal protrusion of a semiconductor element is inserted into a hole, placed, and transported. Figure 3 is a cross-sectional view showing a state in which this transport body is aligned with a test circuit and connected by a pressure press. be.

【0009】図1において半導体素子1の電極パッド(
図示省略)には半田、金、銀、銅、などの材料からなる
金属突起2が、高さ10〜200μm程度、径(幅)1
0〜500μm程度の大きさにて形成されており、半導
体素子1はこの金属突起2によって検査回路(配線パタ
ーン)5に接続、固定される。本発明の半導体素子検査
用の絶縁フィルム3は図1に示すように、半導体素子1
が有する金属突起2と相対する位置に該突起2を挿入で
きる貫通孔4を有するものである。また、絶縁フィルム
3の厚みは金属突起2の高さよりも小さく、従って、貫
通孔4に金属突起2を挿入して搬送状態の時には、図2
に示すように絶縁性フィルム3の半導体素子載置面とは
反対の面の貫通孔部から僅かに金属突起2が突出する。
In FIG. 1, the electrode pads (
(not shown) has a metal protrusion 2 made of material such as solder, gold, silver, copper, etc., with a height of about 10 to 200 μm and a diameter (width) of 1
The metal protrusions 2 are formed to have a size of about 0 to 500 μm, and the semiconductor element 1 is connected and fixed to the test circuit (wiring pattern) 5 by the metal protrusions 2 . As shown in FIG. 1, the insulating film 3 for semiconductor device inspection of the present invention
It has a through hole 4 into which the protrusion 2 can be inserted at a position opposite to the metal protrusion 2 that the metal protrusion 2 has. Further, the thickness of the insulating film 3 is smaller than the height of the metal protrusion 2, and therefore, when the metal protrusion 2 is inserted into the through hole 4 and is being transported, as shown in FIG.
As shown in FIG. 2, a metal protrusion 2 slightly protrudes from a through-hole portion on the surface of the insulating film 3 opposite to the surface on which the semiconductor element is placed.

【0010】また、上記絶縁フィルム3には検査回路の
所定位置(配線パターン5)への位置合わせを精確に行
うために、貫通孔4と相関位置にある位置合わせ用のア
ライメントマーク9が公知の手段にて設けられており、
位置合わせ時にカメラなどで確認しながら確実に載置、
固定することができる。さらに、位置合わせ用の貫通孔
4’を穿孔加工などの手段にて設けることもでき、検査
によって不良と判定された半導体素子1にマーキングを
するための窓6を設けておくこともできる。
In addition, the insulating film 3 is provided with a well-known alignment mark 9 at a position relative to the through hole 4 in order to accurately align the test circuit to a predetermined position (wiring pattern 5). It is provided by means,
Place it securely while checking with a camera etc. when aligning.
Can be fixed. Furthermore, a through hole 4' for positioning may be provided by drilling or other means, and a window 6 may be provided for marking a semiconductor element 1 determined to be defective by inspection.

【0011】本発明では半導体素子1は図2に示すよう
に、絶縁フィルム3に載置されるが、絶縁フィルム3は
長尺状にして複数個の半導体素子1を連続して搬送する
ことができる。このように長尺状とすることによって、
半導体装置の検査工程において連続的に半導体素子を供
給することができ、検査効率の向上が図れるものである
In the present invention, the semiconductor element 1 is placed on an insulating film 3 as shown in FIG. can. By making it long like this,
Semiconductor elements can be continuously supplied in a semiconductor device testing process, and testing efficiency can be improved.

【0012】検査回路5に接続された半導体素子1は、
図3に示すように加圧プレス7によって確実に検査回路
に接続される。このとき絶縁フィルム3を間に介在させ
ているので半導体素子1と検査回路5の間は一定距離に
維持でき、しかも各金属突起2の間も絶縁フィルム3が
壁材的に作用して確実に絶縁されているので短絡を生じ
ることがない。
The semiconductor element 1 connected to the test circuit 5 is
As shown in FIG. 3, the pressure press 7 securely connects the test circuit. At this time, since the insulating film 3 is interposed between them, the distance between the semiconductor element 1 and the test circuit 5 can be maintained at a constant distance, and the insulating film 3 acts like a wall material between each metal protrusion 2 to ensure reliable Since it is insulated, there will be no short circuit.

【0013】本発明にて用いる絶縁フィルム3は、電気
絶縁特性を有するものであればその材質に制限はなく、
例えばポリエステル系樹脂、エポキシ系樹脂、ウレタン
系樹脂、ポリスチレン系樹脂、ポリエチレン系樹脂、ポ
リアミド系樹脂、ポリイミド系樹脂、ABS樹脂、ポリ
カーボネート樹脂、シリコーン系樹脂、フッ素樹脂など
熱硬化性樹脂や熱可塑性樹脂を問わず用いることができ
る。これらの材料のうち耐熱性や機械的強度の点からは
ポリイミド系樹脂を用いることが好ましい。
The material of the insulating film 3 used in the present invention is not limited as long as it has electrical insulating properties.
For example, thermosetting resins and thermoplastic resins such as polyester resins, epoxy resins, urethane resins, polystyrene resins, polyethylene resins, polyamide resins, polyimide resins, ABS resins, polycarbonate resins, silicone resins, and fluorine resins. It can be used regardless of. Among these materials, polyimide resin is preferably used from the viewpoint of heat resistance and mechanical strength.

【0014】上記絶縁フィルム3に形成される貫通孔4
は、半導体素子1の金属突起2の孔4内への挿入、半導
体素子1の搬送および検査回路5への接続、固定に重要
なものであって、孔径は金属突起2の径の100〜50
0%(約100〜500μm)、好ましくは120〜2
00%(約120〜200μm)、貫通孔の深さ(フィ
ルム厚)は金属突起2の高さの5〜200%(約5〜2
00μm)、好ましくは50〜90%程度(約50〜9
0μm)とする。貫通孔4の形成には機械加工やレーザ
ー加工、光加工、化学エッチング法などが採用でき、加
工精度やエッチングファクター(小テーパー角)などの
点からはエキシマレーザー照射によるハーフエッチング
や穿孔加工が好ましい。
Through holes 4 formed in the insulating film 3
is important for inserting the metal protrusion 2 of the semiconductor element 1 into the hole 4, transporting the semiconductor element 1, and connecting and fixing the semiconductor element 1 to the inspection circuit 5, and the hole diameter is 100 to 50% of the diameter of the metal protrusion 2.
0% (approximately 100-500 μm), preferably 120-2
00% (approximately 120 to 200 μm), and the depth of the through hole (film thickness) is 5 to 200% (approximately 5 to 200 μm) of the height of the metal protrusion 2.
00 μm), preferably about 50 to 90% (about 50 to 9
0 μm). Mechanical processing, laser processing, optical processing, chemical etching methods, etc. can be used to form the through hole 4, and half etching or perforation processing using excimer laser irradiation is preferable from the viewpoint of processing accuracy and etching factor (small taper angle). .

【0015】図4は本発明の半導体素子検査用絶縁フィ
ルムの他の実施例を示す断面図であり、絶縁フィルム3
の半導体素子1載置面と反対の面に検査回路5への仮固
定用の接着剤層7が形成されている。このように接着剤
層7を形成しておくことによって、検査回路5への載置
や加圧プレス7による接続時の位置ずれを確実に防止す
ることができるのである。
FIG. 4 is a sectional view showing another embodiment of the insulating film for testing semiconductor devices according to the present invention.
An adhesive layer 7 for temporary fixing to the test circuit 5 is formed on the surface opposite to the surface on which the semiconductor element 1 is placed. By forming the adhesive layer 7 in this way, it is possible to reliably prevent misalignment when placing the test circuit 5 on the test circuit 5 or connecting it with the pressure press 7.

【0016】また、本発明では図5に示すように、前記
絶縁フィルム3には積層手段や、金属層と絶縁フィルム
との二層基板のパターン加工手段などによって、予め検
査回路5を形成して検査装置としておくことが実用上好
ましい。図5のような検査装置としておくことによって
、半導体素子1を載置、接続するだけで簡単に検査を行
うことができる。この場合、検査回路5は通常のフォト
エッチング加工できるので、インピーダンスの整合を容
易にとることができるものである。さらに、本発明の検
査装置の検査回路面にクロム、タングステン、ロジウム
またはこれらの合金からなる電気接点層(図示、省略)
を0.1〜100μm程度の厚みに形成しておくことが
好ましい。このように電気接点層を設けることによって
、検査装置の寿命を大幅に向上させることができ、さら
に、金属突起2に生じる酸化膜のカスによる汚染も防止
することができる。
Further, in the present invention, as shown in FIG. 5, a test circuit 5 is formed in advance on the insulating film 3 by laminating means or patterning means of a two-layer substrate of a metal layer and an insulating film. It is practically preferable to use it as an inspection device. By using the testing apparatus as shown in FIG. 5, testing can be easily performed by simply placing and connecting the semiconductor element 1. In this case, since the test circuit 5 can be processed by normal photo-etching, impedance matching can be easily achieved. Furthermore, an electrical contact layer (not shown, omitted) made of chromium, tungsten, rhodium, or an alloy thereof is provided on the test circuit surface of the test device of the present invention.
It is preferable to form the layer with a thickness of about 0.1 to 100 μm. By providing the electrical contact layer in this manner, the life of the inspection device can be greatly extended, and furthermore, contamination due to oxide film residue generated on the metal protrusions 2 can be prevented.

【0017】本発明の検査装置は上記のように絶縁性フ
ィルム3の片面に検査回路5を形成してなるものである
が、図6に示すように検査回路5を多層に形成し、積層
された各層を金属などの導電性物質を充填したバイアホ
ール8によって接続することにより、目的に応じた種々
の検査装置を設定することができる。バイアホールは上
記貫通孔形成手段や公知の穿孔手段によって形成するこ
とができる。
The testing device of the present invention has the testing circuit 5 formed on one side of the insulating film 3 as described above, but the testing circuit 5 is formed in multiple layers as shown in FIG. By connecting the layers through via holes 8 filled with a conductive material such as metal, various inspection devices can be set up depending on the purpose. The via hole can be formed by the above-mentioned through hole forming means or a known drilling means.

【0018】[0018]

【発明の効果】本発明は以上のように半導体素子の電極
パッド上の金属突起を挿入しうる貫通孔を形成した絶縁
フィルムを用い、これによって半導体素子を搬送および
検査回路への接続を行っているので、半導体素子の搬送
が検査が簡便となり、しかも接続部分への位置合わせを
容易に行うことができるものである。
[Effects of the Invention] As described above, the present invention uses an insulating film in which through-holes are formed into which metal protrusions on the electrode pads of semiconductor elements can be inserted, and thereby the semiconductor elements are transported and connected to a test circuit. Therefore, it is easy to transport and inspect the semiconductor device, and it is also easy to align the semiconductor device to the connecting portion.

【0019】また、上記絶縁フィルムを介して半導体素
子を検査回路に接続するので、半導体素子と検査回路間
や各電極パッド間の絶縁を確実にでき短絡が防止できる
のである。さらに、検査回路を有する検査装置の場合は
インピーダンスの整合が容易であり、高周波特性を有す
る半導体素子の検査が簡単に行え、また検査回路を多層
化することによって多価密度タイプ、エリアタイプの半
導体素子にも充分に適用できるものである。
Furthermore, since the semiconductor element is connected to the test circuit through the insulating film, insulation between the semiconductor element and the test circuit and between each electrode pad can be ensured, and short circuits can be prevented. Furthermore, in the case of test equipment with a test circuit, impedance matching is easy, and semiconductor devices with high frequency characteristics can be tested easily. It can also be fully applied to devices.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】  本発明の半導体素子検査用絶縁フィルムを
用いて半導体素子を搬送、検査する工程を説明するため
の断面図である。
FIG. 1 is a cross-sectional view for explaining a process of transporting and testing a semiconductor device using the insulating film for semiconductor device testing of the present invention.

【図2】  図1に示す絶縁フィルムに半導体素子を載
置して搬送する状態の断面図である。
FIG. 2 is a cross-sectional view of a state in which a semiconductor element is placed on the insulating film shown in FIG. 1 and transported.

【図3】  検査回路に半導体素子を接続した状態を示
す断面図である。
FIG. 3 is a cross-sectional view showing a state in which a semiconductor element is connected to a test circuit.

【図4】  本発明の絶縁フィルムの他の実施例を示す
断面図である。
FIG. 4 is a sectional view showing another example of the insulating film of the present invention.

【図5】  本発明の検査装置の実施例を示す断面図で
ある。
FIG. 5 is a sectional view showing an embodiment of the inspection device of the present invention.

【図6】  本発明の検査装置の他の実施例を示す断面
図である。
FIG. 6 is a sectional view showing another embodiment of the inspection device of the present invention.

【符号の説明】[Explanation of symbols]

1  半導体素子 2  金属突起 3  絶縁フィルム 4  貫通孔 5  検査回路 7  接着剤層 1 Semiconductor element 2 Metal protrusion 3 Insulating film 4 Through hole 5 Test circuit 7 Adhesive layer

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】  半導体素子の電極パッド上の金属突起
を挿入しうる貫通孔が形成されており、かつ該金属突起
の高さよりも小さい厚みを有することを特徴とする半導
体素子検査用絶縁フィルム。
1. An insulating film for testing semiconductor devices, characterized in that a through hole is formed into which a metal protrusion on an electrode pad of a semiconductor element can be inserted, and the film has a thickness smaller than the height of the metal protrusion.
【請求項2】  半導体素子検査用絶縁フィルムの片面
に検査回路への仮固定用の接着剤層が形成されてなる請
求項1記載の半導体素子検査用絶縁フィルム。
2. The insulating film for testing semiconductor devices according to claim 1, wherein an adhesive layer for temporary fixing to a test circuit is formed on one side of the insulating film for testing semiconductor devices.
【請求項3】  請求項1記載の絶縁フィルムの片面に
半導体素子を検査するための回路が形成されている検査
装置。
3. An inspection device comprising a circuit for inspecting a semiconductor element formed on one side of the insulating film according to claim 1.
【請求項4】  検査回路面にクロム、タングステン、
ロジウムまたはこれらの合金からなる電気接点層を形成
してなる請求項3記載の検査装置。
[Claim 4] Chromium, tungsten,
4. The inspection device according to claim 3, further comprising an electrical contact layer made of rhodium or an alloy thereof.
【請求項5】  請求項3または4記載の検査装置の貫
通孔に半導体素子の電極パッド上の金属突起を挿入して
、検査回路と金属突起を接続することを特徴とする検査
方法。
5. An inspection method comprising the step of inserting a metal protrusion on an electrode pad of a semiconductor element into the through hole of the inspection apparatus according to claim 3 or 4, and connecting the inspection circuit and the metal protrusion.
【請求項6】  請求項1または2記載の半導体素子検
査用絶縁フィルムの貫通孔に半導体素子の電極パッド上
の金属突起を挿入した状態で、半導体素子の検査回路上
へ搬送、接続し、検査回路と上記金属突起を接続するこ
とを特徴とする検査方法。
6. The insulating film for semiconductor device testing according to claim 1 or 2, with the metal projections on the electrode pads of the semiconductor device inserted into the through holes, is transported onto the testing circuit of the semiconductor device, connected, and tested. An inspection method characterized by connecting a circuit and the metal protrusion.
JP3157491A 1991-05-31 1991-05-31 Insulating film for inspection of semiconductor element and inspection device and inspection method Pending JPH04354348A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3157491A JPH04354348A (en) 1991-05-31 1991-05-31 Insulating film for inspection of semiconductor element and inspection device and inspection method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3157491A JPH04354348A (en) 1991-05-31 1991-05-31 Insulating film for inspection of semiconductor element and inspection device and inspection method

Publications (1)

Publication Number Publication Date
JPH04354348A true JPH04354348A (en) 1992-12-08

Family

ID=15650852

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3157491A Pending JPH04354348A (en) 1991-05-31 1991-05-31 Insulating film for inspection of semiconductor element and inspection device and inspection method

Country Status (1)

Country Link
JP (1) JPH04354348A (en)

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