JPH04354122A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH04354122A
JPH04354122A JP12806291A JP12806291A JPH04354122A JP H04354122 A JPH04354122 A JP H04354122A JP 12806291 A JP12806291 A JP 12806291A JP 12806291 A JP12806291 A JP 12806291A JP H04354122 A JPH04354122 A JP H04354122A
Authority
JP
Japan
Prior art keywords
window
insulating film
contact window
poly
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP12806291A
Other languages
Japanese (ja)
Inventor
Kenichi Kawabata
健一 川端
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP12806291A priority Critical patent/JPH04354122A/en
Publication of JPH04354122A publication Critical patent/JPH04354122A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE:To stably form an upward expanding sectional shape of a contact window without using control etching, regarding a method of forming a contact window to a substratum in a multilayered constitution insulating layer composed of a plurality of insulating films formed in order on the substratum. CONSTITUTION:By etching wherein masks 7B, 8B are arranged at each time of forming insulating films 2, 3, windows 2b, 3b exposing a substratum 1 in a contact window forming part are formed in the following manner. The window 2b to be formed in the insulating film 2 whose formation order is n-th (first in figure) is so constituted that the window 3b to be formed in the (n+1)th (second in figure) insulating film 3 is contained in the almost flat region of the insulating film 3 in the region of the window 2b so as to have margin. The window 3b to be formed in the insulating film 3 whose formation order is last is constituted so as to have a size conformed to the bottom part of a contact window 5.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、半導体装置の製造方法
に係り、特に、下地上に順次に形成される複数の絶縁膜
からなる多層構成絶縁層に該下地へのコンタクト窓を形
成する方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a contact window to a base in a multilayer insulating layer consisting of a plurality of insulating films sequentially formed on the base. Regarding.

【0002】半導体装置の製造では、上記多層構成絶縁
層にコンタクト窓を形成する場合がある。その場合は、
絶縁層の厚さ増大によりコンタクト窓が深くなるので、
絶縁層上に形成する電極のステップカバレージを確保す
るため、コンタクト窓の断面形状を上方拡がりにするこ
とが望まれる。
[0002] In the manufacture of semiconductor devices, contact windows are sometimes formed in the multilayer insulating layer. In that case,
As the contact window becomes deeper due to the increase in the thickness of the insulating layer,
In order to ensure step coverage of the electrode formed on the insulating layer, it is desirable that the cross-sectional shape of the contact window expands upward.

【0003】0003

【従来の技術】図3は、上記多層構成絶縁層に上記コン
タクト窓を形成する際の従来方法を説明するための工程
順断面図であり、絶縁膜の数が2の場合を示す。図中、
1は下地、2は第1絶縁膜、3 は第2絶縁膜、4は第
1絶縁膜2及び第2絶縁膜3からなる多層構成絶縁層、
5はコンタクト窓、6は電極、である。
2. Description of the Related Art FIGS. 3A and 3B are cross-sectional views showing a conventional method for forming the contact window in the multilayer insulating layer, in order of steps, and show a case in which the number of insulating films is two. In the figure,
1 is a base, 2 is a first insulating film, 3 is a second insulating film, 4 is a multilayer insulating layer consisting of the first insulating film 2 and the second insulating film 3;
5 is a contact window, and 6 is an electrode.

【0004】先ず、図3(a) のように下地1上に第
1絶縁膜2を形成し、その上にマスク7Aを設けて第1
絶縁膜2をエッチングし、図3(b) のように第1絶
縁膜2にコンタクト窓の底部に見合った大きさの窓2a
を明ける。窓2aは下地1を表出させる。
First, as shown in FIG. 3(a), a first insulating film 2 is formed on a base 1, and a mask 7A is provided on the first insulating film 2.
The insulating film 2 is etched, and a window 2a of a size corresponding to the bottom of the contact window is formed in the first insulating film 2 as shown in FIG. 3(b).
Open the day. The window 2a exposes the base 1.

【0005】次いで、図3(c) のように窓2a領域
を含む第1絶縁膜2上に第2絶縁膜3を形成して多層構
成絶縁層4が形成され、その上にマスク8Aを設けて第
2絶縁膜3をエッチングし、図3(d) のように第2
絶縁膜3に孔2aより大きな窓3aを明ける。その際、
窓2a内の第2絶縁膜3を除去して下地1を再び表出さ
せるが、窓2aの周囲に表出する第1絶縁膜2をできる
だけ除去しないようにする。これにより、断面形状を上
方拡がりにしたコンタクト窓5が形成される。
Next, as shown in FIG. 3(c), a second insulating film 3 is formed on the first insulating film 2 including the window 2a region to form a multilayer insulating layer 4, and a mask 8A is provided thereon. Then, the second insulating film 3 is etched, and the second insulating film 3 is etched as shown in FIG. 3(d).
A window 3a larger than the hole 2a is formed in the insulating film 3. that time,
The second insulating film 3 within the window 2a is removed to expose the base 1 again, but the first insulating film 2 exposed around the window 2a is not removed as much as possible. As a result, a contact window 5 whose cross-sectional shape expands upward is formed.

【0006】従って、多層構成絶縁層4上に形成されて
コンタクト窓5を介し下地1に接続する電極6は、図3
(e) のようにコンタクト窓5のステップカバレージ
が確保される。
Therefore, the electrode 6 formed on the multilayer insulating layer 4 and connected to the base 1 through the contact window 5 is as shown in FIG.
Step coverage of the contact window 5 is ensured as shown in (e).

【0007】[0007]

【発明が解決しようとする課題】しかしながら、上述し
た従来方法は、第2絶縁膜3に窓3aを明けるエッチン
グの際に、第1絶縁膜2がエッチングストッパとなり得
ない場合が多いため、第1絶縁膜2をオーバエッチング
させないようにエッチング停止を見込みで行うコントロ
ールエッチングが必要である。このことは、コンタクト
窓5の断面形状を不安定にさせる問題があり、電極6の
形状に大きく影響を与えていた。
[Problems to be Solved by the Invention] However, in the above-mentioned conventional method, the first insulating film 2 often cannot act as an etching stopper during etching to open the window 3a in the second insulating film 3. Control etching is required to prevent the insulating film 2 from being over-etched, in which the etching is stopped in anticipation. This has the problem of making the cross-sectional shape of the contact window 5 unstable, which greatly affects the shape of the electrode 6.

【0008】そこで本発明は、半導体装置の製造方法に
係り、特に、上述のように多層構成絶縁層にコンタクト
窓を形成する方法に関し、コントロールエッチングを用
いないでコンタクト窓の上方拡がりにする断面形状を安
定に形成することができる方法の提供を目的とする。
Therefore, the present invention relates to a method of manufacturing a semiconductor device, and in particular, to a method of forming a contact window in a multilayer insulating layer as described above, the present invention relates to a method of forming a contact window in a multilayer insulating layer as described above, and a cross-sectional shape of the contact window that expands upward without using controlled etching. The purpose of the present invention is to provide a method that can stably form .

【0009】[0009]

【課題を解決するための手段】図1は本発明の原理を説
明するための工程順断面図であり、従来例を説明した図
3に対応している。従って、従来例の場合と同様に絶縁
膜の数が2の場合を示し、図中、図3と同一符号は同一
対象物を示す。
[Means for Solving the Problems] Fig. 1 is a process-order sectional view for explaining the principle of the present invention, and corresponds to Fig. 3 illustrating a conventional example. Therefore, as in the case of the conventional example, the case where the number of insulating films is two is shown, and in the figure, the same reference numerals as in FIG. 3 indicate the same objects.

【0010】図1を参照して、上記目的を達成するため
に、本発明による半導体装置の製造方法は、下地1上に
順次に形成される複数の絶縁膜2,3からなる多層構成
絶縁層4に下地1へのコンタクト窓5を形成するに際し
て、各絶縁膜2,3の形成毎にマスク7B, 8Bを設
けたエッチングにより該コンタクト窓形成部に下地1を
表出させる窓2b、3bを明け、且つ、形成順番がn番
目(図では1番目)の絶縁膜2に明ける窓2bは、n+
1番目(図では2番目)の絶縁膜3に明ける窓3bが、
前者の窓2bの領域内における後者の絶縁膜3のほぼ平
坦な領域に余裕を残して収まる大きさにすることを特徴
としている。
Referring to FIG. 1, in order to achieve the above object, the method for manufacturing a semiconductor device according to the present invention includes a multilayer insulating layer consisting of a plurality of insulating films 2 and 3 sequentially formed on a base 1. 4, when forming the contact window 5 to the base 1, windows 2b and 3b are formed to expose the base 1 in the contact window forming portion by etching using masks 7B and 8B for each insulating film 2 and 3 formed. The window 2b opened in the insulating film 2 whose formation order is nth (first in the figure) is n+
The window 3b opened in the first (second in the figure) insulating film 3 is
It is characterized by having a size that fits within the region of the former window 2b in a substantially flat region of the latter insulating film 3 with some margin left.

【0011】そして、前記形成順番が最終番目(図では
2番目)の絶縁膜3に明ける窓3bは、コンタクト窓5
の底部に合わせた大きさにすれば良い。
The window 3b opened in the insulating film 3 which is the last in the formation order (the second in the figure) is the contact window 5.
It should be sized to match the bottom of the.

【0012】0012

【作用】上記の構成によれば、絶縁膜3に明ける窓3b
が絶縁膜2に明けた窓2bの領域内において絶縁膜3の
上記ほぼ平坦な領域に余裕を残して収まるようにしてあ
るので、コントロールエッチングが不要となり、コンタ
クト窓の上方拡がりにする断面形状を安定に形成するこ
とが可能である。
[Operation] According to the above structure, the window 3b opened in the insulating film 3
Since the area of the window 2b opened in the insulating film 2 is made to fit within the above-mentioned almost flat area of the insulating film 3 with a margin, control etching is not required, and the cross-sectional shape of the contact window is made to expand upward. It is possible to form it stably.

【0013】そして窓3bの大きさをコンタクト窓5の
底部に合わせることにより、コンタクト窓5の底部の大
きさを確保することができる。上述の説明は2または3
で示される絶縁膜の数が2の場合であるが、その数が3
以上になっても同様にすることにより所望のコンタクト
窓を安定に形成することができる。
By matching the size of the window 3b to the bottom of the contact window 5, the size of the bottom of the contact window 5 can be secured. The above explanation is 2 or 3
In this case, the number of insulating films shown by is 2, but if the number is 3
Even in the above cases, a desired contact window can be stably formed by doing the same.

【0014】[0014]

【実施例】以下本発明によるコンタクト窓の形成を適用
した半導体装置の製造の実施例について図2の工程順断
面図を用いて説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An example of manufacturing a semiconductor device to which contact window formation according to the present invention is applied will be described below with reference to step-by-step cross-sectional views of FIG.

【0015】この実施例は、半導体装置がバイポーラト
ランジスタとポリSi配線及びそれと同一層のポリSi
抵抗素子を有し、ポリSi配線の抵抗低減にシリサイド
を導入するため、ポリSi抵抗素子へのコンタクト窓を
形成する絶縁層が多層構成となったものである。
In this embodiment, the semiconductor device includes a bipolar transistor, a poly-Si wiring, and a poly-Si wiring in the same layer.
It has a resistive element, and in order to introduce silicide to reduce the resistance of the poly-Si wiring, the insulating layer forming the contact window to the poly-Si resistive element has a multilayer structure.

【0016】図2において、図2(a) はSi基板2
1にバイポーラトランジスタ20及びポリSi抵抗素子
11を形成した状態を示す。図中、22はフィールド酸
化膜、23はベース、24はエミッタ、25はベース引
出し用のポリSi配線、26はエミッタ引出し用のポリ
Si膜、であり、ポリSi抵抗素子11は、フィールド
酸化膜22上にポリSi配線25と同一の層から形成さ
れている。また、ポリSi膜26を分離するためポリS
i配線25及びポリSi抵抗素子11を覆うSiO2絶
縁膜12が設けられている。
In FIG. 2, FIG. 2(a) shows the Si substrate 2.
1 shows a state in which a bipolar transistor 20 and a poly-Si resistance element 11 are formed. In the figure, 22 is a field oxide film, 23 is a base, 24 is an emitter, 25 is a poly-Si wiring for leading out the base, 26 is a poly-Si film for leading out the emitter, and the poly-Si resistance element 11 is a field oxide film. The poly-Si wiring 25 is formed on the same layer as the poly-Si wiring 25 . In addition, in order to separate the poly-Si film 26,
An SiO2 insulating film 12 is provided to cover the i-wire 25 and the poly-Si resistance element 11.

【0017】そして、本発明によるコンタクト窓の形成
はポリSi抵抗素子11からの引出し用として行うもの
であり、ポリSi抵抗素子11及びSiO2絶縁膜12
が先に説明した図1の下地1及び第1絶縁膜2に該当す
る。
The contact window according to the present invention is formed to lead out from the poly-Si resistive element 11, and the contact window is formed for the purpose of leading out from the poly-Si resistive element 11 and the SiO2 insulating film 12.
correspond to the base 1 and first insulating film 2 in FIG. 1 described above.

【0018】この後、図1(b) を参照して、マスク
を設けたエッチングによりSiO2絶縁膜12に窓明け
して、ポリSi配線25及びポリSi抵抗素子11を表
出させ、その部分にシリサイド27を形成する。その際
、ポリSi抵抗素子11を表出させる窓12bの大きさ
は図1で説明した窓2bと同様にする。シリサイド27
はポリSi配線26の抵抗を低減させるためのものであ
る。
After this, referring to FIG. 1(b), a window is opened in the SiO2 insulating film 12 by etching with a mask to expose the poly-Si wiring 25 and the poly-Si resistive element 11, and the portion is etched. Silicide 27 is formed. At this time, the size of the window 12b exposing the poly-Si resistive element 11 is made the same as the window 2b explained in FIG. Silicide 27
is for reducing the resistance of the poly-Si wiring 26.

【0019】次いで図1(c) を参照して、CVDに
よりSiO2絶縁膜13を形成する。このSiO2絶縁
膜13は、ポリSi配線25及びポリSi膜26の露出
部を被覆するものであるが、着目するコンタクト窓に関
して見れば図1の第2絶縁膜3に該当する。従って、S
iO2絶縁膜12及び13が図1の多層構成絶縁層4に
該当する多層構成絶縁層14を構成する。
Next, referring to FIG. 1(c), a SiO2 insulating film 13 is formed by CVD. This SiO2 insulating film 13 covers the exposed portions of the poly-Si wiring 25 and the poly-Si film 26, and corresponds to the second insulating film 3 in FIG. 1 with respect to the contact window of interest. Therefore, S
The iO2 insulating films 12 and 13 constitute a multilayer insulating layer 14 corresponding to the multilayer insulating layer 4 in FIG.

【0020】次いで図1(d) を参照して、マスクを
かけたエッチングによりSiO2絶縁膜13に窓明けし
て、ポリSi配線25及びポリSi膜26へのコンタク
ト窓を形成すると共に、ポリSi抵抗素子11へのコン
タクト窓15を形成する。 コンタクト窓15は図1のコンタクト窓5に該当するも
のであり、コンタクト窓15用としてSiO2絶縁膜1
3に明ける窓13b の大きさは図1で説明した窓3b
と同様にする。従って、コンタクト窓15は、多層構成
絶縁層14に形成されるが、SiO2絶縁膜13のエッ
チングにコントロールエッチングが不要であり上方拡が
りの断面形状が安定している。
Next, referring to FIG. 1(d), windows are opened in the SiO2 insulating film 13 by masked etching to form contact windows to the poly-Si wiring 25 and the poly-Si film 26, and the poly-Si A contact window 15 to the resistive element 11 is formed. The contact window 15 corresponds to the contact window 5 in FIG.
The size of window 13b that opens in Figure 3 is the same as window 3b explained in Figure 1.
Do the same as. Therefore, although the contact window 15 is formed in the multilayer insulating layer 14, control etching is not required for etching the SiO2 insulating film 13, and the upwardly expanding cross-sectional shape is stable.

【0021】次いで図1(e) を参照して、ベース2
3に接続する電極28、エミッタ24に接続する電極2
9、ポリSi抵抗素子11に接続する電極16、を一緒
に形成して半導体装置を完成する。ここでは、電極16
が図1の電極6に該当している。
Next, referring to FIG. 1(e), the base 2
Electrode 28 connected to 3, Electrode 2 connected to emitter 24
9. An electrode 16 connected to the poly-Si resistive element 11 is also formed to complete the semiconductor device. Here, the electrode 16
corresponds to the electrode 6 in FIG.

【0022】[0022]

【発明の効果】以上説明したように本発明によれば、半
導体装置の製造方法に係り、特に、下地上に順次に形成
される複数の絶縁膜からなる多層構成絶縁層に該下地へ
のコンタクト窓を形成する方法に関し、コントロールエ
ッチングを用いないでコンタクト窓の上方拡がりにする
断面形状を安定に形成することができる方法が提供され
て、当該コンタクト窓の安定した製造を可能にさせる効
果がある。
As described above, the present invention relates to a method of manufacturing a semiconductor device, and particularly, a method for manufacturing a semiconductor device, in which a multilayer insulating layer consisting of a plurality of insulating films sequentially formed on a base, is provided with a contact to the base. Regarding the method of forming a window, there is provided a method that can stably form a cross-sectional shape that expands upward in a contact window without using controlled etching, and has the effect of enabling stable manufacture of the contact window. .

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】  本発明の原理を説明するための工程順断面
[Fig. 1] Process-order cross-sectional diagram for explaining the principle of the present invention

【図2】  実施例を説明するための工程順断面図[Figure 2] Process order cross-sectional diagram for explaining the example


図3】  従来方法を説明するための工程順断面図
[
Figure 3: Process-order cross-sectional diagram to explain the conventional method

【符号の説明】[Explanation of symbols]

1  下地 2  第1絶縁膜 2a, 2b  第1絶縁膜に明けた窓3  第2絶縁
膜 3a, 3b  第2絶縁膜に明けた窓4  多層構成
絶縁層 5  コンタクト窓 6  電極 7A, 7B, 8A, 8B  窓明けエッチングの
ためのマスク11  ポリSi抵抗素子 (下地) 12  SiO2絶縁膜 (第1絶縁膜)12b   
SiO2絶縁膜 (第1絶縁膜) に明けた窓13  
SiO2絶縁膜 (第2絶縁膜)13b   SiO2
絶縁膜 (第2絶縁膜) に明けた窓14  多層構成
絶縁層 15  ポリSi抵抗素子へのコンタクト窓16  ポ
リSi抵抗素子に接続する電極20  バイポーラトラ
ンジスタ 21  Si基板 22  フィールド酸化膜 23  ベース 24  エミッタ 25  ベース引出し用のポリSi配線26  エミッ
タ引出し用のポリSi膜27  シリサイド 28  ベースに接続する電極 29  エミッタに接続する電極
1 Underlayer 2 First insulating film 2a, 2b Window 3 in first insulating film 3 Second insulating film 3a, 3b Window 4 in second insulating film Multilayer insulating layer 5 Contact window 6 Electrode 7A, 7B, 8A, 8B Mask for window opening etching 11 Poly-Si resistance element (base) 12 SiO2 insulating film (first insulating film) 12b
Window 13 opened in SiO2 insulation film (first insulation film)
SiO2 insulating film (second insulating film) 13b SiO2
Window 14 in the insulating film (second insulating film) Multilayer insulating layer 15 Contact window 16 to the poly-Si resistor element 20 Electrode 20 connected to the poly-Si resistor element Bipolar transistor 21 Si substrate 22 Field oxide film 23 Base 24 Emitter 25 Poly-Si wiring 26 for leading out the base Poly-Si film 27 for leading out the emitter Silicide 28 Electrode 29 connected to the base 29 Electrode connected to the emitter

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】  下地(1) 上に順次に形成される複
数の絶縁膜(2,3) からなる多層構成絶縁層(4)
 に該下地(1) へのコンタクト窓(5) を形成す
るに際して、各絶縁膜(2,3) の形成毎にマスク(
7B,8B) を設けたエッチングにより該コンタクト
窓形成部に該下地(1) を表出させる窓(2b,3b
) を明け、且つ、形成順番がn番目の絶縁膜(2) 
に明ける当該窓(2b)は、n+1番目の絶縁膜(3)
 に明ける当該窓(3b)が、前者の窓(2b)の領域
内における後者の絶縁膜(3) のほぼ平坦な領域に余
裕を残して収まる大きさにすることを特徴とする半導体
装置の製造方法。
[Claim 1] A multilayer insulating layer (4) consisting of a plurality of insulating films (2, 3) sequentially formed on a base (1).
When forming a contact window (5) to the base (1), a mask (
7B, 8B) to expose the base (1) in the contact window forming part by etching (2b, 3b).
) and whose formation order is nth (2)
The window (2b) that opens in is the n+1th insulating film (3)
The manufacturing of a semiconductor device characterized in that the window (3b) opened in the first window (3b) is sized to fit in a substantially flat area of the latter insulating film (3) within the area of the former window (2b) with a margin. Method.
【請求項2】  前記形成順番が最終番目の前記絶縁膜
(3) に明ける前記窓(3b)は、前記コンタクト窓
(5) の底部に合わせた大きさにすることを特徴とす
る請求項1記載の半導体装置の製造方法。
2. The window (3b) formed in the insulating film (3) that is last in the formation order is sized to match the bottom of the contact window (5). A method of manufacturing the semiconductor device described above.
JP12806291A 1991-05-31 1991-05-31 Manufacture of semiconductor device Withdrawn JPH04354122A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12806291A JPH04354122A (en) 1991-05-31 1991-05-31 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12806291A JPH04354122A (en) 1991-05-31 1991-05-31 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH04354122A true JPH04354122A (en) 1992-12-08

Family

ID=14975534

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12806291A Withdrawn JPH04354122A (en) 1991-05-31 1991-05-31 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH04354122A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005317932A (en) * 2004-03-29 2005-11-10 Yamaha Corp Semiconductor device and its manufacturing method
US7728423B2 (en) 2004-03-29 2010-06-01 Yamaha Corporation Semiconductor device having step-wise connection structures for thin film elements

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005317932A (en) * 2004-03-29 2005-11-10 Yamaha Corp Semiconductor device and its manufacturing method
US7728423B2 (en) 2004-03-29 2010-06-01 Yamaha Corporation Semiconductor device having step-wise connection structures for thin film elements
US8008127B2 (en) 2004-03-29 2011-08-30 Yamaha Corporation Method of fabricating an integrated circuit having a multi-layer structure with a seal ring

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