JPH04352366A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce the frequency of the scattering of impurities of conductive carriers in a channel region and to restrain a drop in a mobility due to the scattering of the impurities of the conductive carriers by a method wherein one part of a single-crystal first-conductivity-type semiconductor substrate at a low impurity concentration is used as the surface of the channel region coming into contact with a gate insulating film. CONSTITUTION:N-type impurities are implanted deep into a P-type semiconductor substrate 1 by a high-energy ion implantation method; an N-type well 2 is formed. Part of the P-type semiconductor substrate 1 is left on the N-type well 2. The one part, of the P-type semiconductor substrate 1, which has been left on the N-type well 2 is used as a P-type channel region; a gate insulating film 4 and a gate electrode 5 are formed on its surface; and a source-drain region is formed. Since the impurity concentration of the P-type substrate 1 is low in this manner, the impurity concentration is low even in the P-type channel region using it. Consequently, a drop in a mobility due to the scattering of impurities of conductive carriers and the deterioration of the performance of a device itself due to it are not caused.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a buried channel type P-type MIS semiconductor device formed in an N-type well on a P-type semiconductor substrate.

0002

2. Description of the Related Art FIG. 3 is a sectional view showing a conventional semiconductor device. In the figure, 1 is a P-type semiconductor substrate, 2 is a P-type semiconductor substrate, and 2 is a P-type semiconductor substrate.
3 is an N-type well formed by implanting impurities into a type semiconductor substrate; 3 is a P-type channel region formed on the N-type well 2;
4 is a gate insulating film, and a gate electrode 5 is formed on the channel region 3 via this gate insulating film 4. Also,
Reference numeral 6 denotes P-type source/drain diffusion regions provided on both sides of the channel region 3.

Next, a method for manufacturing this semiconductor device will be explained. An N-type well 2 is formed by implanting impurities into a P-type semiconductor substrate 1 . P-type channel region 3 formed by shallowly implanting P-type impurities into the surface of N-type well 2
A gate insulating film 4 is formed on the surface of the gate insulating film 4, and a gate electrode 5 is provided in a predetermined region on the gate insulating film 4. This gate electrode 5
P-type impurities are implanted using the mask as a mask to form source/drain regions 6.

The conventional semiconductor device is constructed as described above, and the P-type channel region 3 is formed by further implanting P-type impurities into the surface of the N-type well 2, which is formed by implanting impurities into the substrate. The impurity distribution in the depth direction in the channel portion of this semiconductor device is as shown in FIG.

[0005]

[Problems to be Solved by the Invention] Since the conventional semiconductor device and its manufacturing method are constructed as described above, a P-type impurity is introduced into the surface of the N-type well 2 to obtain the P-type channel region 3. Therefore, in order to obtain a P-type channel region with an impurity concentration NA on an N-type well with an impurity concentration ND, a P-type impurity with a concentration ND is implanted into the N-type impurity with a concentration ND in the N-type well, and P trying to get
P-type impurity must be implanted in the required concentration NA in the type channel region, i.e., the concentration (ND + NA)
It is necessary to implant P-type impurities. P-type semiconductor substrate 1
The impurity concentration of NA. SUB, the total impurity concentration in the P-type channel region is NA. SUB +ND +(N
D + NA).

[0006] Since the total impurity concentration in the P-type channel region, which is an electrically conductive region, is high as described above, impurity scattering of conduction carriers becomes frequent and the mobility of conduction carriers decreases.
There was a problem that the performance of the semiconductor device deteriorated.

The present invention was made to solve the above-mentioned problems, and provides a high-performance semiconductor device and its semiconductor device that suppresses the decrease in the mobility of conduction carriers by reducing the frequency of impurity scattering of conduction carriers. The purpose is to obtain a manufacturing method.

[0008]

[Means for Solving the Problems] A semiconductor device according to the present invention is formed in a second conductivity type well region in a single crystal first conductivity type semiconductor substrate with a low impurity concentration, and a surface region thereof is formed in a first conductivity type semiconductor substrate.
A semiconductor device comprising a buried channel region of a conductive type and a gate electrode formed through a gate insulating film on the channel region, wherein the surface region of the channel region in contact with the gate insulating film is doped with the low impurity concentration. A part of a single-crystal first conductivity type semiconductor substrate is used.

The method for manufacturing a semiconductor device according to the present invention includes:
A step of forming a second conductivity type well in a single crystal first conductivity type semiconductor substrate with a low impurity concentration, and a step of forming a buried channel type first conductivity type MIS semiconductor device in the second conductivity type well. In the first step, the second
Conductivity type impurities are added to the second layer by high energy ion implantation.
A second conductivity type well is formed by introducing the low impurity concentration single crystal of the first conductivity type semiconductor substrate deep into the first conductivity type semiconductor substrate so as to remain on the conductivity type well.

0010

[Operation] In this invention, since a part of the single-crystal first conductivity type semiconductor substrate with a low impurity concentration is used as the surface of the channel region in contact with the gate insulating film, the frequency of impurity scattering of conduction carriers in the channel region is small, and the conduction Decrease in mobility due to impurity scattering of carriers can be suppressed, and a high-performance semiconductor device can be obtained.

Further, in the present invention, in the step of forming a second conductivity type well in a single crystal first conductivity type semiconductor substrate with a low impurity concentration, impurities of the second conductivity type are implanted into the second conductivity type by high energy ion implantation. Since the single crystal first conductivity type semiconductor substrate with low impurity concentration remains on the type well, the second conductivity type well is formed by introducing the semiconductor substrate deeply into the first conductivity type semiconductor substrate, so that the impurity concentration in the channel region is reduced. Therefore, the frequency of impurity scattering of conduction carriers in the channel region is low, it is possible to suppress a decrease in the mobility of conduction carriers due to impurity scattering, and a high-performance semiconductor device can be obtained.

0012

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention. In the figure, the same reference numerals as in FIG. 2 indicate the same parts, and the structure is such that a part of the semiconductor substrate 1 is used as the channel region 3 of the semiconductor device in FIG.

As described above, according to this embodiment, a buried channel type MOS semiconductor device is constructed as described above, and P
Since a part of the P type substrate 1 is used as the type channel region, the impurity distribution in the depth direction of the channel portion of this semiconductor device is as shown in FIG. That is, since the P-type substrate 1 has a low impurity concentration, the impurity concentration is also low in the P-type channel region using this substrate, and therefore the mobility of conduction carriers is reduced due to impurity scattering, and the performance of the device itself is accordingly degraded. There isn't.

Next, a method for manufacturing this semiconductor device will be explained. An N-type well 2 is formed by implanting N-type impurities deep into the P-type semiconductor substrate 1 using a high-energy ion implantation method. At this time, a portion of the P-type semiconductor substrate 1 is left on the formed N-type well 2. A part of the P-type semiconductor substrate 1 left on the N-type well 2 is used as a P-type channel region, a gate insulating film 4 and a gate electrode 5 are formed on this surface, and impurities are implanted using the gate electrode 5 as a mask. Then, source/drain regions are formed.

As described above, according to this embodiment, the P-type substrate 1
In the step of forming an N-type well by implanting N-type impurities, the impurity was implanted so that a part of the P-type substrate 1 remained on the surface of the formed N-type well 2. By using a part of the P-type substrate 1 as a channel region, the total impurity concentration in the P-type channel region does not become high as in the conventional case, and it is possible to suppress a decrease in the mobility of conductive carriers due to impurity scattering. It is possible to obtain a semiconductor device with high performance.

[0016]

As described above, according to the semiconductor device of the present invention, since a part of the single crystal first conductivity type semiconductor substrate with a low impurity concentration is used as the channel region surface in contact with the gate insulating film, the channel region In this method, the frequency of impurity scattering of conduction carriers is low, and a decrease in mobility of conduction carriers due to impurity scattering can be suppressed, and a high-performance semiconductor device can be obtained.

Further, according to the method for manufacturing a semiconductor device according to the present invention, in the step of forming a second conductivity type well in a single crystal first conductivity type semiconductor substrate with a low impurity concentration, a second conductivity type well is formed.
Conductivity type impurities are added to the second layer by high energy ion implantation.
Since the single-crystal first conductivity type semiconductor substrate with low impurity concentration remains on the conductivity type well, the impurity concentration in the channel region is reduced by introducing the semiconductor substrate deeply into the first conductivity type semiconductor substrate to form the second conductivity type well. is low, the frequency of impurity scattering of conduction carriers in the channel region is low, it is possible to suppress a decrease in the mobility of conduction carriers due to impurity scattering, and a high-performance semiconductor device can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is an impurity distribution diagram of a channel portion of a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a conventional semiconductor device.

FIG. 4 is an impurity distribution diagram of a channel portion of a conventional semiconductor device.

[Explanation of symbols]

1 P-type semiconductor substrate 2 N type well 3 P-type channel region 4 Gate insulating film 5 Gate electrode 6 P-type source/drain diffusion region

Claims (2)

[Claims] 1. A buried channel region formed in a second conductivity type well region in a single crystal first conductivity type semiconductor substrate with a low impurity concentration, the surface region of which is of the first conductivity type, and a gate insulating layer on the channel region. In a semiconductor device including a gate electrode formed through a film, a part of the single crystal first conductivity type semiconductor substrate with a low impurity concentration is used as a surface region of a channel region in contact with the gate insulating film. Characteristic semiconductor devices. 2. A step of forming a second conductivity type well in a single crystal first conductivity type semiconductor substrate with a low impurity concentration;
A buried channel type first conductivity type MI in a conductivity type well.
In the method for manufacturing a semiconductor device, the first step includes forming a second conductivity type impurity into the second conductivity type well by a high energy ion implantation method. 1. A method for manufacturing a semiconductor device, comprising a step of forming a second conductivity type well by introducing the crystalline semiconductor substrate deeply into the first conductivity type semiconductor substrate such that the first conductivity type semiconductor substrate remains.