JPH04348034A - Wiring pattern forming method - Google Patents

Abstract

PURPOSE:To form a wiring pattern to a required pattern width by forming a resist pattern considering a difference in dimensional conversion for every region where each pattern with different pattern density is formed and by giving an etching treatment of a conductive film using the resist pattern as a masking material. CONSTITUTION:An element isolation film 2 is first formed on a semiconductor substrate 1 and a polysilicon film 3 is formed. Then, the first resist 4 is applied to the polysilicon film 3, and a resist pattern is formed controlled to the desired resist width and pattern density on the left side of the element isolation film 2. Then, dry etching is performed by using the resist pattern as a masking material, the first resist 4 is removed, the first resist remaining at the right side of the element isolation film 2 removed, and the first gate electrode is formed. Then, the second resist 5 is applied to the whole surface on the semiconductor substrate 1 thereby forming a different resist pattern and then dry etching is performed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming wiring patterns in semiconductor devices, and more particularly to a method for forming wiring patterns having patterns with different pattern densities.

0002

2 is a cross-sectional view showing the process of forming a gate electrode (wiring pattern) of a conventional MOS transistor. FIG. 2(a) shows a state in the middle of formation, and FIG.
indicates the completed state. In the figure, 1 is a semiconductor substrate, 2 is an element isolation film, 3 is a polysilicon film, and 6 is a patterned resist.

Next, the process of forming the gate electrode will be explained. First, an element isolation film 2 is formed on a semiconductor substrate 1, and then a polysilicon film 3 of about 4000 angstroms is formed over the entire surface of the substrate 1 as a conductive film. Next, a resist 6 is coated on the polysilicon film 3, exposed through a photomask with a desired pattern, and developed, so that the pattern spacing is, for example, 2 μm or less as shown in FIG. 2(a). A resist pattern 6 is formed, which includes a pattern region having a pattern and a pattern region having a pattern density with an interval of, for example, 2 μm or more. next,
Using the resist pattern 6 as a mask material, an etching process such as dry etching is performed to form a gate electrode consisting of a pattern of the polysilicon film 3 as shown in FIG. 2(b).

0004

[Problems to be Solved by the Invention] In the conventional process of forming gate electrodes of MOS transistors, gate electrodes 3 formed of patterns with different pattern densities are formed on the same substrate 1.
To form a resist pattern, a single resist pattern formation step,
One etching process is performed using the resist pattern as a mask material, and the dimensional difference (hereinafter simply referred to as dimensional conversion difference) that occurs between the width of the gate electrode 3 to be formed and the resist width of the resist pattern is performed. ) is different in each pattern region having a different pattern density, making it difficult to form the gate electrode 3 to a desired electrode width.

The present invention has been made to solve the above-mentioned problems, and when forming a wiring pattern consisting of patterns with different pattern densities, such as the gate electrode of the above-mentioned MOS transistor, it is possible to An object of the present invention is to obtain a method for forming a wiring pattern that can be formed to a pattern width.

[0006]

[Means for Solving the Problems] A method for forming a wiring pattern according to the present invention includes forming a resist pattern in consideration of dimensional conversion differences for each region where patterns with different pattern densities are formed, and masking the resist pattern. The conductive film used as the material is etched.

Furthermore, in the method for forming a wiring pattern according to the present invention, a resist pattern is formed in consideration of dimensional conversion differences for each region where patterns with different pattern densities are formed, and a conductive film is formed using the resist pattern as a mask material. The etching process is performed for each resist pattern.

[0008]

[Operation] In this invention, a resist pattern can be designed taking into account the dimensional difference (dimensional conversion difference) between the pattern width of the resist pattern and the pattern width of the wiring pattern to be formed for each wiring pattern with different pattern density. It is possible to form a resist pattern with high dimensional accuracy in consideration of dimensional conversion differences for each pattern of each pattern density, and the conductive film pattern obtained by etching using the resist pattern as a mask has the desired pattern width and pattern density. It is equipped with a plurality of patterns formed in.

Furthermore, in the present invention, a resist pattern is designed in consideration of the dimensional difference (dimensional conversion difference) between the pattern width of the resist pattern and the pattern width of the wiring pattern to be formed, for each wiring pattern having a different pattern density. Etching conditions can be controlled during etching process.
A resist pattern with high dimensional accuracy can be formed by taking into account dimensional conversion differences for each pattern of each pattern density.Furthermore, the optimum etching conditions can be selected for the resist pattern, so wiring patterns can be formed with the desired pattern width and pattern density. It can be formed to have a plurality of patterns formed on it.

0010

Embodiment FIG. 1 is a cross-sectional view showing the process of forming a gate electrode (wiring pattern) of a MOS transistor according to an embodiment of the present invention, in which 1 is a semiconductor substrate, 2 is an element isolation film,
3 is a polysilicon film, 4 is a first resist, and 5 is a second resist.

The process of forming the gate electrode will be explained below. First, an element isolation film 2 is formed on a semiconductor substrate 1, and then a polysilicon film 3 having a thickness of about 4000 angstroms is formed over the entire surface of the semiconductor substrate 1 so as to cover the element isolation film 2. Next, a first resist 4 is coated on the polysilicon film 3, and a desired area as shown in FIG. A resist pattern is formed with a controlled resist width and pattern density.

Next, using the resist pattern as a mask material, dry etching is performed to remove the first resist 4 and further remove the first resist 4 remaining on the semiconductor substrate 1 on the right side of the upper part of the element isolation film 2. After removing the resist 4, as shown in FIG. 1(b)
A first gate electrode as shown in FIG.

Next, after applying the second resist 5 to the entire surface of the semiconductor substrate 1, as shown in FIG. Also, a resist pattern having a sparse pattern density is formed.

Next, using the resist pattern as a mask material, dry etching is performed to remove the second resist 5. Furthermore, the second resist 5 covering the first gate electrode is removed, and the second resist 5 is removed. A second gate electrode having a pattern density lower than that of the first gate electrode and having a desired electrode width is formed, and a gate with patterns having different pattern densities is formed on the semiconductor substrate 1 as shown in FIG. 1(d). The electrode is completed.

[0015] Note that the first resist and the second resist in the above step
The pattern density and resist width of each resist pattern of the resist are controlled by taking into account the dimensional conversion difference determined by, for example, the material of the resist, the thickness of the resist, the thickness of the electrode (wiring) to be formed, the etching conditions, etc. However, this can be done by computer processing the pattern density and pattern width of the reticle when making a photomask.

In the process of forming the gate electrode of the MOS transistor of this embodiment, the first
The formation of a resist pattern using the resist 4 and the formation of a resist pattern using the second resist 5 with a sparse pattern density are performed in separate processes, and each resist pattern is constrained by the dimensional conversion difference of the other resist pattern with a different pattern density. Because the dimensions are precisely designed by considering only the dimensional conversion difference for each pattern, the electrodes obtained by etching using these resist patterns as a mask can have the desired electrode width and pattern density. A gate electrode is formed on the gate electrode.

Furthermore, in this embodiment, an etching process using the first resist pattern as a mask and an etching process using the second resist pattern as a mask are performed after the formation of the first resist pattern and after the formation of the second resist pattern, respectively. Since the etching is performed separately later, it is possible to control each etching condition so that the gate electrode formed has the desired pattern width and pattern density, and the gate electrode formed has higher dimensional accuracy. becomes.

In this example, the first resist pattern with a dense pattern density was formed first, and then the second resist pattern with a sparse pattern density was formed, but the order may be reversed. In either case, electrodes (wirings) can be formed with a desired pattern width and pattern density.

Furthermore, although the wiring pattern in the above embodiment is the gate electrode of a MOS transistor, the present invention
This is useful when forming densely patterned gate electrodes such as memory cells in AM and basic cells in gate arrays, and sparsely patterned gate electrodes in their peripheral circuits to desired electrode widths.

Furthermore, although the wiring pattern in the above embodiment is a gate electrode of a MOS transistor, it goes without saying that the present invention is applicable not only to the formation of gate electrodes of transistors but also to the formation of wiring patterns using various conductive films.

[0021]

As described above, according to the present invention, a resist pattern is formed taking into account the difference in dimension conversion for each pattern having a different pattern density, and an etching process is performed using the resist pattern as a mask material. Since wiring patterns having different pattern densities are formed for each pattern density, a wiring pattern having a plurality of patterns having a desired wiring width and different pattern densities can be formed on the same semiconductor substrate. This has the effect of improving the precision and reliability of semiconductor devices.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a process of forming a gate electrode of a MOS transistor according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a process of forming a gate electrode of a conventional MOS transistor.

[Explanation of symbols]

1 Semiconductor substrate 2 Element isolation film 3 Polysilicon 4 First resist 5 Second resist 6 Resist

Claims (2)

[Claims] 1. A step of forming a conductive film on a semiconductor substrate, a step of forming a first resist pattern on the conductive film, and a step of forming a second resist pattern with a pattern density different from that of the first resist pattern. the step of forming the first
, an etching process step of etching the conductive film using a second resist pattern as a mask. 2. The method for forming a wiring pattern according to claim 1, wherein the etching process using the first resist pattern as a mask and the etching process using the second resist pattern as a mask are performed separately. A method for forming a wiring pattern characterized in that it is performed in a process.