JP3526981B2 - Wiring structure of semiconductor integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure in a memory device or the like of a semiconductor integrated circuit device. FIG. 8 shows an example of a plan block diagram of a general memory device. In the figure, 50 is a row decoder, 51 is a column decoder, 52 is a sense refresh amplifier, 54 is a memory cell block,
57 is a wiring array portion in a region sandwiched by the memory cells 54, 58
Is a terminal portion of the wiring array, and 59 is a wiring array portion in a region between the memory cell block 54 and the sense refresh amplifier 52. FIG. 9 is a layout plan view of a word line in which a wiring array portion 57 in an area sandwiched by memory cells 54 in FIG. 8 is enlarged. In the figure, 13 is a word line, 30 is the remaining dimension width a in the minimum design rule of the word line, 31
Is a blank width b in the minimum design rule of the word line, 40 is a cover portion for performing interlayer connection, 14 is an interlayer connection portion, 15 is a bit line, and 22 is an active region of a memory cell. FIG. 10 is an enlarged plan view of the word line layout of the wiring array section 58 in FIG. In the figure, reference numeral 43 denotes a pattern portion having a remaining dimension width a (30) in the minimum design rule of a word line at a word line termination portion. Other reference numerals are the same as those in FIG. FIG. 11 is an enlarged plan view of a wiring array 59 in a boundary region between the memory cell block 54 and the sense amplifier 52 in FIG. 8, and is a layout plan view of bit lines. In the drawing, 15 is a bit line, 22 is an active region of a memory cell, 35 is a remaining dimension width c in the minimum design rule of the bit line, 36 is a punched dimension width d in the minimum design rule of the bit line, and 37 is a wiring of the terminal portion. The spaces e and 41 are cover portions for performing interlayer connection, 85 is a bit line terminal portion and a pattern portion having a remaining dimension width of 36 in the minimum design rule of the bit line, and 110 is an interlayer connection portion between the substrate and the bit line. . Such a pattern layout (design) is usually designed in consideration of the degree of integration and structure of the device. Here, the design rule is a fixed rule of the pattern dimension in designing a certain pattern.
The minimum design rule is a set of values of the (remaining) dimension width (30 or 35) of the narrowest part of the pattern and the (extraction) dimension width (31 or 36) of the narrowest part of the pattern gap. Point. Usually, such a pattern is generally formed by a fine processing technique, that is, a photolithography technique and an etching technique. FIG. 12 shows a conceptual diagram of a process for forming a pattern. In the figure, 120 is a photomask, 125 is a photosensitive resin film (resist), 126 is reduced projection exposure, 127 is a resist pattern, 128 is plasma, 130
Is a wiring film (film to be etched), 135 is a wiring pattern, 14
0 indicates a substrate. An original plate of a pattern necessary for fine processing is called a photomask (reticle) 120, and at present, the above-described predetermined pattern is drawn by an electron beam (EB drawing). This mask master is usually subjected to reduced projection exposure 126 to form a resist pattern 127 having a predetermined pattern on the wafer. Then, a predetermined wiring pattern 135 is obtained by etching the underlying wiring film 130 using the resist pattern 127 as a mask. These steps are described in detail. The photoengraving step includes (1) a photosensitive resin film (resist) on a lower surface of a wafer.
(2) selectively expose the resist 125 by reducing projection exposure 126 with ultraviolet rays or the like using the photomask master 120 having a predetermined pattern, and (3) treating the exposed resist 125 with a developing solution. Selectively dissolving to obtain a predetermined resist pattern 127. Next, etching is usually performed by a dry etching method suitable for microfabrication, in which a reactive gas is converted into plasma 128, and physical and chemical reactions between reactive ions and radicals in the plasma and the base (film to be etched 130) are performed. The etching is performed by a reactive reaction to obtain a wiring pattern 135. FIG. 13 is a cross-sectional view conceptually showing a reduction in the contact area between the pattern and the base as the pattern becomes finer due to the higher integration of the semiconductor integrated circuit. In the figure, 32 is a contact portion between the pattern and the base, 12
7 indicates a photoresist pattern. In the semiconductor integrated circuit device having the conventional wiring layout as described above, in particular, the pattern portion 43 having the remaining dimension width a (30) in the minimum design rule of the word line at the word line end portion shown in FIGS. And the contact area 32 with the substrate of the pattern portion 59 having the remaining dimension width c (36) in the minimum design rule of the bit line at the terminal portion of the bit line is smaller than the other wiring portions, so that the adhesion to the base is low, Infiltration of the liquid into the interface between the resist and the base during the development process in the photoengraving process at the time of forming the resist pattern, or washing with water after the formation of the wiring pattern, or the surface of the liquid at the boundary area where the pattern is rough The pattern may fall down due to the tension difference,
There was a problem of peeling. As shown in FIG. 13, these pattern defects are becoming more and more prominent with the miniaturization of the pattern due to the high integration of the semiconductor integrated circuit device, that is, the reduction of the contact area 32 between the pattern and the substrate. SUMMARY OF THE INVENTION The present invention has been made to solve such a problem.
Alternatively, it is another object of the present invention to prevent the pattern from collapsing or peeling even in a process such as washing with water after forming the wiring pattern. [0015] A plurality of wirings having interlayer connection parts and arranged in parallel with each other, and a terminal part of the wirings
In so as not to cause white space between the cover portion and the terminal portion of the interlayer connection portion, continuous with the cover portion, and the wide while being integrally formed, than the dimensions leaving at the minimum design rule The wiring structure of the semiconductor integrated circuit formed as described above. Embodiment 1 of the Invention FIG. 1 is a plan view showing a layout of a word line terminating portion 60 according to the present invention, and corresponds to FIG. This is the part to do. In the figure, 13 is a word line, 30 is a remaining dimension a in the minimum design rule of the word line, 31 is a cutout dimension b in the minimum design rule of the word line, 40 is a cover portion for performing interlayer connection, and 14 is an interlayer connection portion. , 15 are bit lines, 22 is an active region of a memory cell, and 54 is a memory cell portion. As shown in the drawing, by forming a wiring structure in which the pattern end portion is formed by a cover portion 40 for performing interlayer connection, the cover portion is a portion for performing interlayer connection. The wiring is terminated with a pattern wider than the remaining dimension width a (31) in the minimum design rule of the wiring, and the wiring structure has a large contact area with the base at the end portion, and therefore has strong adhesion with the base. be able to. As described above in the conventional example, such a pattern can be formed in a semiconductor device by drawing the pattern of the present invention on a photomask master and performing photolithography and etching using the photomask. . Embodiment 2 of the Invention FIG. 2 shows a termination section 81 when the embodiment 1 of the invention is applied to a bit line.
11 is a plan layout diagram of FIG.
It is a part corresponding to. In the figure, 15 is a bit line, 22
Is the active region of the memory cell, 41 is a cover part for performing interlayer connection, 35 is the remaining dimension width c in the minimum design rule of the bit line, 36 is the punching dimension width d in the minimum design rule of the bit line, 110 is the bit line. Reference numeral 52 denotes a sense refresh amplifier. By adopting a wiring structure in which the terminal portion of the bit line is formed by the cover portion 41 for performing interlayer connection as in the first embodiment, the contact area with the base is large, and Can have a strong wiring structure. Further, a pattern can be formed by the same method as in the first embodiment. Embodiment 3 of the Invention FIG. 3 is a plan layout view of a word line terminating portion 70 showing a third embodiment of the present invention, and is a portion corresponding to FIG. 10 in the conventional example. . In the figure, reference numeral 45 denotes a pattern of a terminal portion of a plurality of wirings according to the present invention. Other reference numerals are the same as those described in the first embodiment. In the first embodiment, pattern collapse and peeling can be prevented. However, since a blank portion whose width is about three times as large as the pitch (a + b) of the word lines 13 as shown in FIG. When an interlayer insulating film or the like is formed after the formation, a step 16 as shown in FIG.
0 tends to occur, which makes it difficult to form a pattern such as a photolithography process or etching. Therefore, as shown in FIG. 2, in order to prevent the blank portion of the wiring terminal portion of the first embodiment from being generated, a plurality of wiring terminal portions are formed between the cover portion and the terminal portion of the interlayer connection portion. Is the remaining dimension width a in the minimum design rule
(30) The wiring structure 45 has a wider width. Note that the termination pattern 45 is a pattern that is continuous with each of the wirings, and does not necessarily have a boundary between the wirings as shown in the figure. FIG. 6 shows FIG. 3 after the interlayer insulating film 150 is formed.
Is a cross-section of the C-C 'portion of FIG. 1, but since the pattern is dense, steps are hardly generated and the flatness is improved. Will be very easy. In addition, since the terminal portion is terminated with a pattern wider than the cover portion for performing interlayer connection, the contact area with the base is further increased, and the adhesion is improved. Such pattern formation can be achieved by the same method as described in the first embodiment. Embodiment 4 of the Invention FIG. 4 is a plan layout diagram of a word line terminating portion 75 showing a fourth embodiment of the present invention, and corresponds to FIG. 10 in the conventional example. . In the figure, reference numeral 46 denotes a dummy pattern according to the present invention. Other reference numerals are the same as those described in the second embodiment. As another method for compensating for the blank portion in the third embodiment, a dummy pattern 46 that is independent of each wiring and wider than the remaining dimension in the minimum design rule is arranged in the blank portion. By doing so, a large blank portion is filled, so that the problem of the step as shown in FIG. 5 is solved. Further, by arranging such a dummy pattern, a difference in surface tension in a boundary area where patterns are coarse and dense during liquid processing such as development can be reduced, so that the wiring structure described in the first embodiment can be reduced. Further, the adhesion to the base can be enhanced. Such pattern formation can be achieved by the same method as described in the first embodiment. Embodiment 5 of the Invention FIG. 7 is a plan layout diagram of a terminal 80 of a bit line according to a fifth embodiment of the present invention, which corresponds to FIG. 11 in the conventional example. . In the drawing, reference numeral 90 denotes a pattern of a bit line termination portion in the present invention, 15 denotes a bit line, 22 denotes an active region of a memory cell, 35 denotes a remaining dimension width c in the minimum design rule of the bit line, and 36 denotes a minimum design rule of the bit line. The width d, 37 of the extraction dimension in the above is the distance e, 41 between the end wirings.
Is a cover portion of an interlayer connection portion, 52 is a sense refresh amplifier, and 110 is an interlayer connection portion between a substrate and a bit line. In the case of a wiring such as the bit line 15 in which the interval e (37) between the terminations is larger than the remaining dimension c (35) of the minimum design rule of the wiring, the termination is the minimum design of the wiring. It is formed by a rectangular pattern having sides wider than the remaining dimension width c (37) in the rule. As described in the third embodiment, this rectangular pattern is continuous with each wiring, and does not have a boundary between the wirings as shown in the figure. By doing so, the contact area between the pattern and the base at the terminal end can be increased, so that the adhesion is enhanced. Further, since the space near the rectangular pattern is reduced, the step as described in the second embodiment can be reduced. Such pattern formation can be achieved by the same method as described in the first embodiment. [0031] [0032] [0033] [0034] [Effect of the Invention] According to the first invention, the wiring Rejisutopa
Turn and pattern from the end of pattern after etching
Device fall and pattern peeling can be prevented, and the device yield,
Since the reliability can be improved and the step on the device surface after the wiring is formed can be reduced and flattened, the pattern formation after the wiring is formed becomes easy and the number of steps can be reduced. [0035]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view of a wiring termination layout of an embodiment of a semiconductor integrated circuit device according to the present invention. FIG. 2 is a layout plan view of a terminal portion of a wiring in another embodiment of the semiconductor integrated circuit device according to the present invention. FIG. 3 is a layout plan view of a terminal portion of a wiring in another embodiment of the semiconductor integrated circuit device according to the present invention. FIG. 4 is a layout plan view of a terminal portion of a wiring in another embodiment of the semiconductor integrated circuit device according to the present invention. FIG. 5 is a cross-sectional view of the pattern after the BB ′ portion in FIG. 1 is etched. FIG. 6 is a cross-sectional view of a pattern after the CC ′ portion in FIG. 3 is etched. FIG. 7 is a layout plan view of a terminal portion of a wiring in another embodiment of the semiconductor integrated circuit device according to the present invention. FIG. 8 is a block diagram showing a memory cell and an array of a semiconductor integrated circuit device in a conventional example. FIG. 9 is a layout plan view of word lines in a memory cell block gap of a semiconductor integrated circuit device in a conventional example. FIG. 10 is a layout plan view of a terminal portion of a word line in an outermost memory cell block of a semiconductor integrated circuit device in a conventional example. FIG. 11 is a layout plan view of a bit line in a gap between a memory cell block and a sense refresh amplifier in a semiconductor integrated circuit device in a conventional example. FIG. 12 is a sectional view showing a process flow of pattern formation. FIG. 13 is a sectional view of a resist pattern taken along the line AA ′ in FIG. 9; [Description of Reference Numerals] 13 Word line 14 Interlayer connection hole portion 15 Bit line 22 Memory cell active region 30 Remaining dimension 31 in minimum design rule of word line Extraction dimension 32 in minimum design rule of word line Contact portion 35 between pattern and base 35 Remaining dimension 36 in the minimum design rule of the bit line 36 Drilling dimension 37 in the minimum design rule of the bit line Wiring interval 40 at the end of the bit line Cover part 41 for performing interlayer connection of word lines 41 for performing interlayer connection of bit lines Cover part 45 Word line end part pattern 46 of the present invention Dummy line end part dummy pattern 50 Row decoder 51 Column decoder 52 Sense refresh amplifier 54 Memory cell block 57 Memory cell block gap wiring array part 5 in the present invention Word line end portion layout 60 in outermost memory cell block in word line scanning direction Layout of word line end portion 70 in the present invention Layout of word line end portion 75 in the present invention Layout 80 of word line end portion 80 in the present invention Layout 90 of the end part of bit line in the present invention 90 Rectangular pattern 110 of the end part of bit line in the present invention 110 Interlayer connection part 120 between bit line and substrate Photomask (reticle) 125 Photosensitive resin film (resist) 126 Reduction projection exposure 127 Resist pattern 128 plasma 130 wiring film (film to be etched) 135 wiring pattern 140 substrate 150 interlayer insulating film 160 step

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Claims (1)

(57) [Claim 1] A plurality of wirings having interlayer connection portions and arranged in parallel with each other, and a blank portion is formed at the end of the wirings.
Flip As no between the cover portion of the interlayer connection portion the terminal portion, continuous with the cover portion, and, while being integrally formed, and is formed wider than the remaining size at the minimum design rule semiconductor The wiring structure of an integrated circuit.