JP2008047904A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for forming a pattern that can solve problems of short-circuit or breaking of word lines and data line ends caused by interference of diffracted light produced at a pattern end on a boundary part between a memory array and a sub-word driver or sense amplifier when fine word lines and data lines having linewidth smaller than a wavelength are patterned on a memory. <P>SOLUTION: In a mask pattern (a) for patterning word lines and data lines, lengths of word lines WL1, WL2, WL5 and WL6 having end parts neighboring each other are varied to shift their ends from each other, and further the ends of word lines WL1, WL2, WL5 and WL6 are slanted. Separation within a resist pattern and contact of patterns with each other can be thereby prevented, and also breakage of wires to be patterned and short-circuiting between wires can be prevented. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to photolithography for forming a fine pattern, and more particularly, to an exposure method for manufacturing a semiconductor device.

  In order to increase the integration and speed of semiconductor memories and microprocessors, it is essential to make ULSI finer. The most important problem for this is miniaturization of photolithography. Currently, in photolithography, a pattern having a wavelength shorter than the light wavelength of the exposure apparatus is formed. As an example, in a 1 Gb DRAM, it is necessary to form a word line and a data line with a width of 0.16 μm by an exposure apparatus using a KrF excimer laser with a wavelength of 0.248 μm as a light source.

  In order to form a pattern having a size smaller than the wavelength as described above, a super-resolution technique such as a phase shift method or modified illumination is used. The super-resolution technique is effective in a line & space (L & S) pattern in which simple straight lines such as memory word lines and data lines are repeated. This is because, by shifting the phase of light passing through adjacent line patterns by 180 degrees, the light cancels each other at the boundary between the line patterns, and a space pattern is formed. In the super-resolution technique, the coherent coefficient is about 0.3, which is smaller than that of normal exposure, and the light coherence is enhanced.

  In the L & S pattern, it is possible to pattern the size below the wavelength by the method as described above. However, it has been found that there is a problem with patterns that deviate from the L & S, such as the connection between the memory array and the peripheral circuit of the memory. This is because light diffraction or interference occurs at the end of the wiring or at the bent portion, so that the resist pattern may be narrower than the mask pattern or may be severed if severe. The following are newly clarified by the present inventors through examination.

  This is schematically shown in FIG. FIG. 14A shows a conventional mask pattern of a word line (WL) at the boundary between a DRAM memory array and a sub word driver (SWD) or a word shunt region (Shunt). In the SWD portion, the WL is widened to form a dogbone pattern in order to allow room for placing contacts. In this example, SWDs are alternately arranged with respect to the memory array as will be described later, WL0, 3, 4, and 7 are connected to the SWD on the left side of the array, and WL1, 2, 5, 5, and 6 are on the right side of the SWD. It is connected to the.

  The pattern (a) is lithography using an exposure apparatus whose light source is a KrF excimer laser with a wavelength λ = 0.248 μm, a numerical aperture NA = 0.6 of a lens, a coherent coefficient σ = 0.3, and a reduction ratio K = 1/5. The conceptual diagram of the resist pattern obtained when performing is shown in FIG. The ends of adjacent WLs are short-circuited with each other, and the wiring is disconnected near the dogbone. This is because light interference has an adverse effect.

  This phenomenon is shown by optical simulation. In this simulation, the contour lines of the light intensity obtained on the resist are calculated based on the mask pattern and the optical constants of the exposure apparatus. FIG. 15A shows a conventional mask pattern at the end of a word line. The word line width and space were both 0.16 um. As optical constants, λ = 0.248 μm, NA = 0.6, σ = 0.3, defocus = −0.5 μm, and spherical aberration are assumed. In this simulation, phase shift lithography is used, and a phase of 0 degrees is assigned to the pattern with the upward slanting line in (a), and a phase of 180 degrees is assigned to the pattern with the slanting line of the lower right. In principle, similar results can be obtained with modified illumination lithography. All subsequent simulations assume similar optical conditions. In optical lithography, reduced projection exposure is used, and in exposure with a reduction ratio K (K <1), the actual circuit pattern and resist pattern are K times larger than the mask pattern. For example, if K = 1/5, the line width of the mask for obtaining the wiring width of 0.16 μm is 0.8 μm. However, for the sake of simplification, the mask pattern is reduced to the same size as the circuit pattern and the resist pattern. Show. The light intensity distribution, which is an optical image obtained by calculation for this pattern, is shown in FIG. Contour lines with relative light intensities of 0.18, 0.32, and 0.53 are shown. For light intensity, the light transmittance in a sufficiently large pattern is defined as 1. The same three contour lines are shown in all subsequent optical simulation results.

  FIG. 15B shows a resist pattern in which contour lines with a light intensity of 0.32 are actually obtained, and word lines are formed at equal intervals at positions sufficiently away from the ends. However, the contour line having the light intensity of 0.18 (the contour line on the outermost side of the pattern) is not separated between adjacent word lines at the tip portion. This indicates that the light intensity in this portion is not sufficiently lowered due to the interference effect of light. Therefore, there is a high possibility that the resist remains during development and the word line is short-circuited.

  In addition, when looking at the dog bone portion, the contour line having a light intensity of 0.53 is broken, indicating that the light intensity is weak at this portion. Therefore, there is a high possibility that the resist film is reduced during development and the wiring is disconnected.

  FIG. 16A shows a conventional second word line end mask pattern. In this example, the SWD or shunt region is arranged on the left side of the memory array, and all word lines are connected to the left SWD. Even in this case, the contour line having the light intensity of 0.18 (the contour line on the outermost side of the pattern) is not separated between the adjacent word lines at the tip portion, so that there is a high possibility that the word line is short-circuited.

  It is an object of the present invention to prevent a short circuit or disconnection that occurs at the end of an L & S pattern or the like.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  The object is to provide a semiconductor device in which the positions of the ends of adjacent wirings are shifted in the length direction when a large number of wirings are arranged at regular intervals, such as memory word lines and data lines. Achieved. In this way, when patterning the wiring, the interference effect of the diffracted light generated at the end of the wiring can be weakened, and a short circuit or disconnection can be prevented.

  This wiring can be obtained by exposing using the mask which shifted the position of the edge part of an adjacent pattern to the length direction. For example, the mask pattern shown in FIG. 11A has a configuration in which the positions of the ends of both adjacent patterns are shifted from each other in the length direction. When exposure is performed using this mask, a light intensity distribution as shown in FIG. From FIG. 11B, it can be seen that the pattern is less likely to be disconnected, and is less likely to be separated and short-circuited.

  Further, the difference in length between the end positions of adjacent wirings is set to be more than half of the wiring pitch. If it is more than half of the wiring pitch, the effect of preventing a short circuit or disconnection is increased. Further, the difference in the length of the end position is set to be equal to or less than the wiring pitch. By doing so, the wasted area can be minimized.

  Further, when the present invention is applied to word lines and data lines of memories such as DRAM, SRAM, FLASH, and mask ROM, short circuit and disconnection are less likely to occur in the manufacturing process.

  Further, exposure is performed using a mask having a side that is not parallel to the short side and the long side of the pattern so that the corner of the pattern is dropped and the pattern width becomes smaller as the end is approached. Thereby, the interference effect of diffracted light can be further reduced. For example, the mask pattern shown in FIG. 10A has a configuration in which the pattern edge portions on both sides are shifted from each other in the length direction and the corners of the pattern edge portions are dropped. When exposure is performed using this mask, as shown in FIG. 10B, a light intensity distribution is obtained in which no disconnection or short circuit occurs. In this way, the possibility of disconnection or short-circuiting can be reduced by using a mask in which the corners of the pattern are dropped. Although FIG. 10 shows the mask pattern shifted in the length direction, the interference effect of the diffracted light can be obtained even if the pattern length is equal and the pattern corners are dropped without shifting in the length direction. It can be weakened to some extent and shorts and disconnections can be reduced.

  Further, when the exposure wavelength of the exposure apparatus is λ and the numerical aperture is NA, a short circuit or disconnection at the end of the wiring becomes a problem particularly when the pitch of the wiring is λ / (NA) or less. It is effective to perform exposure using a mask such as

  The present invention relates to a memory such as a DRAM, SRAM, FLASH, and mask ROM. (1) A word line pattern at a boundary area between a memory array and a word line driver; (2) A boundary area between a memory array and a shunt area of a word line (3) a data line pattern in the boundary area between the memory array and the sense amplifier, short-circuiting and disconnection are less likely to occur. Also, the same effect can be obtained when the gate array is applied to the tip of the gate of the MOS transistor.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  By using the asymmetric word line end of the present invention, when forming a fine word line having a width less than the exposure wavelength by photolithography, the boundary between the SWD and the memory array or the boundary between the word line shunt region and the memory array. This can reduce the possibility that the end of the word line is short-circuited. Further, it is possible to reduce the possibility of disconnection of the dogbone pattern that contacts the word line.

  Similarly, by using the asymmetric data line end of the present invention, when forming a fine data line having a width less than the exposure wavelength by photolithography, the data line end may be short-circuited at the boundary between the SA and the memory array. Can be reduced. Further, it is possible to reduce the possibility that the dog bone pattern that contacts the data line is disconnected.

(Example 1)
FIG. 1 shows a first asymmetric word line end of the present invention. At the boundary between the SWD and the memory array, the lengths of adjacent word lines (WL1 and WL2, WL5 and WL6) are changed, and the word line ends are shifted in the horizontal direction. Also, the corners of the word line ends are dropped smoothly. A conceptual diagram of a resist pattern when this pattern is exposed is shown in FIG. Diffracted light is generated at the corners at the end of the word line, and this light interferes with the conventional pattern, causing a short circuit or disconnection. On the other hand, when the mask pattern of the present invention is used, the positions of the corners are shifted laterally from each other, and the interference of diffracted light is weakened. The effect which prevents is obtained. Note that when the wavelength of the exposure apparatus is λ and the numerical aperture is NA, the above effect is great when the difference in length between WL1 and WL2 or WL5 and WL6 is λ / (2NA) or more. This is because the range affected by the diffracted light generated at the corner is about λ / (2NA). If attention is paid only to the pattern, assuming that the repetition pitch of the word lines is P, the above-described effect is great if the leading end of WL is shifted by P / 2 or more between WL1 and WL2 or WL5 and WL6. This is because λ and NA are determined so that P / 2 and λ / (2NA) are approximately equal during lithography. However, unnecessarily increasing the amount by which the tip is displaced leads to an increase in the chip area, so it is desirable to set it to λ / NA or less or P or less.

  Further, when the WL tip is slanted, pattern processing at the time of mask data creation is facilitated by making a sharp angle by leaving a side perpendicular to WL slightly at the WL tip as shown in the figure. If the word line is shunted with a metal wiring without using the hierarchical word system, a similar pattern can be used at the boundary between the shunt region (Shunt) of the word line and the memory array.

  The effect of the pattern of the present invention is shown by optical simulation. FIG. 2A shows a mask pattern at the end of the first asymmetric word line of the present invention. The word line width and space were both 0.16 um. As optical constants, λ = 0.248 μm, NA = 0.6, σ = 0.3, defocus = −0.5 μm, and spherical aberration are assumed. In this simulation, phase shift lithography is used, and a phase of 0 degrees is assigned to the pattern with the upward slanting line in (a), and a phase of 180 degrees is assigned to the pattern with the slanting line of the lower right. In principle, similar results can be obtained with modified illumination lithography. All subsequent simulations assume similar optical conditions. Hereinafter, for simplification, the mask pattern is reduced to the same size as the circuit pattern and the resist pattern. An optical image obtained by calculation for this pattern is shown in FIG. Contour lines with relative light intensities of 0.18, 0.32, and 0.53 are shown. For light intensity, the light transmittance in a sufficiently large pattern is defined as 1. The same three contour lines are shown in all subsequent optical simulation results.

  By using this mask pattern, 0.18 contour lines (contour lines on the outermost pattern), which have been short-circuited, are separated between adjacent word lines. This indicates that the light interference effect is weakened by improving the pattern, and the possibility that the word line is short-circuited during development is reduced. In addition, contour lines having a light intensity of 0.53 at the dogbone portion that has been disconnected in the past are continuous, and a decrease in light intensity at this portion is suppressed. Therefore, the possibility of disconnection during development is reduced.

(Example 2)
In this embodiment, one of the cases where the present invention is applied to a DRAM is shown.

  In a DRAM, the pattern as shown in FIG. 1 occurs not only at the word line end but also at the data line end. FIG. 3 shows a configuration diagram of the DRAM chip. Bonding pads and indirect peripheral circuits are arranged in the center and long side direction of the chip. Here, an address and data input / output circuit, a power supply circuit, a refresh control circuit, a main amplifier, and the like are arranged. An array control circuit for controlling the SWD and the sense amplifier (SA) is arranged in the short side direction. The chip is roughly divided into four blocks by the above circuit, and each chip is surrounded by a row decoder that outputs a main word line (MWLB) and a column decoder that outputs a column selection line (YS). Each block is divided by the SA column in the row direction and the SWD column in the column direction, and a portion where the memory cells surrounded by the SA column and the SWD column are arranged in an array is called a memory array.

  FIG. 4 shows a configuration diagram of the SWD column, SA column, and memory array in the alternately arranged hierarchical word driver (WD) system. A memory cell (MC) is arranged at the intersection of the word line (WL) and the data line (DL). WL is driven by SWD. Two DLs are input to one SA and amplify the signal coming out of the MC. Both SWD and SA are arranged alternately with respect to the memory array. That is, every other WL is alternately connected to the left and right SWDs, and every other WL is alternately connected to the upper and lower SAs.

  FIG. 5 shows a circuit diagram of SWD, SA, and MC. The operation is as follows. During standby, all MWLBs are at Vpp (voltage higher than the high level VDL of the data line), FX is at Vss (ground potential), and SWD outputs Vss to WL. In MC, the selection transistor is turned OFF, and the voltage of VDL or Vss is written in the capacitor according to information. In SA, SHRU, SHRD are Vss, CSP, CSN are VBLR, BLEQ is Vcc (a voltage higher than VDL and lower than Vpp), YS is Vss, and DL is precharged to VBLR. Usually, VBLR = VDL / 2.

  When commands and addresses are input to the DRAM and the above memory array is selected, first, SHRD and BLEQ are dropped to Vss, then one MWLB becomes Vss and one FX becomes Vpp, SWD WL selected in is activated to Vpp. Then, the MC selection transistor connected to the activated WL is turned ON, and a signal is output to DL or DLB. Subsequently, CSP is dropped to VDL and CSN is dropped to Vss, and this signal is amplified by SA. In the case of reading, YS is raised to Vcc when the potential difference between the paired DLs is sufficiently opened, and data is read to SIO and SIOB. In the case of writing, data is written from SIO and SIOB.

  FIG. 6 shows the layout of word line ends and data line ends according to the present invention at the boundary between SWD, SA and memory array, including memory cells. M1 is the first metal wiring layer, ACT is the active region of the MOS transistor, CONT is the contact between M1 and WL or ACT, SNCT is the contact connecting the capacitor of the MC and the selection transistor, DLCT is the connection between the selection transistor of the MC and the DL It is a contact.

  (A) shows the boundary between the SWD and the memory array of the present invention. The SWDs are arranged alternately with respect to the memory array. Therefore, when looking at the boundary between the SWD and the memory array, there are WL that pass through the boundary and enter the SWD (WL0, 3, 4, 7) and those that end at the boundary (WL1, 2, 5, 6). It is repeated every second. Similarly to FIG. 1, the lengths of WL1 and WL2 and WL5 and WL6 are changed to shift the tip, and the WL tip is further inclined. By using such a mask pattern, there is an effect of preventing short-circuiting at the WL tip and disconnection at the boundary between WL0, 3, 4, and 7. In addition, if the difference in length between WL1 and WL2 or WL5 and WL6 is set to λ / (2NA) or more, the above effect is enhanced. If attention is paid only to the pattern, assuming that the repetition pitch of the word lines is P, the above-described effect is great if the leading end of WL is shifted by P / 2 or more between WL1 and WL2 or WL5 and WL6. However, unnecessarily increasing the amount by which the tip is displaced leads to an increase in the chip area, so it is desirable to set it to λ / NA or less or P or less.

  Further, when the WL tip is slanted, pattern processing at the time of mask data creation is facilitated by making a sharp angle by leaving a side perpendicular to WL slightly at the WL tip as shown in the figure. When the word line is shunted by metal wiring without using the hierarchical word system, the same pattern can be used at the boundary between the shunt region of the word line and the memory array.

  In this pattern, auxiliary patterns CP1-4 are added to the dogbone portions where the contacts WL0, 3, 4, and 7 are made. By adding such a pattern, the effect of preventing disconnection at the boundary between WL0, 3, 4, and 7 is further enhanced. The auxiliary pattern has a high effect of preventing disconnection when the size in the data line direction is λ / (10NA) or more and λ / (2NA) or less and the size in the word line direction is λ / (2NA) or more. If the size of the auxiliary pattern in the data line direction is excessively small, mask inspection becomes difficult, and if the size is larger than the resolution limit λ / (2NA), the auxiliary pattern itself is resolved. It is desirable to be. With respect to the word line direction, by making it larger than the resolution limit, the effect of the auxiliary pattern appears. When attention is paid only to the pattern, the auxiliary pattern is highly effective in preventing disconnection when the size in the data line direction is P / 10 or more and P / 2 or less and the size in the word line direction is P / 2 or more.

  (B) shows the boundary between the SA of the present invention and the memory array. SAs are interleaved with respect to the memory array. Therefore, looking at the boundary between the SA and the memory array, there are DLs that pass through the boundary and enter the SA (DL0B, DL2, DL2B, DL4), and those that end at the boundary (DL1, DL1B, DL3, DL3B). It is repeated every second.

This time, the lengths of DL1 and DL1B or DL3 and DL3B are changed to shift the tip, and the DL tip is further inclined. By using such a mask pattern, there is an effect of preventing a short circuit at the DL tip and disconnection at the boundary between DL0B, DL2, DL2B, and DL4. In addition, if the difference in length between DL1 and DL1B or DL3 and DL3B is set to λ / (2NA) or more, the above-described effect is increased. When attention is paid only to the pattern, assuming that the repetition pitch of the data lines is PD, the above effect is great if the leading end of DL is shifted by PD / 2 or more between DL1 and DL1B or DL3 and DL3B. However, unnecessarily increasing the amount by which the tip is displaced leads to an increase in the chip area, so it is desirable to set it to λ / NA or less or PD or less.
Further, when the DL tip is inclined, if a sharp angle is not made by leaving a side perpendicular to the DL at the DL tip as shown in the figure, pattern processing at the time of mask data creation is facilitated.

  Further, in this pattern, auxiliary patterns CP1-4 are added to the dogbone portions where the contacts DL0B, DL2, DL2B, and DL4 are made. By adding such a pattern, the effect of preventing disconnection at the boundary between DL0B, DL2, DL2B, and DL4 is further enhanced. The auxiliary pattern has a high effect of preventing disconnection when the size in the word line direction is λ / (10NA) or more and λ / (2NA) or less and the size in the data line direction is λ / (2NA) or more. When attention is paid only to the pattern, the auxiliary pattern has a high effect of preventing disconnection when the size in the word line direction is PD / 10 or more and PD / 2 or less and the size in the data line direction is PD / 2 or more.

  On the other hand, if the data line lengths of the data line pairs such as DL1 and DL1B are different, the data line capacity may be unbalanced and the sensitivity of SA may be reduced. However, since the difference in the data line length necessary in the present invention is very small with respect to the length of the data line itself, the imbalance can be almost ignored. As an example, when 512-bit memory cells are connected per SA with a data line pitch of 0.32 um, the data line length is 163.84 um. On the other hand, if the difference between the data line lengths required in the present invention is λ = 0.248 μm and NA = 0.6 μm, λ / (2NA) = 0.21 μm, so the unbalance is about 0.1%.

(Example 3)
FIG. 7A shows a second asymmetric word line end of the present invention.

  FIG. 7A shows a case where SWDs are alternately arranged with respect to the memory array, and every other WL is connected to the left and right SWDs. Therefore, looking at the boundary between the SWD and the memory array, WL passes through the boundary and enters the SWD (WL0, 2, 4, 6), and ends at the boundary (WL1, 3, 5, 7). Is repeated every other line. Even in such a pattern, when the lengths of the WLs are the same as in the prior art, short-circuiting of the WL tip and disconnection at the boundary part have become problems due to interference of diffracted light at the WL end.

  In the pattern of the present invention, every other WL ending at the boundary is changed in length and the tip is shifted, and the WL tip is inclined. By using such a mask pattern, there is an effect of preventing short-circuiting at the WL tip and disconnection at the boundary between WL0, 2, 4, and 6. If the difference in length between WL1 and WL3, or WL5 and WL7 is λ / (2NA) or more, the above effect is enhanced. When attention is paid only to the pattern, if the repetition pitch of the word lines is P, the above-described effect is great if the leading end of WL is shifted by P / 2 or more between WL1 and WL3 or WL5 and WL7. However, unnecessarily increasing the amount by which the tip is displaced leads to an increase in the chip area, so it is desirable to set it to λ / NA or less or P or less. Further, when the WL tip is slanted, pattern processing at the time of mask data creation is facilitated by making a sharp angle by leaving a side perpendicular to WL slightly at the WL tip as shown in the figure. When the word line is shunted by metal wiring without using the hierarchical word system, the same pattern can be used at the boundary between the shunt region of the word line and the memory array.

Example 4
FIG. 7B shows a third asymmetric word line end of the present invention. FIG. 7B shows a case where the SWD is arranged on one side with respect to the memory array and all WLs are connected to the left SWD. In this case, all WL ends on the right side of the memory array. As shown in FIG. 16 as the conventional second word tip, if the WL lengths are made equal, there is a problem that all the WL tips are short-circuited. In the pattern of the present invention, the length of the WL is changed every other line to shift the tip, and the WL tip is inclined. By using such a mask pattern, there is an effect of preventing a short circuit at the WL tip. If the difference in length between WL0 and WL1 and WL2 and WL3 is λ / (2NA) or more, the above effect is enhanced. When attention is paid only to the pattern, if the repetition pitch of the word lines is P, the above-described effect is great if the leading end of WL is shifted by P / 2 or more between WL0 and WL1 and WL2 and WL3. However, unnecessarily increasing the amount by which the tip is displaced leads to an increase in the chip area, so it is desirable to set it to λ / NA or less or P or less. Further, when the WL tip is slanted, pattern processing at the time of mask data creation is facilitated by making a sharp angle by leaving a side perpendicular to WL slightly at the WL tip as shown in the figure. When the word line is shunted by metal wiring without using the hierarchical word system, the same pattern can be used at the boundary between the shunt region of the word line and the memory array.

  The effect of this pattern is shown by optical simulation. FIG. 8A shows a mask pattern at the end of the third asymmetric word line of the present invention. The word line width and space were both 0.16 um. As shown in FIG. 8B, by using this mask pattern, the 0.18 contour lines (contour lines on the outermost pattern) that have been short-circuited in the past are considerably separated between adjacent word lines. Although there are some short-circuited portions, the possibility of short-circuiting is reduced compared to the conventional pattern of FIG.

(Example 5)
FIG. 9A shows the fourth asymmetrical word line end of the present invention. In the same manner as in FIG. 7B, the SWD is arranged on one side with respect to the memory array, and all WLs are connected to the left SWD. Show. In the pattern of the present invention, the length of WL is changed with a period of four, the length is increased in the order of WL0, 1, 2, and 3, and the tip of WL is further inclined. When such a mask pattern is used, an extra area is required when the length is changed every other line, but the effect of preventing short-circuiting at the WL tip is enhanced. If the difference in length between WL0 and WL1 and WL2 and WL3 is λ / (2NA) or more, the above effect is enhanced. When attention is paid only to the pattern, if the repetition pitch of the word lines is P, the above-described effect is great if the leading end of WL is shifted by P / 2 or more between WL0 and WL1 and WL2 and WL3. However, unnecessarily increasing the amount by which the tip is displaced leads to an increase in the chip area, so it is desirable to set it to λ / NA or less or P or less. Further, since it is essential that the lengths of the four WLs are different, a pattern in which any two of WL0-4 are replaced is also effective. Furthermore, the number of cycles becomes effective even if the value is other than 2 or 4.

  Further, when the WL tip is slanted, pattern processing at the time of mask data creation is facilitated by making a sharp angle by leaving a side perpendicular to WL slightly at the WL tip as shown in the figure. When the word line is shunted by metal wiring without using the hierarchical word system, the same pattern can be used at the boundary between the shunt region of the word line and the memory array.

  The effect of this pattern is shown by optical simulation. FIG. 10A shows a mask pattern at the end of the fourth asymmetric word line of the present invention. The word line width and space were both 0.16 um. (B) shows the light intensity distribution. By using this mask pattern, the 0.18 contour line (contour line on the outermost pattern), which has been short-circuited in the past, is completely separated between adjacent word lines. Compared with the conventional pattern of FIG. 16 and the pattern of FIG. 7B, the possibility of short-circuiting is further reduced.

(Example 6)
FIG. 9B shows a fifth asymmetric word line end of the present invention. At the boundary between the SWD and the memory array, the lengths of adjacent word lines (WL1 and WL2, WL5 and WL6) are changed, and the word line ends are shifted in the horizontal direction. In this pattern, the corner of the WL end is not dropped. FIG. 11 (a) shows the mask pattern of the present invention, and FIG. 11 (b) shows the result of the optical simulation. Compared with the case where the corner is dropped, the effect of suppressing the interference of diffracted light is small, so there is no short at the WL tip. However, the disconnection at Dogbone remains. However, this pattern is applicable as an example when the line is wider than the space and disconnection is not a problem, and an effect of preventing a short circuit can be obtained. Note that when the wavelength of the exposure apparatus is λ and the numerical aperture is NA, the above effect is great when the difference in length between WL1 and WL2 or WL5 and WL6 is λ / (2NA) or more. If attention is paid only to the pattern, assuming that the repetition pitch of the word lines is P, the above-described effect is great if the leading end of WL is shifted by P / 2 or more between WL1 and WL2 or WL5 and WL6. However, unnecessarily increasing the amount by which the tip is displaced leads to an increase in the chip area, so it is desirable to set it to λ / NA or less or P or less. In addition, since the front end of WL is not inclined and the number of vertices of graphic data is small, there is an effect that pattern processing at the time of creating mask data is facilitated. When the word line is shunted by metal wiring without using the hierarchical word system, the same pattern can be used at the boundary between the shunt region of the word line and the memory array.

(Example 7)
FIG. 12A shows the first asymmetric data line of the present invention. SAs are interleaved with respect to the memory array. Therefore, when looking at the boundary between the SA and the memory array, there are DL that pass through the boundary and enter the SA (DL0B, DL2, DL2B, DL4), and those that end at the boundary (DL1, DL1B, DL3, DL3B). It is repeated every second.

  In the present invention, the lengths of DL1 and DL1B or DL3 and DL3B are changed to shift the tip, and the DL tip is inclined. By using such a mask pattern, there is an effect of preventing a short circuit at the DL tip and disconnection at the boundary between DL0B, DL2, DL2B, and DL4. In addition, if the difference in length between DL1 and DL1B or DL3 and DL3B is set to λ / (2NA) or more, the above-described effect is increased. When attention is paid only to the pattern, assuming that the repetition pitch of the data lines is PD, the above effect is great if the leading end of DL is shifted by PD / 2 or more between DL1 and DL1B or DL3 and DL3B. However, unnecessarily increasing the amount by which the tip is displaced leads to an increase in the chip area, so it is desirable to set it to λ / NA or less or PD or less. Further, when the DL tip is inclined, if a sharp angle is not made by leaving a side perpendicular to the DL at the DL tip as shown in the figure, pattern processing at the time of mask data creation is facilitated.

  In the present invention, every two data lines, the lengths of DL1 and DL1B or DL3 and DL3B are changed to shift the tips, and the DL tips are inclined. By using such a mask pattern, there is an effect of preventing a short circuit at the DL tip and disconnection at the boundary between DL0B, DL2, DL2B, and DL4. In addition, if the difference in length between DL1 and DL1B or DL3 and DL3B is set to λ / (2NA) or more, the above-described effect is increased. When attention is paid only to the pattern, assuming that the repetition pitch of the data lines is PD, the above effect is great if the leading end of DL is shifted by PD / 2 or more between DL1 and DL1B or DL3 and DL3B. However, unnecessarily increasing the amount by which the tip is displaced leads to an increase in the chip area, so it is desirable to set it to λ / NA or less or PD or less. Further, when the DL tip is inclined, if a sharp angle is not made by leaving a side perpendicular to the DL at the DL tip as shown in the figure, pattern processing at the time of mask data creation is facilitated.

(Example 8)
FIG. 12B shows the second asymmetric data line of the present invention. SAs are interleaved with respect to the memory array. In this example, when looking at the boundary between the SA and the memory array, DL passes through the boundary and enters the SA (DL0B, DL2, DL2B, DL4), and ends at the boundary (DL1, DL1B, DL3, DL3B) ) Is repeated every other line. Such a data line arrangement is advantageous in the following case as compared with the arrangement (a). In the case of forming data lines by phase shift lithography, the 0 phase line pattern and the φ phase line pattern are alternately arranged. However, due to optical conditions or mask processing problems, the 0 phase pattern and the φ phase line pattern are arranged. An error may occur in the line width of the pattern. Even in such a case, since the same phase is assigned to the data line pairs (DL1 and DL1B, DL2 and DL2B, etc.) connected to the same SA in the data line arrangement of (b), the line width is within the pair. There is an advantage that the data line capacitance is not unbalanced.

  As for the unbalance of the data line capacity, as described above, since the difference in the data line length required in the present invention is very small with respect to the length of the data line itself, the unbalance is almost ignored. Is possible.

  In the above embodiments, the DRAM has been described as an example. However, the word line end and the data line end of the present invention can be applied to other types of memories such as a flash memory, an EEPROM, a mask ROM, and an SRAM.

Example 9
FIG. 13 shows a basic cell of a gate array using the asymmetric gate of the present invention. The basic cell is divided into a region where a PMOS transistor is arranged and a region where an NMOS transistor is arranged, and the PMOS is formed in an N-type well (NWEL). FG is the gate of the MOS transistor, ACT is the active region of the MOS transistor, CNT is the contact between FG and the first-layer metal wiring M1 (not shown), and CNTL is the contact between M1 and ACT.

  In the gate array, a semiconductor vendor prepares the basic cells created as shown in the figure, and the user lays out the contact between M1 or M1, the second layer metal wiring M2, and M1-M2 to realize a desired circuit. Take the design method. In the basic cell, ACTs are connected in the horizontal direction, and FGs are regularly arranged. CNTL is arranged between FGs. In the case of isolation, the NMOS has a gate connected to Vss and the PMOS has a gate connected to Vcc.

  In this example, assuming that the gate pitch is reduced and the pitch for arranging the FG is shortened, the dogbone regions of the contacts are alternately arranged from above and below the ACT. This method has an advantage that the layout of the dogbone becomes easy. On the other hand, at the end portions of the gates regularly arranged in this way, the problem of short circuit or disconnection occurs as in the case of the WL of the memory described above.

  Therefore, in the basic cell of the gate array of the present invention, the length of adjacent FG is changed to shift the tip, and the FG tip is inclined. By using such a mask pattern, it is possible to obtain an effect of preventing a short at the FG tip and a disconnection at the dog bone. Note that if the difference in the length of the FG is λ / (2NA) or more, the above effect is enhanced. When attention is paid only to the pattern, if the repetition pitch of the FG is PG, the above-described effect is great if the tip of the FG is shifted by PG / 2 or more. However, unnecessarily increasing the amount by which the tip is displaced leads to an increase in the chip area, so it is desirable to set it to λ / NA or less or PG or less. In addition, when the FG tip is inclined, if the edge of the FG is left with some sides perpendicular to the FG to prevent an acute angle, pattern processing at the time of mask data creation is facilitated.

It is the first asymmetric word line end of the present invention. It is an optical simulation result of the first asymmetric word line end of the present invention. It is a chip configuration diagram of a DRAM. It is a block diagram of an alternately arranged hierarchy WD system array. It is a circuit diagram of an alternately arranged hierarchical WD system array. It is the asymmetrical word line end and data line end of the present invention. It is the 2nd and 3rd asymmetrical word line end of the present invention. It is an optical simulation result of the 3rd asymmetrical word line end of the present invention. It is the 4th and 5th asymmetrical word line end of the present invention. It is an optical simulation result of the 4th asymmetrical word line end of the present invention of the present invention. It is an optical simulation result of the 5th asymmetrical word line end of the present invention of the present invention. It is a 1st asymmetrical data line end of this invention. It is a gate array using the asymmetric gate of the present invention. It is a conventional word line end. It is the optical simulation result of the conventional word tip. It is the optical simulation result of the conventional 2nd word tip.

Explanation of symbols

WL ... Word line SWD ... Sub word driver Shunt ... Word shunt area SA ... Sense amplifier MC ... Memory cell MWLB ... Main word line FX ... Sub word driver selection line SHRU, SHRD ... Shared SA selection line CSP ... PMOS common source CSN ... NMOS common source BLEQ ... data line equalize line VBLR ... data line reference power supply SIO, SIOB ... sub I / O line M1 ... wiring layer CONT ... contact ACT ... active region of MOS transistor CP ... auxiliary pattern SNCT ... capacitor contact DLCT ... data line contact FG ... Gate of MOS transistor NWEL ... N-type well region CNT ... Gate contact CNTL ... Diffusion layer contact

Claims (24)

A plurality of first word lines extending in a first direction, a plurality of data lines extending in a second direction intersecting the first direction, and intersections of the plurality of first word lines and the plurality of data lines A memory array unit having a plurality of first memory cells provided in
A first sub-word driver region having a plurality of first sub-word drivers arranged outside the memory array portion and connected to the plurality of first word lines; or the plurality of first sub-word drivers arranged outside the memory array portion. A first shunt region for shunting the word line to the metal wiring,
Each of the plurality of first word lines has one end connected to the plurality of sub word drivers or connected to the metal wiring, and the other end not connected to the plurality of sub word drivers or not connected to the metal wiring. Have
The other end of two adjacent word lines among the plurality of first word lines is formed to be shifted in the first direction.   2. The semiconductor device according to claim 1, wherein the other ends of the plurality of first word lines are disposed outside the memory array unit. The memory array unit further includes a plurality of second word lines extending in the first direction, and a plurality of second memory cells provided at intersections of the plurality of second word lines and the plurality of data lines. And
The semiconductor device includes a second sub-word driver region having a plurality of second sub-word drivers arranged outside the memory array section and connected to the plurality of second word lines, or shunts the plurality of second word lines. And a second shunt region for
The memory array unit is disposed between the first subword driver region and the second subword driver region, or between the first shunt region and the second shunt region.
Each terminal portion of the plurality of first word lines is disposed between the second sub-word driver region and the memory array unit, or between the second shunt region and the memory array unit. The semiconductor device according to claim 1, wherein the semiconductor device is characterized.   4. The semiconductor device according to claim 3, wherein the plurality of first word lines and the plurality of second word lines are alternately arranged every other line.   4. The semiconductor device according to claim 3, wherein the plurality of first word lines and the plurality of second word lines are alternately arranged every two lines.   The other two adjacent ends of the plurality of first word lines are shifted in the first direction by ½ or more of the pitch of two adjacent ones of the plurality of first word lines. The semiconductor device according to any one of claims 1 to 5.   7. The semiconductor device according to claim 6, wherein the other two other ends of the plurality of first word lines are shifted by a pitch of two or more adjacent ones of the plurality of first word lines. apparatus.   8. The semiconductor device according to claim 1, wherein a corner portion of any one of two adjacent ones of the plurality of first word lines is removed. 9. . An auxiliary pattern is provided at a connection portion between the plurality of first word lines and the plurality of first sub word drivers or the metal wiring,
In the case where the pitch between two adjacent ones of the plurality of first word lines is P,
The length of the auxiliary pattern in the first direction is P / 2 or more,
9. The semiconductor device according to claim 1, wherein a length of the auxiliary pattern in the second direction in the first half is P / 10 or more and P / 2 or less. 9.   10. The semiconductor device according to claim 1, wherein each of the plurality of first memory cells includes a selection transistor and a capacitor.   The semiconductor device according to claim 1, wherein the semiconductor device is a flash memory.   3. The semiconductor according to claim 1, wherein the plurality of first word lines are formed by shifting a phase of light passing through a line pattern serving as an adjacent word line by 180 degrees in an exposure step. apparatus. A plurality of word lines extending in a first direction, a plurality of first data lines extending in a second direction intersecting the first direction, and an intersection of the plurality of word lines and the plurality of first data lines A memory array unit having a plurality of first memory cells provided in
A first sense amplifier region having a plurality of first sense amplifiers disposed outside the memory array portion and connected to the plurality of first data lines;
Each of the plurality of first data lines has one end connected to a corresponding one of the plurality of first sense amplifiers and the other end not connected to the plurality of first sense amplifiers,
The other ends of two adjacent data lines among the plurality of first data lines are formed shifted in the second direction,
Two adjacent data lines of the plurality of first data lines are sandwiched between two adjacent word lines of the plurality of word lines, and a corresponding memory of the plurality of first memory cells. A first region connected to the cell, and a second region sandwiched between two adjacent word lines of the plurality of word lines and not connected to the plurality of first memory cells,
The width in the first direction of the plurality of first data lines in the first region is the same as the width in the first direction of the plurality of first data lines in the second region. apparatus.   The other end of the plurality of first data lines is disposed outside the memory array section. The memory array unit further includes a plurality of second data lines extending in the second direction, and a plurality of second memory cells provided at intersections of the plurality of word lines and the plurality of second data lines. And
The semiconductor device further includes a second sense amplifier region having a plurality of second sense amplifiers disposed outside the memory array portion and connected to the plurality of second data lines,
The memory array unit is disposed between the first sense amplifier region and the second sense amplifier region,
15. The semiconductor device according to claim 13, wherein the other end of each of the plurality of first data lines is disposed between the second sense amplifier region and the memory array unit.   16. The semiconductor device according to claim 15, wherein the plurality of first data lines and the plurality of second data lines are alternately arranged every other line.   The semiconductor device according to claim 15, wherein the plurality of first data lines and the plurality of second data lines are alternately arranged every two lines.   Two adjacent terminal portions of the plurality of first data lines are shifted in the second direction by a half or more of a pitch of two adjacent ones of the plurality of first data lines. The semiconductor device according to any one of claims 13 to 17.   19. The semiconductor device according to claim 18, wherein the other two other ends of the plurality of first data lines are deviated by the pitch of two adjacent ones of the plurality of first data lines. apparatus.   20. The semiconductor device according to claim 13, wherein a corner portion of one of two adjacent ones of the plurality of first data lines is removed. . An auxiliary pattern is provided at a connection portion between the plurality of first sense amplifiers and the plurality of first data lines.
In the case where the pitch between two adjacent ones of the plurality of first data lines is P,
A length of the auxiliary pattern in the second direction is P / 2 or more;
21. The semiconductor device according to claim 13, wherein a length of the auxiliary pattern in the first direction in the first period is P / 10 or more and P / 2 or less.   22. The semiconductor device according to claim 13, wherein each of the plurality of first memory cells includes a selection transistor and a capacitor.   The semiconductor device according to any one of claims 13 to 21, wherein the semiconductor device is a flash memory.   15. The semiconductor device according to claim 13, wherein the plurality of first data lines are formed by shifting a phase of light passing through a line pattern serving as an adjacent data line by 180 degrees in an exposure process. apparatus.

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