JPH02177558A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent the ununiformity of elements in characteristics by a method wherein a dummy pattern is provided to a region adjacent to the outside of the end of repeating pattern of memory cells or the like. CONSTITUTION:A field oxide film 2, a gate oxide film 3, and a gate electrode layer 4 are formed on a silicon substrate 1, and photoresist patterns 5-7 whose width is L and which are used for the formation of gate electrodes are formed on element forming regions partitioned by the field oxide film 2 respectively. A dummy pattern region 8 partitioned by the field oxide film 2 is formed outside the most peripheral pattern of a memory cell and has the same shape (size) as a unit pattern of a memory cell. Therefore, in these memory cells, as a surrounding pattern (dummy pattern) outside the photoresist pattern 5 has the same shape as the other photoresist patterns 6 and 7, so that the width L of the pattern 5 becomes nearly equal to those of the inner patterns 6 and 7. By this setup, elements are prevented from being ununiform in characteristics and deteriorating in performance due to the ununiformity of photoresist patterns in size.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device in which fine patterns are formed with high precision.

[Prior Art] Recently, with advances in microfabrication technology such as lithography technology and etching technology, the design dimensions of LSIs (integrated circuit devices) have become smaller and smaller, reaching the submicron range.

For this reason, subtle dimensional changes have a large impact on the characteristics of LSIs. Therefore, it is extremely important to form fine patterns according to the designed dimensions.

FIG. 3 is a cross-sectional view showing the element structure at the end of the memory cell after forming a photoresist pattern for forming the gate electrode of the MOS transistor constituting the memory cell in the manufacturing process of the semiconductor memory cell. A field oxide film 12 is formed on the silicon substrate 11 to insulate and isolate the MOS transistors of each memory cell. A gate oxide film 13 is formed on the surface of the substrate 11, and a gate electrode layer 14 is formed on the field oxide M12 and the gate oxide film 13.

Additionally, photoresist patterns 15 and 16 are applied to selectively cover the gate electrode subdivisions of the gate electrode layer 14.
．． 17 is formed. Photoresist pattern 15,
16, 17 have a width, and photoresist patterns 16, 17, . . . 16, 17, . ...is placed.

Although the patterns of field oxide films, gate electrodes, etc. differ depending on the type of LSI, the same repeating pattern is formed within each memory cell.

[Problem to be solved by the invention] However, in the conventional memory cell described above,
Photoresist pattern for gate electrode formation 15.16.1
There is a problem in that the width dimension of the memory cell 7 is different between the outermost peripheral portion and the inside of the memory cell.

FIG. 4 shows the dimensions of the photoresist patterns obtained when the designed dimensions of the photoresist patterns 15, 16, and 17 for forming gate electrodes shown in FIG. 3 are approximately 1.0 μm. FIG. 3 is a graph diagram illustrating the difference from the design dimension from the photoresist pattern 15 (Nal) at the outer periphery of the memory cell toward the pattern 16.17° (Na2, 3, . . .) toward the inside. As is clear from this figure, the gate electrode pattern at the outermost periphery of the memory cell (
Nal) has a larger width than other gate electrode patterns. Note that, as described above, the pattern at the outermost periphery may become thicker in some cases, but it may also become thinner depending on the resist film thickness and the like. This is because the patterns around the outermost photoresist pattern 15 are different, resulting in a change in the resist coating thickness and the occurrence of multiple interference effects.

For this reason, the dimensions of the gate electrode formed at the outermost periphery of the memory cell are significantly different from the dimensions of other gate electrodes formed inside the memory cell, so that the transistor performance differs between that at the outermost periphery and that inside the memory cell. There is a problem that they do not match. This causes problems such as a decrease in the yield of semiconductor integrated circuits and a deterioration in performance.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a semiconductor integrated circuit device that can avoid unevenness in device characteristics and deterioration in performance due to uneven dimensions of a photoresist pattern and has a high manufacturing yield.

[Means for Solving the Problems] A semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device including a repeating pattern in which unit patterns are consecutively formed. The device is characterized in that at least one dummy pattern is provided in a region adjacent to the end portion, which is not involved in the circuit operation of the device and has the same shape as the unit pattern.

[Function] The present invention includes a repeating pattern necessary for circuit operation of the device and at least one dummy pattern having the same shape as a unit pattern of the repeating pattern. Therefore, when a photoresist pattern is formed in the entire area of this repeated pattern and dummy pattern, even if the outermost pattern of the entire area is formed with different dimensions from the inner pattern, this outermost pattern Since the pattern is a dummy pattern and is not involved in the circuit operation of the device, it is possible to avoid unevenness in device characteristics and the resulting deterioration in device performance.

[Example] Next, an example of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a sectional view showing an embodiment in which the present invention is applied to a semiconductor memory cell. FIG. 1 shows the process of patterning the gate electrode of a MOS transistor constituting a memory cell. A device in which a field oxide film 2, a gate oxide wA3, and a gate electrode layer 4 are formed on a silicon substrate 1, and a photoresist pattern 5.6.7 having a width dimension of L for forming a gate electrode is partitioned by the field oxide film 2. They are formed in the respective formation areas. The photoresist pattern 5 is a MOS placed on the outermost periphery of the memory cell.
) This photoresist pattern is for forming a gate electrode of a transistor, and each photoresist pattern is sequentially arranged from photoresist pattern 5 to pattern 6 and 7 toward the inside of the cell.

These photoresist patterns 5, 6, 7, etc. form gate electrodes of MOS transistors constituting the memory cells.

A dummy pattern region 8 partitioned off by field oxide film 2 is formed outside the outermost pattern of this memory cell. This dummy pattern has the same shape (dimensions) as each unit pattern of the memory cell.

In the memory cell of this embodiment configured as described above, the outer peripheral pattern (dummy pattern) of the photoresist pattern 5 is the same as the other photoresist patterns 6.7, so the width dimension of the pattern 5 is different from that of the photoresist pattern 5. The width dimension is approximately equal to that of the internal pattern 6.7. That is, in a pattern with a design dimension of approximately 1.0 μm, pattern 5
Since the dimensional difference is the dimensional difference of the pattern at the position N1L2 in Fig. 4, it is clear from Fig. 4 that this dimensional difference is ±
It is suppressed to an extremely small size of 0.05 μm or less.

FIG. 2 is a sectional view of a memory cell portion showing another embodiment of the present invention. In the first embodiment described above, only the dummy pattern region 8 partitioned by the field oxide film 2 is formed in the region adjacent to the end of the memory cell, whereas in this embodiment, this dummy pattern region 8, a photoresist dummy pattern 9 of a gate electrode is formed. This dummy pattern 9 has the same design dimensions as the photoresist patterns 5, 6.7 for forming gate electrodes.

In this embodiment configured in this manner, in addition to the effects of the first embodiment, the surrounding conditions during development can be made similar between the outermost peripheral portion and the inside of the memory cell. This has the advantage that dimensional control can be performed more stably.

Although the above embodiments have been described with respect to memory cells, it is clear that similar effects can be obtained with peripheral circuits and the like.

[Effects of the Invention] As explained above, in the present invention, the dummy pattern is provided in the area adjacent to the outside of the end of the repetitive pattern of memory cells, etc. Therefore, in the repetitive pattern area necessary for circuit operation, the photoresist pattern is This has the excellent effect of reducing dimensional differences. This lick,
Non-uniformity in device characteristics is prevented, the performance of the semiconductor integrated circuit device is improved, and the manufacturing yield is also improved.

[Brief explanation of the drawing]

Fig. 1 is a sectional view showing an embodiment of the present invention, Fig. 2 is a sectional view showing another embodiment of the invention, Fig. 3 is a sectional view for explaining a conventional example, and Fig. 4 is a resist dimension. It is a graph figure showing the relationship between the formation position and the formation position. 1.11; silicon substrate, 2, 12; field oxide film, 3.13. Gate oxide film, 4, 14: gate electrode layer,
5.6.7.15, 16.17; Photoresist pattern, 8; Dummy pattern area, 9; Photoresist dummy pattern

Claims (1)

[Claims] (1) In a semiconductor integrated circuit device having a repeating pattern in which unit patterns are continuously formed, a region adjacent to an end of the region where the repeating pattern is formed is not involved in the circuit operation of the device, and the unit pattern is not involved in the circuit operation of the device. 1. A semiconductor integrated circuit device comprising at least one dummy pattern having the same shape as .