JPH04345313A - C-mos logarithmic if amplifier - Google Patents

Abstract

PURPOSE:To secure the linearity in the logarithmic characteristic by interconnecting stages of IF amplifiers with series connection capacitors, applying a signal to a rectifier via a 2nd coupling capacitor so as to reduce a 1/f noise thereby minimizing the deterioration in the NF and extending the input band of the rectifier up to a low frequency. CONSTITUTION:IF amplifiers Ai (i=1,2,3,...) are arranged in cascade and multi- stage to amplify an IF signal sequentially. Then a capacitance of an inter-stage coupling capacitor CA of the IF amplifiers Ai and a capacitance of a coupling capacitor CBi of rectifiers Bi are made different and the IF amplifier Ai of each stage is connected by the capacitors CAi and CBi connected in series. Then a signal is fed from the midpoint between the capacitors CAi and CBi to the rectifiers Bi and the output is fed to an adder C. Thus, a low frequency is cut off at a band of the IF amplifier Ai and the frequency is extended up to a low frequency at a band of the rectifier Bi to realize the amplifiers formed on a C-MOS integrated circuit without trouble.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a C-MOSIF logarithmic amplifier formed on a C-MOS integrated circuit.

0002

2. Description of the Related Art As is well known, a logarithmic IF amplifier is composed of IF amplifiers connected in series in multiple stages, a rectifier that receives the output of each IF amplifier, and an adder that adds the outputs of all the rectifiers. However, the conventional logarithmic IF amplifier is
Generally formed on bipolar integrated circuits. This is because bipolar transistors have good noise characteristics and little deterioration in sensitivity when viewed from the receiver input, and the transistor itself has high drive capability, so it can be driven with low impedance or large capacitance. There is.

0003

[Problem to be Solved by the Invention] However, C-MOS integrated circuits also have various advantages, and the development of a C-MOS logarithmic IF amplifier is desired, but in that case, how should the rectifier be configured? In addition to this problem, there are the following problems. That is, when configuring a C-MOS logarithmic IF amplifier,
Since C-MOS transistors have large 1/f noise,
If the low range of the IF band is not cut, the deterioration in sensitivity when viewed from the receiver input will be significant. This HPF characteristic that cuts the low frequency range can be equivalently obtained by coupling the IF amplifiers connected in multiple stages with a capacitor, but it is desirable that the value thereof be small. On the other hand, in the case of capacitor coupling, the logarithmic IF
Since the signal waveform is differentiated in the rectifier that constitutes the amplifier, the DC value of the rectifier output tends to fluctuate. Therefore, in order to obtain logarithmic characteristics with good linearity, it is necessary to widen the input frequency band of the rectifier to a low frequency range, that is, it is necessary to use a coupling capacitor with a large value. Then, I
The driving ability of the F amplifier becomes a problem.

An object of the present invention is to cut the low frequency range in the IF amplifier band and extend it to the low range in the rectifier band, thereby creating a C-MOS logarithmic IF that can be formed without any trouble on a C-MOS integrated circuit. The purpose is to provide an amplifier.

[0005]

Means for Solving the Problems In order to achieve the above object, the C-MOS logarithmic IF amplifier of the present invention has the following configuration. That is, the C-MOS logarithmic IF amplifier of the first invention includes IF amplifiers connected in cascade in multiple stages via a first coupling capacitor; and a signal is supplied from the IF amplifier in each stage via a second coupling capacitor. a rectifier that receives the rectifier; an adder that adds the outputs of all the rectifiers; and the first coupling capacitor and the second coupling capacitor each have a different capacitance.

Further, the C-MOS logarithmic IF amplifier of the second invention includes: IF amplifiers arranged in series in multiple stages; and a coupling capacitor connecting the IF amplifiers in each stage, two of which are connected in series. The present invention is characterized by comprising: a capacitor; a rectifier that receives a signal at the midpoint of the series capacitor; and an adder that adds the outputs of all the rectifiers.

[0007]

[Operation] Next, the C-MO of the present invention configured as described above
The operation of the S-logarithm IF amplifier will be explained. C-MO of the present invention
In the S-logarithmic IF amplifier, the interstage coupling capacitor of the IF amplifier and the coupling capacitor of the rectifier each have a different capacitance (first invention), and each stage of the IF amplifier is coupled with a capacitor connected in series. A signal is supplied to the rectifier from the midpoint of the capacitors connected in series (second invention). As a result, the low frequency band can be cut in the IF amplifier band, and the low frequency band can be expanded to the low frequency band in the rectifier band.

Thus, according to the present invention, it is possible to reduce the 1/f noise of the IF amplifier and minimize the deterioration of the NF.
In addition, the input band of the rectifier can be extended to low frequencies to ensure linearity of logarithmic characteristics. That is, a C-MOS logarithmic IF amplifier can be realized.

[0009]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a C-MOS logarithmic IF amplifier according to an embodiment of the present invention. In FIG. 1, the IF amplifier Ai(i
=1, 2, 3, . . . ) are arranged in cascade in multiple stages to sequentially amplify the IF signal, and the IF amplifiers in each stage are connected by series-connected capacitors CAi and CBi. The rectifier Bi receives a signal from the midpoint between the capacitors CAi and CBi and outputs the signal to the adder C.

The rectifier Bi may be any rectifier as long as it is constructed of C-MOS, but in this embodiment, for example, a square circuit shown in FIG. 2 is used. This is related to the development of the present applicant and is detailed in Japanese Patent Laid-Open No. 63-024377, so it will not be described again, but if this is used, the rectifier Bi becomes a square double wave rectifier.

Now, since the input of the rectifier Bi is the gate of the transistor, it has high impedance.
The gate DC bias can also be made high impedance. Therefore, the combined capacitance Ci of capacitors CAi and CBi can be calculated by the following formula 1, ignoring the input impedance of the rectifier.
It can be approximated by On the other hand, the coupling capacitor with the rectifier is CAi, as shown in FIG.

0012

[Math 1]

Furthermore, since the low range of the band is determined by the differential characteristics (HPF characteristics) of each coupling capacitor, the low cutoff frequency fcIFi of the IF amplifier Ai
The ratio of the low cutoff frequency fcRECTi of the rectifier Bi is expressed by the following equation 2, and fcIFi can be made higher than fcRECTi.

[0014]

[Math 2]

That is, the load capacitance of the IF amplifier Ai is Ci
However, if CAi=CBi=C0, then from Equation 1, Ci=(1/2)C0, and the capacitance of the interstage coupling capacitor of the IF amplifier is half the capacitance of the coupling capacitor with the rectifier. Also, from formula 2, fcIFi=2fcR
ECTi, and the low band of the rectifier is lowered to half that of the IF amplifier.

[0016] As is clear from the above examples, I
Instead of connecting the stages of the F amplifier with series capacitors, it is also possible to connect the stages with one capacitor, use another capacitor for the rectifier, and make the capacitances of both capacitors different.

[0017]

Effects of the Invention As explained above, the C-MO of the present invention
According to the S-logarithmic IF amplifier, the interstage coupling capacitor of the IF amplifier and the coupling capacitor of the rectifier have different capacitances (first invention), and the coupling of each stage of the IF amplifier is connected by a capacitor connected in series. Since the signal is supplied to the rectifier from the midpoint of the capacitors connected in series (second invention), it is possible to cut the low range in the IF amplifier band and extend it to the low range in the rectifier band. . Therefore, according to the present invention, it is possible to provide a C-MOS logarithmic IF amplifier that can be formed on a C-MOS integrated circuit without any problems.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a C-MOS logarithmic IF amplifier according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a rectifier.

[Explanation of symbols]

A1 IF amplifier A2 IF amplifier A3 IF amplifier A4 IF amplifier A5 IF amplifier B1 Rectifier B2 Rectifier B3 Rectifier B4 Rectifier B5 Rectifier C Adder

Claims (2)

[Claims] 1. IF amplifiers connected in cascade in multiple stages via a first coupling capacitor; a rectifier receiving a signal from the IF amplifier in each stage via a second coupling capacitor; outputs of all rectifiers; an adder that adds;
A C-MOS logarithmic IF amplifier comprising: the first coupling capacitor and the second coupling capacitor each having a different capacitance. 2. IF amplifiers arranged in cascade in multiple stages;
a series capacitor formed by connecting two coupling capacitors in series, which connect the IF amplifiers of each stage;
A C-MOS logarithmic IF amplifier comprising: a rectifier that receives a signal at the midpoint of the series capacitor; and an adder that adds the outputs of all the rectifiers.