JPH043452A - Resin sealed semiconductor device - Google Patents
Resin sealed semiconductor deviceInfo
- Publication number
- JPH043452A JPH043452A JP10304290A JP10304290A JPH043452A JP H043452 A JPH043452 A JP H043452A JP 10304290 A JP10304290 A JP 10304290A JP 10304290 A JP10304290 A JP 10304290A JP H043452 A JPH043452 A JP H043452A
- Authority
- JP
- Japan
- Prior art keywords
- bed
- lead
- inner lead
- resin
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 239000011347 resin Substances 0.000 title claims abstract description 20
- 229920005989 resin Polymers 0.000 title claims abstract description 20
- 238000007789 sealing Methods 0.000 claims description 2
- 238000005520 cutting process Methods 0.000 abstract description 10
- 238000000034 method Methods 0.000 abstract description 8
- 239000000853 adhesive Substances 0.000 abstract description 4
- 230000001070 adhesive effect Effects 0.000 abstract description 4
- 238000005452 bending Methods 0.000 abstract 3
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000007591 painting process Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000007730 finishing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
Description
【発明の詳細な説明】
［発明の目的コ
（産業上の利用分野）
本発明は、樹脂封止型半導体装置に関するもので、特に
、この種の装置に使用されるリードフレームの構造に関
するものである。[Detailed Description of the Invention] [Purpose of the Invention (Field of Industrial Application) The present invention relates to a resin-sealed semiconductor device, and in particular to the structure of a lead frame used in this type of device. be.
（従来の技術） 第２図に従来の樹脂封止型半導体装置の断面図を示す。(Conventional technology) FIG. 2 shows a cross-sectional view of a conventional resin-sealed semiconductor device.
この種の樹脂封止型半導体装置では、一般に、ベット２
１及びインナーリード２６とアウターリード２７とが同
一平面になす平板状の構造のリードフレムが使用され、
そのリードフレームのベット２１上に、接着剤２２を介
して半導体チップ２３を接着し、半導体チップ２３の電
極部２４とインナーリード２６とをボンディングワイヤ
ー２５で接続し、前記ベット２１、半導体チップ２３及
びインナーリード２６とを樹脂体２８で封止する。その
後、リードフレームの不要な部材を切り落し、アウター
リード２７を矢印に示すように折り曲げる工程（以下、
カッティング及びペンティング工程と言う）などの仕上
げを行って樹脂封止型半導体装置を完成する。In this type of resin-sealed semiconductor device, generally the bed 2 is
1, and a lead frame having a flat structure in which the inner leads 26 and the outer leads 27 are on the same plane is used,
A semiconductor chip 23 is bonded onto the bed 21 of the lead frame via an adhesive 22, and the electrode portion 24 of the semiconductor chip 23 and the inner lead 26 are connected with a bonding wire 25. The inner leads 26 are sealed with a resin body 28. Thereafter, a step (hereinafter referred to as
The resin-sealed semiconductor device is completed by finishing processes such as cutting and painting processes.
上記従来技術においては、リードフレームのベット及び
インナーリードとアウターリードとが同一平面をなす平
板状構造のため、以下のような問題がある。The above conventional technology has the following problems because it has a flat structure in which the bed of the lead frame, the inner leads, and the outer leads are on the same plane.
すなわち、カッティング及びペンティング工程にＩおい
て、機械による横方向に引張られる力が麹リードにかか
り、パッケージ内のインナーリード及びボンディングワ
イヤーと樹脂体との接合部界面に応力が生じる。そのた
め、リードと樹脂体との密着性が悪くなり、これらの間
に間隙か生じ、この間隙から水分が侵入しコロ−ジョン
現象が発生し、製品としての信頼性、歩留りが劣化して
いた。また、ボンディングワイヤーに応力がかかり、こ
のボンディングワイヤーが伸長し弱くなったり、切断し
たりして、製品としての信頼性、歩留りが劣化していた
。That is, in the cutting and penting process I, a force applied in the lateral direction by the machine is applied to the koji lead, and stress is generated at the inner lead in the package and at the interface between the bonding wire and the resin body. As a result, the adhesion between the lead and the resin body deteriorates, creating a gap between them, allowing moisture to enter through the gap, causing a corrosion phenomenon and deteriorating the reliability and yield of the product. In addition, stress is applied to the bonding wire, causing the bonding wire to stretch, become weak, or break, resulting in deterioration in product reliability and yield.
（発明が解決しようとする課題）
本発明は、上記のような欠点を除去し、カッティング及
びペンティング工程で発生する応力をインナーリード部
及びベット部で阻止することにより、この応力によるパ
ッケージ内のインナーリード及びボンディングワイヤー
と樹脂体との接合部界面のストレスをなくし、樹脂封止
型半導体装置の信頼性・歩留りを向上させることを目的
とする。(Problems to be Solved by the Invention) The present invention eliminates the above-mentioned drawbacks and prevents the stress generated in the cutting and penting processes at the inner lead portion and the bed portion, thereby reducing the damage caused by this stress within the package. The purpose is to eliminate stress at the joint interface between the inner lead and bonding wire and the resin body, and to improve the reliability and yield of resin-sealed semiconductor devices.
［発明の構成］
（課題を解決するための手段）
上記目的を達成するために、本発明においては、上面に
半導体チップを載置したベットと、インナーリード部と
アウターリード部とを有するリードと、前記ベット、半
導体チップ及びインナーリード部を封止する樹脂体とを
具備した樹脂封止型半導体装置において、前記アウター
リード部の平面と、前記ベット及びインナーリード部の
平面とを異ならしめたことを特徴とする樹脂封止型半導
体装置を提供する。[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides a bed on which a semiconductor chip is mounted, a lead having an inner lead portion and an outer lead portion. , in a resin-sealed semiconductor device comprising the bed, a semiconductor chip, and a resin body for sealing the inner lead portion, a plane of the outer lead portion is different from a plane of the bed and the inner lead portion; A resin-sealed semiconductor device is provided.
（作用）
このように構成されたものにおいては、ベット及びイン
ナーリードの平面とアウターリードの平面とを異ならし
めることにより、カッティング及びベツティング工程の
際に、パッケージ内のインナーリード部及びベット部に
発生する応力を阻止することができる。そのため、パッ
ケージ内のインナーリード及びボンディングワイヤーと
樹脂体との接合部界面にかかるストレスをおさえること
ができ、特に、インナーリードと樹脂体との間隙が発生
しなくなり、樹脂封止型半導体装置の信頼性・歩留りか
向上する。(Function) In the device configured in this way, by making the planes of the bet and inner leads different from the planes of the outer leads, the inner leads and the bet part in the package are made different during the cutting and betting process. The stress generated can be prevented. Therefore, the stress applied to the joint interface between the inner leads and bonding wires in the package and the resin body can be suppressed, and in particular, there is no gap between the inner leads and the resin body, which increases the reliability of resin-sealed semiconductor devices. Improves performance and yield.
（実施例） 以下、本発明の一実施例を第１図を参照して説明する。(Example) An embodiment of the present invention will be described below with reference to FIG.
図示の如く、この実施例では、リードフレームは、ベッ
ト１１及びインナーリード１６の支持リードを途中で曲
げ、ベット１１及びインナーリド１６の平面と、樹脂体
１８より外部にのびるアウターリードの１７の平面との
高さを異ならしめる。As shown in the figure, in this embodiment, the lead frame has support leads of the bed 11 and the inner lead 16 bent in the middle, and a flat surface of the bed 11 and the inner lead 16 and a flat surface of the outer lead 17 extending outside from the resin body 18. and the height is different.
更に、このベット１１の上面に接着剤１２を介して半導
体チッ゛ブ１３を接着し、半導体チップ１３の電極部１
４とインナーリード１Ｂをボンディングワイヤー１５で
接続し、前記ベット１１、半導体チップ１３、及びイン
ナーリード１６とを樹脂体１８で封止し、カッティング
及びペンティング工程を施し、樹脂封止型半導体装置を
完成する。Furthermore, a semiconductor chip 13 is adhered to the upper surface of this bed 11 via an adhesive 12, and the electrode portion 1 of the semiconductor chip 13 is
4 and the inner lead 1B are connected with a bonding wire 15, the bed 11, the semiconductor chip 13, and the inner lead 16 are sealed with a resin body 18, and a cutting and painting process is performed to form a resin-sealed semiconductor device. Complete.
本実施例によれば、ベット及びインナーリードの平面と
アウターリードの平面との高さを異ならしめているため
、カッティング及びペンティング工程の際に生しる応力
が阻止できる。パッケージ内のインナーリード及びボン
ディングワイヤーと樹脂体との接合部界面にかかるスト
レスか弱まる。According to this embodiment, the heights of the planes of the bed and inner leads and the planes of the outer leads are made different, so that stress generated during the cutting and penting processes can be prevented. The stress applied to the inner lead in the package and the bonding interface between the bonding wire and the resin body is reduced.
したかって、従来技術のようなリードと樹脂体との間に
間隙か生じ、この間隙から水分が侵入してコロ−ジョン
現象が発生することがなくなる。また、ボンディングワ
イヤーか伸長し弱まったり、切断したりすることがなく
なる。そのため、樹脂封止型半導体装置の信頼性・歩留
りを向上させることができる。Therefore, unlike the prior art, a gap is created between the lead and the resin body, and moisture infiltrates through this gap to cause corrosion. Also, the bonding wire will not stretch, weaken, or break. Therefore, the reliability and yield of the resin-sealed semiconductor device can be improved.
本実施例では、アウターリードに対して、インナーリー
ド及びベットを上方に位置させることにより、両者の平
面を異ならしめているが、インナリード及びベットを下
方に位置させてアウタリードを平面を異ならしめた場合
においても上記と同様な効果が得られる。In this embodiment, the inner lead and the bet are positioned above the outer lead to make the planes of the two different, but if the inner lead and the bet are positioned below and the outer lead has a different plane. The same effect as above can also be obtained.
［発明の効果コ
以上、詳述したように本発明によれば、カッティング及
びペンティング工程の際に生じる応力を阻止できるので
、応力によるパッケージ内のインナーリード及びボンデ
ィングワイヤーと樹脂体との接合部界面にかかるストレ
スか弱まり、リードと樹脂体との間に間隙か発生しなく
なり、また、ボンディングワイヤーが伸長し弱まったり
切断したりすることがなくなり、樹脂封止型半導体装置
の信頼性・歩留りか向上する。[Effects of the Invention] As detailed above, according to the present invention, the stress generated during the cutting and penting processes can be prevented, so that the joints between the inner leads and bonding wires in the package and the resin body due to stress can be prevented. The stress on the interface is reduced, no gaps are created between the leads and the resin body, and the bonding wires are no longer stretched, weakened, or cut, which improves the reliability and yield of resin-sealed semiconductor devices. improves.
第１図は、本発明の樹脂封止型半導体装置を示す断面図
、第２図は、従来の樹脂封止型半導体装置を示す断面図
である。
１１．２１・・・ベット、
１２．２２・・・接着剤、
１３．２３・・・半導体チップ、
１４．２４・・・電極部、
１５．２５・・・ボンディングワイヤ、１６．２６・・
・インナーリード、
１７．２７・・・アウターリード、
１８．２８・・・樹脂体。FIG. 1 is a sectional view showing a resin-sealed semiconductor device of the present invention, and FIG. 2 is a sectional view showing a conventional resin-sealed semiconductor device. 11.21... Bed, 12.22... Adhesive, 13.23... Semiconductor chip, 14.24... Electrode portion, 15.25... Bonding wire, 16.26...
- Inner lead, 17.27... Outer lead, 18.28... Resin body.
Claims (1)
と、 前記ベット、半導体チップ及びインナーリード部を封止
する樹脂体とを具備した樹脂封止型半導体装置において
、 前記アウターリード部の平面と、 前記ベット及びインナーリード部の平面とを異ならしめ
たことを特徴とする樹脂封止型半導体装置。[Scope of Claims] A resin comprising: a bed on which a semiconductor chip is mounted; a lead having an inner lead portion and an outer lead portion; and a resin body for sealing the bed, the semiconductor chip, and the inner lead portion. 1. A resin-sealed semiconductor device, wherein a plane of the outer lead portion is different from a plane of the bed and the inner lead portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10304290A JPH043452A (en) | 1990-04-20 | 1990-04-20 | Resin sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10304290A JPH043452A (en) | 1990-04-20 | 1990-04-20 | Resin sealed semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH043452A true JPH043452A (en) | 1992-01-08 |
Family
ID=14343612
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10304290A Pending JPH043452A (en) | 1990-04-20 | 1990-04-20 | Resin sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH043452A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62184125A (en) * | 1986-02-10 | 1987-08-12 | Toa Nenryo Kogyo Kk | Production of carbon yarn and graphite yarn |
| US5889658A (en) * | 1997-11-25 | 1999-03-30 | Motorola, Inc. | Package assembly for an electronic component |
| WO2012017918A1 (en) | 2010-08-06 | 2012-02-09 | 日立建機株式会社 | Electromagnetic drive unit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4833999A (en) * | 1971-09-02 | 1973-05-15 | ||
| JPS61137352A (en) * | 1984-12-10 | 1986-06-25 | Hitachi Ltd | Semiconductor device |
-
1990
- 1990-04-20 JP JP10304290A patent/JPH043452A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4833999A (en) * | 1971-09-02 | 1973-05-15 | ||
| JPS61137352A (en) * | 1984-12-10 | 1986-06-25 | Hitachi Ltd | Semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62184125A (en) * | 1986-02-10 | 1987-08-12 | Toa Nenryo Kogyo Kk | Production of carbon yarn and graphite yarn |
| JPH043453B2 (en) * | 1986-02-10 | 1992-01-23 | ||
| US5889658A (en) * | 1997-11-25 | 1999-03-30 | Motorola, Inc. | Package assembly for an electronic component |
| WO2012017918A1 (en) | 2010-08-06 | 2012-02-09 | 日立建機株式会社 | Electromagnetic drive unit |
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