JPH04343519A - Input circuit - Google Patents

Abstract

PURPOSE:To prevent the flowing of a through current between power supply terminals and to prevent the generation of a malfunction in a semiconductor device. CONSTITUTION:Two MOS transistors M1, M2 constituting the input circuit are set up so that the sum of the absolute values of thresholds is more than the potential difference (Vcc-Vss) of both sources. Thereby even when the input potential of an input terminal IN is an intermediate level the MOS TRs M1, M2 are not simultaneously turned on. Consequently the flowing of a through current between both power supply terminals Vcc, Vss can be prevented and the generation of the malfunction in the semiconductor device can be prevented.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention particularly relates to an input circuit used in a CMOS type semiconductor device.

0002

2. Description of the Related Art FIG. 1 is a circuit diagram showing an example of the connection relationship between elements of a conventional input circuit. The P-channel MOS transistor M1 has its source connected to the power supply terminal VCC, its drain connected to the input terminal of the internal circuit, and its gate connected to the input terminal IN. N channel MO
The S transistor M2 has its source connected to the power supply terminal (ground terminal) VSS, its drain connected to the input terminal of the internal circuit, and its gate connected to the input terminal IN. Note that the sum of the absolute values of the threshold values of the P-channel MOS transistor M1 and the N-channel MOS transistor M2 is set to be sufficiently smaller than the power supply voltage (VCC-VSS).

In the input circuit configured as described above, when the potential of the input terminal IN is at High level or Low level, the internal circuit has a Low level or High level.
A level signal is supplied.

FIG. 2 is a circuit diagram showing the connection relationship of another example of the conventional input circuit. P-channel MOS transistors M3 and M4 are connected in parallel between the power supply terminal VCC and the input terminal of the internal circuit, the gate of P-channel MOS transistor M3 is connected to control terminal S, and the gate of P-channel MOS transistor M4 is connected to control terminal S. is input terminal I
Connected to N. N channel MOS transistor M
5 and M6 are connected in series between the input terminal of the internal circuit and the power supply terminal VSS, the gate of the N-channel MOS transistor M5 is connected to the input terminal IN, and the gate of the N-channel MOS transistor M6 is connected to the control terminal S. It is connected to the. Note that the P-channel MOS transistor M
The sum of the absolute values of the threshold values of the N-channel MOS transistor M4 and the N-channel MOS transistor M5 is set to be sufficiently smaller than the power supply voltage (VCC-VSS).

In the input circuit configured as described above, when the potential of the input terminal IN is at High level or Low level, the internal circuit has a Low level or High level.
When a high level signal is supplied and the control signal input to the control terminal S is low level, the MOS transistor M6 is turned off, so that a through current flows between the power supply terminals VSS and VSS. can be prevented.

[0006]

However, in the input circuit of FIG. 1, the input potential of the input terminal IN is lower than VSS.
and VSS, MOS transistors M1 and M2 are simultaneously turned on. That is, as shown in FIG.
1, M2 threshold value |VTN|, |VTP| is smaller than VCC-VSS, the input potential becomes VSS+
When VTN to VCC-|VTP|, MOS transistors M1 and M2 are simultaneously turned on. This poses a problem in that a through current flows between the power supply terminals VSS. Depending on the configuration of the semiconductor device, if the above-described through current occurs, the entire device may malfunction.

On the other hand, in the input circuit of FIG. 2, generation of through current can be prevented when the control signal is at a low level, but when the control signal is at a high level, the power supply terminal is A through current flows between VSS and the power supply terminal VSS.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an input circuit that can prevent the flow of through current and prevent malfunction of a semiconductor device.

[0009]

[Means for Solving the Problems] An input circuit according to the present invention includes a first MOS transistor of a first conductivity type whose gate is commonly connected to an input terminal and whose drain is commonly connected to an input terminal of an internal circuit; It has a second MOS transistor of a second conductivity type, and the first and second MOS transistors are characterized in that the sum of the absolute values of their thresholds is greater than or equal to the potential difference between their sources.

0010

[Operation] In the present invention, since the sum of the absolute values of the threshold values of the first and second MOS transistors is greater than the potential difference between the two sources, even if the input potential of the input terminal is at an intermediate level, the first MOS transistor and the second MOS transistor are never turned on at the same time. Thereby, it is possible to prevent a through current from flowing, and it is possible to prevent malfunction of the semiconductor device. Furthermore, when the input potential of the input terminal is at a high level or low level that deviates from the intermediate level, the first or second MOS transistor is turned on, so a low level or high level signal is supplied to the internal circuit. , operates as a normal input circuit.

[0011]

Embodiments Next, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing an input circuit according to a first embodiment of the present invention. In this embodiment, the connection relationship of each element is the same as that of the conventional one described above, and the MOS
The threshold values of transistors M1 and M2 are different from the conventional ones. That is, P channel MOS transistor M1
and N-channel MOS transistor M2, the sum of the absolute values of their thresholds is set to be higher than the power supply voltage (VCC-VSS).

Next, the operation of the above-mentioned input circuit will be explained. FIG. 3 is a diagram showing the operating range of MOS transistors M1 and M2 in the first embodiment. As shown in FIG. 3, the MOS transistor M1 is connected to the input terminal IN
ON when the potential is from VSS to VCC- |VTP|
become a state. On the other hand, the MOS transistor M2 is turned on when the potential of the input terminal IN is between VSS+VTN and VCC. Therefore, the potential of the input terminal changes from VCC-|VTP| to V
Even at an intermediate level up to SS+VTN, MOS transistors M1 and M2 are never turned on at the same time. Thereby, a through current can be prevented from flowing between the power supply terminal VCC and the power supply terminal VSS, and malfunction of the semiconductor device can be prevented. Further, when the potential of the input terminal IN is at a High level or a Low level that deviates from the intermediate level, the MOS transistor M1 or M2
is in the ON state, so the internal circuit has a low level or high level.
It is supplied with a high level signal and operates as a normal input circuit.

FIG. 2 is a circuit diagram showing an input circuit according to a second embodiment of the present invention. In this embodiment, the connection relationship of each element is the same as that of the conventional one described above, and the MOS
The threshold values of transistors M4 and M5 are different from the conventional ones. That is, P channel MOS transistor M4
The sum of the absolute values of the threshold values of the N-channel MOS transistor M5 and M5 is set to be higher than the power supply voltage (VCC-VSS).

In the input circuit configured as described above, when the potential of the input terminal IN is at High level or Low level, the internal circuit has a Low level or High level.
When a high level signal is supplied and the control signal input to the control terminal S is low level, the MOS transistor M6 is turned off, so that a through current flows between the power supply terminals VSS and VSS. can be prevented. Furthermore, since the sum of the absolute values of the threshold values of MOS transistors M4 and M5 is set to be higher than the power supply voltage (VCC-VSS), when the semiconductor device requests an input signal and the control signal becomes High level, Even if the potential of the input terminal is at an intermediate level, the MOS transistors M4 and M
5 are never in the ON state at the same time. This results in
A through current can be prevented from flowing between the power supply terminal VCC and the power supply terminal VSS, and malfunction of the semiconductor device can be prevented.

In this embodiment, the threshold values of the MOS transistors M3 and M6 are not particularly limited. Further, the threshold value of a MOS transistor used in a circuit other than an input circuit in a semiconductor device is not particularly limited.

[0017]

As explained above, according to the present invention, the sum of the absolute values of the threshold values of the first and second MOS transistors is greater than or equal to the potential difference between the two sources, so that the input potential of the input terminal is at an intermediate level. Even at the level, the first and second MO
The S transistors are never turned on at the same time. Thereby, it is possible to prevent a through current from flowing, and it is possible to prevent malfunction of the semiconductor device.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the connection relationship of each element of an input circuit according to a first embodiment of the present invention and a conventional example.

FIG. 2 is a circuit diagram showing the connection relationship of each element of an input circuit according to a second embodiment of the present invention and a conventional example.

FIG. 3 is a diagram showing the operating range of a MOS transistor in the first embodiment.

FIG. 4 is a diagram showing the operating range of a MOS transistor in a conventional example.

[Explanation of symbols]

M1, M3 M4; P-channel MOS transistors M2, M5, M6; N-channel MOS transistors VCC, VSS; power supply terminal IN; input terminal S; control terminal

Claims (1)

[Claims] Claim 1: A first device whose gate is commonly connected to an input terminal and whose drain is commonly connected to an input terminal of an internal circuit.
a first MOS transistor of a conductivity type and a second MOS transistor of a second conductivity type;
An input circuit characterized in that the sum of the absolute values of the threshold values of the MOS transistors is greater than or equal to the potential difference between the two sources.