JPH04338655A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH04338655A
JPH04338655A JP3111916A JP11191691A JPH04338655A JP H04338655 A JPH04338655 A JP H04338655A JP 3111916 A JP3111916 A JP 3111916A JP 11191691 A JP11191691 A JP 11191691A JP H04338655 A JPH04338655 A JP H04338655A
Authority
JP
Japan
Prior art keywords
wire
inclined surface
chip
package
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3111916A
Other languages
Japanese (ja)
Inventor
Mitsuharu Takagi
高儀　光治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP3111916A priority Critical patent/JPH04338655A/en
Publication of JPH04338655A publication Critical patent/JPH04338655A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10157—Shape being other than a cuboid at the active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE:To make a package thinner by performing inner-lead bonding having a low loop height. CONSTITUTION:Inclined planes 4 at a tilt angle 45 deg. with respect to a level surface are formed on the four sides on the upper side of a Si chip 3 received into a package 1. A bonding pad 5 is formed on the inclined planes 4 opposite to a lead part 7 of a lead frame of these inclined planes 4, and the bonding pad 5 is connected to the lead part 7 of the lead frame by a wire 6. In this case a root part of the wire 6 is connected perpendicularly to the inclined plane 4.

Description

【発明の詳細な説明】[Detailed description of the invention]

【０００１】0001

【産業上の利用分野】本発明は、例えばＴＳＯＰ（Ｔｈ
ｉｎ　　Ｓｍａｌｌ　　Ｏｕｔｌｉｎｅ　　Ｐａｃｋａ
ｇｅ）等の実装技術を用いた薄型の半導体装置に関する
。[Industrial Application Field] The present invention is applicable to, for example, TSOP (Th
in Small Outline Packa
This invention relates to a thin semiconductor device using mounting technology such as ge).

【０００２】0002

【従来の技術】近年、ノート型のパーソナルコンピュー
タや電子手帳用のメモリーカードのニーズが増えつつあ
ることに対応して、１ｍｍ程度の極めて薄い厚みを有す
るＴＳＯＰが開発されている。かかるパッケージを用い
た半導体装置としては、例えば図５に示すようなものが
知られている。すなわち、この従来例においては、同図
に示すように、樹脂モールドからなるパッケージ２０の
中にダイパッド２１及びＳｉチップ２２が重ねて配置さ
れるとともに、このＳｉチップ２２上に形成されたボン
ディングパッド２３ａにワイヤ２３が接続され、さらに
このワイヤ２３は、パッケージ２０の外側に延びるリー
ドフレームのリード部２４に対してループ状になって接
続されている。2. Description of the Related Art In recent years, in response to the increasing need for memory cards for notebook personal computers and electronic notebooks, TSOPs having an extremely thin thickness of about 1 mm have been developed. As a semiconductor device using such a package, the one shown in FIG. 5, for example, is known. That is, in this conventional example, as shown in the figure, a die pad 21 and a Si chip 22 are arranged in a stacked manner in a package 20 made of a resin mold, and a bonding pad 23a formed on this Si chip 22 is A wire 23 is connected to the package 20 , and the wire 23 is connected in a loop to a lead portion 24 of a lead frame extending outside the package 20 .

【０００３】0003

【発明が解決しようとする課題】ところで、一般に図５
に示すようなＴＳＯＰにおいては、断面方向に関し、ワ
イヤ２３がＳｉチップ２０とリードフレーム２４とに接
触しないようループ高さ及びループ形状が安定している
こと、またワイヤ２３のネック部に対しループ形成後の
ダメージがないことが必要とされる。従って、このよう
な要求を満たすためには、ワイヤ２３のループ高さは一
定の高さが必要であり、その結果、パッケージ２０の薄
型化に限界が生じていた。[Problem to be solved by the invention] By the way, in general, FIG.
In the TSOP shown in FIG. 2, the loop height and loop shape must be stable so that the wire 23 does not come into contact with the Si chip 20 and the lead frame 24 in the cross-sectional direction, and the loop must be formed at the neck portion of the wire 23. It is required that there be no subsequent damage. Therefore, in order to satisfy such requirements, the loop height of the wire 23 needs to be a certain level, and as a result, there is a limit to how thin the package 20 can be made.

【０００４】本発明は、従来例のかかる点に鑑みてなさ
れたもので、その目的とするところは、ループ高の低い
インナーリードボンディングを可能にしてパッケージの
一層の薄型化を達成しうる半導体装置を提供することに
ある。The present invention has been made in view of the above-mentioned problems of the prior art, and its object is to provide a semiconductor device that enables inner lead bonding with a low loop height to achieve further thinning of the package. Our goal is to provide the following.

【０００５】[0005]

【課題を解決するための手段】本発明は、例えば図１に
示すように、Ｓｉチップ３の縁部に傾斜面４を形成し、
この傾斜面４に配線の端子部５を形成するようにしたも
のである。[Means for Solving the Problems] The present invention, as shown in FIG. 1, forms an inclined surface 4 on the edge of a Si chip 3,
The terminal portion 5 of the wiring is formed on this inclined surface 4.

【０００６】[0006]

【作用】かかる構成を有する本発明にあっては、半導体
チップ３の縁部に傾斜面４を形成し、この傾斜面４に配
線の端子部を形成するようにしたので、ワイヤ６の根元
の部分を半導体チップ３外方へ向って傾けることが可能
になり、この結果、ワイヤ６のネック部に対してダメー
ジを与えることなく、またループ形状を不安定にするこ
となく、ループの高さを低くすることができる。[Operation] In the present invention having such a configuration, the inclined surface 4 is formed on the edge of the semiconductor chip 3, and the terminal portion of the wiring is formed on this inclined surface 4, so that the root of the wire 6 is formed. It is now possible to tilt the portion of the wire toward the outside of the semiconductor chip 3, and as a result, the height of the loop can be increased without damaging the neck portion of the wire 6 or destabilizing the loop shape. It can be lowered.

【０００７】[0007]

【実施例】以下、本発明に係る半導体装置の実施例につ
いて図面を参照して説明する。図１は、本発明の一実施
例であるＴＳＯＰを用いた半導体装置の要部概略構成を
示す断面説明図である。同図に示すように、樹脂モール
ドからなるパッケージ１内には、ダイパッド２上に半導
体チップであるＳｉチップ３が形成されている。そして
、本実施例においては、後述の方法によりＳｉチップ３
の上側の四辺に傾斜面４が形成されるとともに、この傾
斜面４にＡｌによるボンディングパッド５が形成され、
さらに、このボンディングパッド５にワイヤ６の一端が
接続されている。この場合、傾斜面４は、水平方向に対
して４５°の傾斜角を有しており、ワイヤ６の根元の部
分は傾斜面４に対して垂直に接続されている。そして、
ワイヤ６の他端は、パッケージ１の外側に延びるリード
フレームのリード部７に接続され、これによりワイヤ６
のループが形成されている。Embodiments Hereinafter, embodiments of a semiconductor device according to the present invention will be described with reference to the drawings. FIG. 1 is an explanatory cross-sectional view showing a schematic configuration of main parts of a semiconductor device using a TSOP, which is an embodiment of the present invention. As shown in the figure, a Si chip 3, which is a semiconductor chip, is formed on a die pad 2 in a package 1 made of a resin mold. In this embodiment, the Si chip 3 is
A sloped surface 4 is formed on the upper four sides of the board, and a bonding pad 5 made of Al is formed on this sloped surface 4.
Furthermore, one end of a wire 6 is connected to this bonding pad 5. In this case, the inclined surface 4 has an inclination angle of 45° with respect to the horizontal direction, and the root portion of the wire 6 is connected perpendicularly to the inclined surface 4. and,
The other end of the wire 6 is connected to a lead portion 7 of a lead frame extending outside the package 1, so that the wire 6
A loop is formed.

【０００８】次に、Ｓｉチップ３に傾斜面４及びボンデ
ィングパッド５を形成する方法について説明する。まず
、図２（ａ）に示すように、厚み６００μｍのＳｉウェ
ハー８にファースト酸化膜（ＳｉＯ２　）９を形成し、
幅１００μｍのスクライブライン１０以外の領域をレジ
スト１１で覆う。そして、アルカリの特定溶液を用い等
方性エッチングであるテーパエッチングにより、スクラ
イブライン１０に沿う部分、即ち領域Ａをエッチングし
、上述の傾斜面４を形成する。この場合、エッチングの
深さは１００μｍとする。一方、爾後形成されるＳｉチ
ップ３の傾斜面４の傾斜角は４５°であるから、スクラ
イブライン１０の両側のエッチング量は、１００μｍ程
必要になる。そして、その結果、傾斜面４の幅は１４１
μｍとなるので、１００μｍ平方のボンディングパッド
５を形成するには十分なスペースを確保することができ
る。尚、スクライブライン１０は図３に示す如く５００
０μｍ平方のＳｉチップ３が得られるようにＳｉウェハ
ー８表面において格子状に形成されている。Next, a method for forming the inclined surface 4 and the bonding pads 5 on the Si chip 3 will be explained. First, as shown in FIG. 2(a), a first oxide film (SiO2) 9 is formed on a Si wafer 8 with a thickness of 600 μm.
The area other than the scribe line 10 having a width of 100 μm is covered with a resist 11. Then, the portion along the scribe line 10, that is, the region A, is etched by taper etching, which is isotropic etching, using a specific alkali solution, thereby forming the above-mentioned inclined surface 4. In this case, the etching depth is 100 μm. On the other hand, since the inclination angle of the inclined surface 4 of the Si chip 3 to be formed later is 45°, the etching amount on both sides of the scribe line 10 is required to be about 100 μm. As a result, the width of the inclined surface 4 is 141
.mu.m, it is possible to secure a sufficient space to form the bonding pad 5 of 100 .mu.m square. Incidentally, the scribe line 10 is 500 as shown in FIG.
They are formed in a lattice shape on the surface of the Si wafer 8 so as to obtain Si chips 3 of 0 μm square.

【０００９】次に、図２（ｂ）に示すように、傾斜面４
の下部にウェル１２を形成する。この場合、ボンディン
グ時のショートを防止するため、Ｓｉウェハー８のＮ形
と逆導電形のＰ形ウェル１２を形成する。Next, as shown in FIG. 2(b), the inclined surface 4
A well 12 is formed at the bottom of the well. In this case, in order to prevent short circuits during bonding, a P-type well 12 having a conductivity type opposite to that of the N-type of the Si wafer 8 is formed.

【００１０】その後、図２（ｃ）に示すように、ＬＯＣ
ＯＳ（ｌｏｃａｌｉｚｅｄ　　ｏｘｉｄａｔｉｏｎ　　
ｏｆ　　ｓｉｌｉｃｏｎ）層１３を形成し、ＬＯＣＯＳ
層１３で分離された各電子形成領域に所要の半導体素子
を形成した後、その電極及び配線と共に、Ｓｉウェハー
８の各傾斜面にＡｌによるボンディングパッド５を形成
する。 そしてスクライブライン１０に沿って切断して図１に示
すＳｉチップ３を作製する。After that, as shown in FIG. 2(c), the LOC
OS (localized oxidation)
of silicon) layer 13 and LOCOS
After the required semiconductor elements are formed in each electron formation region separated by the layer 13, bonding pads 5 made of Al are formed on each inclined surface of the Si wafer 8 along with the electrodes and wiring thereof. Then, the Si chip 3 shown in FIG. 1 is manufactured by cutting along the scribe line 10.

【００１１】図４は、Ｓｉチップ３の傾斜面４近傍を拡
大したものである。同図に示すように、各傾斜面４には
、上述のＬＯＣＯＳ層１２上に１００μｍ平方のボンデ
ィングパッド５が形成され、このＬＯＣＯＳ層１２を挟
んでボンディングパッド５の下部にはＰ形ウェル１２が
形成されている。また、ボンディングパッド５の周囲に
はオーバーコート膜１４が形成されている。FIG. 4 is an enlarged view of the vicinity of the inclined surface 4 of the Si chip 3. As shown in the figure, on each inclined surface 4, a 100 μm square bonding pad 5 is formed on the above-mentioned LOCOS layer 12, and a P-type well 12 is formed under the bonding pad 5 with the LOCOS layer 12 in between. It is formed. Further, an overcoat film 14 is formed around the bonding pad 5 .

【００１２】ボンディングバッド５に金線であるワイヤ
６を接続するには、ボンディングパッド５に対して垂直
になるようワイヤ６を水平方向に対して４５°傾けてボ
ンディングを行う。In order to connect the wire 6, which is a gold wire, to the bonding pad 5, bonding is performed by tilting the wire 6 at 45 degrees with respect to the horizontal direction so that it is perpendicular to the bonding pad 5.

【００１３】以上の構成を有する本実施例によれば、ワ
イヤ６の根元の部分がリードフレームのリード部７に向
って４５°傾いた状態で接続されているため、ワイヤ６
のネック部に対してダメージを与えることなく、またル
ープ形状を不安定にすることなく、ループの高さを低く
することができる。従って、ＴＳＯＰにおいてループ高
の低いインナーリードボンディングを行うことができる
ので、パッケージ１を非常に薄く構成することが可能に
なる。According to this embodiment having the above-described configuration, since the root portion of the wire 6 is connected to the lead portion 7 of the lead frame at an angle of 45°, the wire 6
The height of the loop can be lowered without damaging the neck portion of the loop or making the loop shape unstable. Therefore, since inner lead bonding with a low loop height can be performed in the TSOP, it is possible to construct the package 1 very thinly.

【００１４】尚、本実施例においては、傾斜面の角度を
水平方向に対して４５°傾けるようにしたが、本発明は
これに限られることはなく、パッケージの種類に応じて
傾斜角の値を変えてもよい。[0014] In this embodiment, the angle of the inclined surface is inclined at 45 degrees with respect to the horizontal direction, but the present invention is not limited to this, and the value of the angle of inclination can be adjusted depending on the type of package. may be changed.

【００１５】また、本実施例においては、Ｓｉチップの
四辺に傾斜面を形成するようにしたが、本発明はこれに
限られることはなく、例えばリードフレームのリード部
に対向する二辺にのみ傾斜面を形成するようにしてもよ
い。Further, in this embodiment, the Si chip is formed with inclined surfaces on the four sides, but the present invention is not limited to this. An inclined surface may be formed.

【００１６】[0016]

【発明の効果】以上述べたように本発明にあっては、半
導体チップの縁部に傾斜面を形成し、この傾斜面に配線
の端子部を形成するようにしたので、ループ高の低いイ
ンナーリードボンディングが可能になり、この結果、パ
ッケージを一層薄型にすることができる。As described above, in the present invention, an inclined surface is formed on the edge of a semiconductor chip, and the terminal portion of the wiring is formed on this inclined surface, so that an inner wire with a low loop height can be used. Lead bonding is now possible, resulting in a thinner package.

【図面の簡単な説明】[Brief explanation of drawings]

【図１】本発明の実施例の要部概略構成を示す断面説明
図である。FIG. 1 is an explanatory cross-sectional view showing a schematic configuration of main parts of an embodiment of the present invention.

【図２】同実施例における傾斜面及びボンディングパッ
ドの形成方法を示す説明図である。FIG. 2 is an explanatory diagram showing a method for forming an inclined surface and a bonding pad in the same embodiment.

【図３】同実施例のＳｉチップの概略寸法を示す説明図
である。FIG. 3 is an explanatory diagram showing the approximate dimensions of the Si chip of the same example.

【図４】同実施例の傾斜面近傍を示す拡大図である。FIG. 4 is an enlarged view showing the vicinity of the inclined surface of the same embodiment.

【図５】従来例の要部概略構成を示す断面説明図である
。FIG. 5 is an explanatory cross-sectional view showing a schematic configuration of main parts of a conventional example.

【符号の説明】[Explanation of symbols]

１　　パッケージ ３　　Ｓｉチップ ４　　傾斜面 ５　　ボンディングパッド ６　　ワイヤ ７　　リードフレームのリード部 1 Package 3 Si chip 4 Slope surface 5 Bonding pad 6 Wire 7 Lead part of lead frame

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】　　半導体チップの縁部に、傾斜面を形成
し、該傾斜面に配線の端子部を形成するようにした半導
体装置。1. A semiconductor device in which a sloped surface is formed at the edge of a semiconductor chip, and a terminal portion of wiring is formed on the sloped surface.
JP3111916A 1991-05-16 1991-05-16 Semiconductor device Pending JPH04338655A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3111916A JPH04338655A (en) 1991-05-16 1991-05-16 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3111916A JPH04338655A (en) 1991-05-16 1991-05-16 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH04338655A true JPH04338655A (en) 1992-11-25

Family

ID=14573332

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3111916A Pending JPH04338655A (en) 1991-05-16 1991-05-16 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH04338655A (en)

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