JPH0433146U

JPH0433146U -

Info

Publication number: JPH0433146U
Application number: JP7356690U
Authority: JP
Priority date: 1990-07-11
Filing date: 1990-07-11
Publication date: 1992-03-18

Description

[Brief explanation of the drawing]

第１図はこの考案の一実施例によるＦＩＦＯ装
置を示す構成図、第２図はこの考案の一実施例に
よる書き込み信号のタイミングを示す説明図、第
３図はこの考案の一実施例による読み出し信号の
タイミングを示す説明図、第４図はこの考案に係
る一実施例のＦＩＦＯ素子を示す説明図、第５図
は従来のＦＩＦＯメモリ装置を示す構成図、第６
図は従来のＦＩＦＯメモリ装置の一例を示す説明
図である。図において、１は複数のデジタル信号入力、２
はＦＩＦＯ素子、３はデータ書き込み信号、４は
第１の３パルス発生回路、５は第１の３入力ＯＲ
回路、６は新たな書き込み信号、７はデータ読み
出し信号、８は第２の３パルス発生回路、９は第
１の読み出し信号、１０は第２の読み出し信号、
１１は第３の読み出し信号、１２は第２の３入力
ＯＲ回路、１３は新たな読み出し信号、１４は複
数のＦＩＦＯ読み出しデータ信号、１５は第１の
レジスタ、１６は第２のレジスタ、１７は３入力
多数決回路、１８は複数の多数決データ信号であ
る。なお、図中、同一符号は同一、または相当部
分を示す。 FIG. 1 is a configuration diagram showing a FIFO device according to an embodiment of this invention, FIG. 2 is an explanatory diagram showing the timing of a write signal according to an embodiment of this invention, and FIG. 3 is a diagram showing a read signal according to an embodiment of this invention. FIG. 4 is an explanatory diagram showing the timing of signals, FIG. 4 is an explanatory diagram showing a FIFO element according to an embodiment of this invention, FIG. 5 is a configuration diagram showing a conventional FIFO memory device, and FIG.
The figure is an explanatory diagram showing an example of a conventional FIFO memory device. In the figure, 1 indicates multiple digital signal inputs, 2
is a FIFO element, 3 is a data write signal, 4 is a first 3-pulse generation circuit, and 5 is a first 3-input OR
circuit, 6 is a new write signal, 7 is a data read signal, 8 is a second 3-pulse generation circuit, 9 is a first read signal, 10 is a second read signal,
11 is a third read signal, 12 is a second 3-input OR circuit, 13 is a new read signal, 14 is a plurality of FIFO read data signals, 15 is a first register, 16 is a second register, 17 is a A three-input majority decision circuit, 18 is a plurality of majority decision data signals. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims

[Scope of utility model registration request]

FIFO (Fi
rst-In First-Out) element, a first three-pulse generation circuit that inputs a data write signal and generates three time-shifted pulses, and three outputs of the first three-pulse generation circuit, respectively. a first 3-input OR circuit that inputs the signal and outputs it to the FIFO element; a second 3-pulse generating circuit that receives the data read signal and generates three time-shifted pulses; and the second 3-pulse a second 3-input OR circuit that inputs the three outputs of the generation circuit and outputs them to the FIFO element;
a first register that inputs a plurality of output data signals of the element and latches the data at the timing of one output of the second three-pulse generating circuit; and the FIF
A plurality of output data signals of the O element are input and the second
a second register that latches data at another output timing of the three pulse generating circuits;
A FIFO comprising: a 3-input majority circuit that inputs a plurality of output data signals of the IFO element, an output data signal of the first register, and an output data signal of the second register, and takes majority logic for each bit. memory device.