JPH0433146U - - Google Patents
Info
- Publication number
- JPH0433146U JPH0433146U JP7356690U JP7356690U JPH0433146U JP H0433146 U JPH0433146 U JP H0433146U JP 7356690 U JP7356690 U JP 7356690U JP 7356690 U JP7356690 U JP 7356690U JP H0433146 U JPH0433146 U JP H0433146U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- inputs
- fifo
- register
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 7
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Description
第1図はこの考案の一実施例によるFIFO装
置を示す構成図、第2図はこの考案の一実施例に
よる書き込み信号のタイミングを示す説明図、第
3図はこの考案の一実施例による読み出し信号の
タイミングを示す説明図、第4図はこの考案に係
る一実施例のFIFO素子を示す説明図、第5図
は従来のFIFOメモリ装置を示す構成図、第6
図は従来のFIFOメモリ装置の一例を示す説明
図である。
図において、1は複数のデジタル信号入力、2
はFIFO素子、3はデータ書き込み信号、4は
第1の3パルス発生回路、5は第1の3入力OR
回路、6は新たな書き込み信号、7はデータ読み
出し信号、8は第2の3パルス発生回路、9は第
1の読み出し信号、10は第2の読み出し信号、
11は第3の読み出し信号、12は第2の3入力
OR回路、13は新たな読み出し信号、14は複
数のFIFO読み出しデータ信号、15は第1の
レジスタ、16は第2のレジスタ、17は3入力
多数決回路、18は複数の多数決データ信号であ
る。なお、図中、同一符号は同一、または相当部
分を示す。
FIG. 1 is a configuration diagram showing a FIFO device according to an embodiment of this invention, FIG. 2 is an explanatory diagram showing the timing of a write signal according to an embodiment of this invention, and FIG. 3 is a diagram showing a read signal according to an embodiment of this invention. FIG. 4 is an explanatory diagram showing the timing of signals, FIG. 4 is an explanatory diagram showing a FIFO element according to an embodiment of this invention, FIG. 5 is a configuration diagram showing a conventional FIFO memory device, and FIG.
The figure is an explanatory diagram showing an example of a conventional FIFO memory device. In the figure, 1 indicates multiple digital signal inputs, 2
is a FIFO element, 3 is a data write signal, 4 is a first 3-pulse generation circuit, and 5 is a first 3-input OR
circuit, 6 is a new write signal, 7 is a data read signal, 8 is a second 3-pulse generation circuit, 9 is a first read signal, 10 is a second read signal,
11 is a third read signal, 12 is a second 3-input OR circuit, 13 is a new read signal, 14 is a plurality of FIFO read data signals, 15 is a first register, 16 is a second register, 17 is a A three-input majority decision circuit, 18 is a plurality of majority decision data signals. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
rst−In First−Out)素子と、デ
ータ書き込み信号を入力し時間的にずれた3つの
パルスを発生する第1の3パルス発生回路と、上
記第1の3パルス発生回路の3つの出力をそれぞ
れ入力し上記FIFO素子に出力する第1の3入
力OR回路と、データ読み出し信号を入力し、時
間的にずれた3つのパルスを発生する第2の3パ
ルス発生回路と、上記第2の3パルス発生回路の
3つの出力をそれぞれ入力し上記FIFO素子に
出力する第2の3入力OR回路と、上記FIFO
素子の複数の出力データ信号を入力し上記第2の
3パルス発生回路の1つの出力のタイミングでデ
ータをラツチする第1のレジスタと、上記FIF
O素子の複数の出力データ信号を入力し上記第2
の3パルス発生回路の別の1つの出力タイミング
でデータをラツチする第2のレジスタと、上記F
IFO素子の複数の出力データ信号と上記第1の
レジスタの出力データ信号および上記第2のレジ
スタの出力データ信号を入力し、それぞれビツト
毎に多数決論理をとる3入力多数決回路と、を備
えたFIFOメモリ装置。 FIFO (Fi
rst-In First-Out) element, a first three-pulse generation circuit that inputs a data write signal and generates three time-shifted pulses, and three outputs of the first three-pulse generation circuit, respectively. a first 3-input OR circuit that inputs the signal and outputs it to the FIFO element; a second 3-pulse generating circuit that receives the data read signal and generates three time-shifted pulses; and the second 3-pulse a second 3-input OR circuit that inputs the three outputs of the generation circuit and outputs them to the FIFO element;
a first register that inputs a plurality of output data signals of the element and latches the data at the timing of one output of the second three-pulse generating circuit; and the FIF
A plurality of output data signals of the O element are input and the second
a second register that latches data at another output timing of the three pulse generating circuits;
A FIFO comprising: a 3-input majority circuit that inputs a plurality of output data signals of the IFO element, an output data signal of the first register, and an output data signal of the second register, and takes majority logic for each bit. memory device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7356690U JPH0433146U (en) | 1990-07-11 | 1990-07-11 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7356690U JPH0433146U (en) | 1990-07-11 | 1990-07-11 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0433146U true JPH0433146U (en) | 1992-03-18 |
Family
ID=31612492
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7356690U Pending JPH0433146U (en) | 1990-07-11 | 1990-07-11 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0433146U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014186704A (en) * | 2013-03-25 | 2014-10-02 | Fujitsu Ltd | Data storage device and data storage method |
-
1990
- 1990-07-11 JP JP7356690U patent/JPH0433146U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014186704A (en) * | 2013-03-25 | 2014-10-02 | Fujitsu Ltd | Data storage device and data storage method |
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