JPS62133553A - Digital signal processing circuit - Google Patents

Abstract

PURPOSE:To improve the highest operating speed by completing the transfer of a data between each signal processing unit in a periodic term. CONSTITUTION:One piece of common line 40 is increased in parallel to a data bus 100. Also, the number of bits of each 3-state buffer 21-2n is set so as to be 1 bit more than the number of bits of the data bus 100, the input of the 3-state buffer of this 1 bit is pulled up to logic '1', and its output is connected to a common line 40 in the vicinity of a connecting point to the data bus 100 lines of the respective 3-state buffer outputs. Also, from the common line 40 in the vicinity of the connecting point of the data input of each signal processing unit 11-1n and the data bus 100, strobe signals 201-20n are applied to each signal processing unit 11-1n, respectively, through delaying circuits 31-3n, respectively.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a digital signal processing circuit that performs data transfer and signal processing between signal processing units using all bus lines such as data buses [5]. In particular, the present invention relates to a digital signal processing circuit that can operate at high speed.

[Conventional technology]

Conventionally, digital signal processing circuits with bus lines are
The configuration is as shown in FIG.

Hereinafter, the configuration and operation of the conventional example will be explained according to the timing charts of FIGS. 4 and 5. In the conventional example shown in FIG. 4, data from the data bus 100 is input and [,
N signal processing units 11 that perform various signal processing.
12. ..., 1n, and the output data of each (i processing unit 11, 12...+1') is transferred to the data bus 1.
N 3-state buffers outputting to 00 21.22.
..., Qn, and N signal processing units 11,
12. ....

In and 3-state buffers 51, 52 . ....

A control circuit 7 that provides a control signal to the signal processing unit 1.5n, and a control circuit 7 and a signal processing unit 1.
2. ..., 3 and the basic clock 104.

It is configured to include a clock generation circuit 8 that supplies a strobe signal 200 that is a source of strobe of input data from a data bus. In addition, the signal processing units 11.12.
..., 1n does not have either h of output to td, f-tabus, or input from data bus, but this is not directly related to the detailed explanation of the conventional example and the present invention. , here signal processing units 11.12.・
. . . has 1n inputs and outputs. In addition, there are cases where the signals between each signal processing unit do not go through a data bus, and there are cases where a multi-phase clock is supplied to the clock from the clock generator 8, but Konera uses the same reason. This is abbreviated as I in the drawings.

Here each signal processing unit 11.1.2. ..., 1
Various circuits can be used depending on the purpose of the processing, for example, an adder circuit 14 as shown in FIG. 14 adder circuits in Figure 2, data path cod =
AND circuit 17.1 for each input data from Kanoomi
The output of these latches 15, 16 is input to the latches 15 and 16 which catch the rising edge of the output of 8, and the adder 19 which performs addition, and the output of this adder 19 is the basic clock. It consists of a latch 20 that captures and provides output data.

Now, in the conventional example shown in FIG. 4, the adder circuit 14 shown in FIG. As an example, consider the case where L7 is transferred to the signal processing unit 11 of 1 through the data bus #1, added to 1, and output again to the data bus.

FIG. 5(a) is a timing chart showing the station and sample at this time. First, the signal 10 from the control circuit 7 is
2 becomes q"1", the second 3-state buffer 22 opens, the output of the second signal processing unit 12 is transferred to the data bus Joov, and the output of the first signal processing unit 11 is transferred after a delay time td2. Power IN appears as a valid data person. Since the signal 301 from the control circuit 7 and the strobe signal 200 become 11# simultaneously, the AND
Circuit 17 provides a latch pulse to latch 15, and at this point latch 15 takes in input data A. Next, in the same manner, the output of the N-th signal processing unit In is passed through the entire N-th three-stage buffer 2n to the data bus 10 by the signal 103.
After a delay time tdN, valid data B appears at the input IN of the first signal processing unit 110, which is ANDed by the signal 301 and the strobe signal 200.
Circuit 18 provides a latch pulse, data B is sent to latch 16
It cannot be taken into account. As a result, the adder 19 executes the operation A+B, and the signal is output to the output OUT of the first signal processing unit 11 at the next falling edge of the basic clock CK. In this state, since the signal 101 is not applied from the control circuit 7, the output data of the operation result A+B is output onto the data bus. As described above, conventional circuits are widely used because they perform the desired operations and are structurally very suitable for integration into integrated circuits. Indeed, the loading of data bus lines on integrated circuits is heavy and non-uniform, and data transfer via data buses between signal processing units that are geographically far apart typically results in The delay time becomes very large and often determines the upper limit of the frequency V of the basic clock 104. Assuming that the first and second signal processing units 11 and In are placed geometrically farthest apart, tdN in FIG. 5(a) is the maximum delay time of data on the data bus 100. Become.

The strobe signal 200, which is the source of the latch pulse of input data in each unit 31!1', is supplied from the clock generation circuit 8, but generally,
The basic clock 104 is an oscillator (
The strobe signal 200 is also generated by dividing the oscillator output into 1/2 and 1/4 (not shown).
Since the strobe signal 200 is generated, the position on the etch timing that can be selected is the basic clock 104.
1/4 increments of period To & 1 degree of freedom it is not allowed. Also, after opening the 3-state buffer that receives the output of the signal processing unit on the data sending side, the data on the data node 100 is the most stable, and during the interval when the 3-state buffer is open, , strobe signal 20
Since the timing position of the edge of 0 is taken, for example, a timing such as the strobe signal 200 in FIG. 5(a) is selected. As the timing for opening each 3-state buffer, for example, the signal 102 in FIG.
In order to prevent the output data from colliding with each other on the data bus 100, as in the relationship between For the same reason as in the case, the degree of freedom is selected to be 1/4 of the synchronization To with 8 degrees of freedom.

In the conventional circuit where the timing is fixed in this way, the frequency of the basic clock is reduced to 1 / as shown in Figure 5(b).
Consider the case of increasing from T o to 1/T I.

However, as described above, the position of the strobe signal 200 with respect to the basic clock 104 is fixed at 1/2 of the period T1, and the delay time t of data on the data bus 100
Since dN is also constant regardless of the frequency of the basic clock 0ψ, in this case +'dN>TI/2, and the first signal processing unit:y)11 is the data transferred from the Nth signal processing unit 1n. Correct B, < cannot be taken in, causing malfunction.

When there are many signal processing units, the wiring length of the data bus connecting them becomes long, and the output terminals of all signal processing units themselves become a load, so the load on the data bus does not go through other data buses. The load is heavy compared to the load on the signal line.

However, since there is a limit to the ability of the signal line to drive square loads, in general, in a digital signal processing unit that transfers data via a data bus, the signal delay on the data bus is This is larger than the delay of other signal lines, and in the case of this conventional circuit, the maximum operating frequency fM
AX is governed by the maximum delay time tdN of data on the data bus 100, and in this case, when converted to the basic clock 104, 1MAX=□ (1) t
dN.

[Problem that the invention seeks to solve]

In this way, in the conventional circuit, the maximum operating frequency is (1)
Although limited as shown in the equation, an object of the present invention is to further improve this maximum operating frequency to increase the processing speed of the entire circuit.

The reason why the operating speed is limited in the conventional example is that the timing position of the throat strobe signal STB with respect to the basic clock 104 is fixed regardless of the magnitude of the delay of data on the data bus 100. . Considering this point, the basic point of the circuit of the present invention is that by generating the strobe signal 200 after a certain period of time from the data change point on the data bus 100, the data can be captured reliably and effectively. The purpose is to improve operating speed.

[Means for solving problems]

The digital signal processing circuit of the present invention has a
In a digital signal processing circuit that transfers data using a common line arranged in parallel with a bus line, each signal processing unit synchronizes the timing of outputting data to the bus line.

A means for outputting a pulse to this common line, and an input to the common line near each signal processing unit are connected to w, and an output is connected to the strobe signal input of the input data from the bus line in the signal processing unit, respectively. , and a delay circuit.

〔Example〕

FIG. 1 shows an embodiment of the present invention, which basically connects the input to the data bus 1o13G;
N signal processing units) 11, 12°..., 1n, and N 3 units that output their outputs to oo on the data bus.
It consists of steady buffers 21, 22°...+2n, a control circuit 7 for controlling stiffness, and a clock generation circuit 8, and is further arranged geometrically parallel to the data bus 100.

They are also wired using the same wiring material and have a common line 12 pulled down to logic '0#' by a resistor 13.

In addition, each 3-state buffer 21.22. ....

The number of bits of 2n is set to 1 bit more than the 1000-bit number of the data bus.The input of this 1-bit 3-state buffer is pulled up to the logic 'f9'1', and its output is It is connected to the common line 40 near the connection point of the 3-state buffer output with the data bus 100 line.

Furthermore, each signal processing unit 11.12. ..., 1
Delay circuits 31, 32, .・
. . , 3n, each signal processing unit 11.12.
..., In, the strobe signals 201, 202
．． ...20n is given.

Fig. 3 Fi The book in Fig.
A timing chart in the case of performing the same operation as in the conventional example b) is shown. The operation of the embodiment of the present invention will be explained with reference to FIG.

First, the signal 102 becomes %1#, and the output of the second signal processing unit 12 is output onto the data bus 100 and appears at the input IN of the first signal processing unit 11 as input data after a delay time td2. At this time, among the second three-state buffers 22,
A 1-bit 3-state buffer whose input is pulled up to v11# outputs 11#. Note that before this, the common line 40 is set to %0# due to the resistor 13. The load on the data bus 100 lines from the output of the second 3-state buffer 22 to the input of the first signal processing unit 11 and the load on the second 3-state buffer 22
The load on the common line 40 from the output of the L to the input of the first delay circuit 31 is geometrically similar to L, and since they are wired with the same material, they are approximately equal, so the resistor 13
Due to this connection, the load on the common line 40 becomes slightly heavier. Therefore, when 'l' is output to the common line 40, after a delay time tdx that is approximately the same as the data delay on the data bus 100, if 7
A rising etch appears at the input of the delay circuit 31, and the first
Further, after a delay time of jt, a rising etch is applied as the strobe signal 201 of the first signal processing unit 11 via the delay circuit 31 . The rising edge of this strobe signal 201 and the signal 3o1 from the control circuit 7 (see also FIG. 2 below) cause the AND circuit 17 to
generates a latch pulse, and latch 15 takes in input data A. Next, in the same way, the Nth third
State buffer 2n opens and Nth signal processing circuit 1n
The output B appears at the input of the first signal processing circuit 11, and the rising edge of 1# of the common line appears at the input of the first delay circuit 31 after approximately the same delay time tdN. common line 4
The rising edge of o is further applied to the first signal processing circuit 11 as a signal 201 of 0-7" after a delay time of jt via the first delay circuit 31. The AND circuit 18 gives a latch pulse in response to the signal 302 and takes in the input data B of the latch 16H.As a result, the adder 19 executes the addition A+13 of the two input data A and B, and the signal 101 is sent to the control circuit 7. , the desired output of the first signal processing unit 11 is output to the data bus 100.

In addition to the conventional structure, the present invention includes one common line 4o in parallel with the data bus 100, and three-state buffers 21, 22 . It is necessary to add one bit to the number of +2" bits, but the area occupied on the chip when integrated circuits is insignificant compared to the total circuit,
The industrial benefits of the nearly two-fold improvement in maximum operating speed obtained by adding kneads are far greater.

〔Effect of the invention〕

As is clear from the operation of the embodiment of the present invention described above, completing the data transfer of each signal processing unit Hi within a period of period + 111 is a prerequisite for operation, so to speak, the upper limit of the operation speed of the present invention. is from the falling edge of the basic clock lo,
Each strobe signal 2o1゜202,...&20n
Among them, the delay time until the rising edge of the signal that is the slowest is given at the limit point exceeding the period T1, and the maximum operating frequency at this time is converted to the basic clock 1040 frequency, as shown in the timing chart of Fig. 3. It is obtained as in equation (2).

Here, the delay circuits 31, 32 . Since it is easily possible to select all the weekly extension times Δ of 3n, when compared with the conventional maximum operating frequency formula (1), it becomes t4H+dt, and the degree of improvement is as follows, which is nearly twice as high. It has the effect of being able to improve.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
Block diagram illustrating an example of the signal processing unit in the figure, No. 3
The figure is a timing chart showing the operation of Figure 1, Figure 4 is a block diagram of the conventional example, and Figures 5 (a) and (b) are the first
5 is a timing chart showing the operation shown in the figure. 11.12. In... Signal processing unit, 21
゜22.2n...3 state buffer, 7...
...Control circuit, 8...Clock generation circuit, 31゜32.30...Delay circuit, 40
...Common line, 13...Resistance, 14
...Addition circuit, 15, 16°20...
Latch, 17.18...AND circuit, 19...
... Adder, 100 ... Data bus, 1o
4...Basic clock.

Claims (1)

[Claims] A digital signal processing circuit that performs signal processing by transferring data between a plurality of signal processing units each having a signal processing function via a bus line, the circuit having a common line arranged in parallel with the bus line; means for outputting a pulse from each of the plurality of signal processing units to the common line in synchronization with the timing at which each of the signal processing units outputs data to the bus line; A digital signal processing circuit comprising a plurality of delay circuits each having an input connected to a nearby common line and an output connected to a strobe signal input of input data from a bus line in the plurality of signal processing units. .