JPH0270121A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To suppress power current fluctuation and to prevent malfunction by synchronizing the output buffer enable signals of plural three-state output buffers with a clock signal and providing an output control circuit having delay elements with respectively different delay quantity. CONSTITUTION:In a semiconductor integrated circuit, plural three-state output buffers 4-1 to 4-M transmitting plural output signals in synchronizing with the clocks of a logic circuit 3, the delay elements 6-1 to 6-M which synchronize the enables signals of the output buffers 4-1 to 4-M with the clock signals, delays the signals by respectively different delay quantity, input buffers 2-0 to 2-M, an inverter 7 and an AND circuit 8 are provided. Inputted signals pass through the input buffers 2, are signal-processed in the logic circuit 3 and are inputted to the three-state output buffers 4. At that time, the enable signals of the three-state output buffers are sequentially delayed and outputted through the AND circuit 8 and the delay elements 6 with signals inverted in the inverter 7, and fluctuation of a power current is dispersed, whereby malfunction is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to an output control circuit.

[Conventional technology]

FIG. 3 shows an example of a conventional circuit configuration. The signal of logic circuit 3 is passed through 3-state output buffers 4-1 to 4-M to output pins 5-1 to 5. Output to M. ■-1~l-11t
is an input pin.

[Problem to be solved by the invention]

In the conventional semiconductor integrated circuit described above, as shown in FIG. 4, the output signals from the logic circuits each connected to a plurality of three-state output buffers become 10' or ``1'' at the same timing synchronized with the clock. When the current changes, the 3-state output buffer also changes at the same time.For this reason, the sum Σi of the currents flowing through the 3-state output buffer becomes a large current, and when it flows through the semiconductor integrated circuit, it causes a fluctuation in the power supply voltage due to the internal resistance. , which has the disadvantage of causing circuit malfunction.

An object of the present invention is to provide a semiconductor integrated circuit that solves the above problems.

[Means to solve the problem]

To achieve the above object, the present invention provides a semiconductor integrated circuit including a plurality of three-state output buffers that output a plurality of output signals synchronized with the clock of a logic circuit, in which an output buffer enable signal of the plurality of three-state output buffers is provided. It has an output control circuit equipped with a delay element that applies the signals after different delay amounts in synchronization with a clock signal.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

In the figure, the semiconductor integrated circuit of the present invention includes a plurality of three output signals synchronized with the clock of a logic circuit three.
Delay elements 6-1 to 6-1 which synchronize the enable signals of the state output buffers 4-1 to 4-M and the three-state output buffers 4-1 to 4-H with a clock signal and apply the enable signals after delaying them by different delay amounts. 6 gates and 2 input buffers
-0 to 2-M and the inverter 7.

AND circuit 8.

In the embodiment, signals inputted from input pins 1-1 to 1-N pass through input buffers 2-1 to 2-N to logic circuit 3.
The result of signal processing is input to the input of the 3-state output buffer. At this time, the enable signal of the 3-state output buffer is successively passed through the AND circuit 8 with the inverted signal inverted by the inverter 7 of the clock signal input from the input pin 1-0, and the delay lines 6-1 to G-M. It is input to 3-state output buffers 4-1 to 4-M. In other words, as shown in Fig. 2, the output of the 3-state output cover sofa takes a time from the rising edge of the clock signal input from the clock input pins 1-0 as shown in the following formula: TPdm '' m X Δt Δt: Delay time of delay element TPdm: Delay time at output pin 5-M However, since output is delayed by 1≦m≦8, multiple output buffers 4-1
~4-M does not change at the same timing.

〔Effect of the invention〕

As explained above, the semiconductor integrated circuit according to the present invention can prevent a plurality of outputs of the semiconductor integrated circuit from changing at the same timing, and since fluctuations in the power supply current are dispersed, fluctuations in the power supply voltage are suppressed. Malfunctions are prevented.

Particularly remarkable effects can be obtained in large-scale integrated circuits having a large number of outputs.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
3 is a circuit diagram showing a conventional example, and FIG. 4 is a time chart of FIG. 3. 1-0~l-N...Input pin 2-0~2-N...
・Input buffer 3...Logic circuit

Claims (1)

[Claims] (1) In a semiconductor integrated circuit including a plurality of 3-state output buffers that send out a plurality of output signals synchronized with the clock of a logic circuit, output buffer enable signals of the plurality of 3-state output buffers are synchronized with the clock signal. 1. A semiconductor integrated circuit comprising an output control circuit including delay elements that delay and apply voltage by different delay amounts.