JPH01108625U - - Google Patents
Info
- Publication number
- JPH01108625U JPH01108625U JP331788U JP331788U JPH01108625U JP H01108625 U JPH01108625 U JP H01108625U JP 331788 U JP331788 U JP 331788U JP 331788 U JP331788 U JP 331788U JP H01108625 U JPH01108625 U JP H01108625U
- Authority
- JP
- Japan
- Prior art keywords
- register
- logic gate
- detection circuit
- detects
- gate circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 238000003708 edge detection Methods 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Manipulation Of Pulses (AREA)
Description
第１図はこの考案の一実施例によるビツト反転
検出回路の論理図、第２図はそのタイミングチヤ
ート、第３図はビツト反転検出回路を含まない従
来のレジスタである。図において１はレジスタ、
２はＮＡＮＤゲート、３および１１はＯＲゲート
、４および６はインバータによる遅延回路、５は
ＥＸ―ＮＯＲ回路、７および９はＥＸ―ＯＲゲー
ト、８および１０はＡＮＤゲート、１２は出力デ
ータの次段に接続されている論理回路である。な
お、図中点線は同一時刻における各信号の相関関
係を判り易くするためのものである。また各図中
、同一符号は同一または相当部分を示す。
FIG. 1 is a logic diagram of a bit reversal detection circuit according to an embodiment of the present invention, FIG. 2 is a timing chart thereof, and FIG. 3 is a conventional register that does not include a bit reversal detection circuit. In the figure, 1 is a register,
2 is a NAND gate, 3 and 11 are OR gates, 4 and 6 are delay circuits using inverters, 5 is an EX-NOR circuit, 7 and 9 are EX-OR gates, 8 and 10 are AND gates, 12 is the next output data It is a logic circuit connected to stages. Note that the dotted lines in the figure are for making it easier to understand the correlation between signals at the same time. In each figure, the same reference numerals indicate the same or corresponding parts.
Claims (1)
る論理ゲート回路と、レジスタへのセツト・リセ
ツト入力信号を検出する論理ゲート回路と、これ
らの信号のエツジを総合的に捕えるエツジ検出回
路と、レジスタへの入力データとレジスタからの
出力データを比較する論理ゲート回路と、レジス
タからの出力データのエツジを捕えるエツジ検出
回路と、これらの回路の出力条件によりビツト反
転を判別する論理ゲート回路から成るビツト反転
検出回路。 A logic gate circuit that detects the clock pulse input signal to the register, a logic gate circuit that detects the set/reset input signal to the register, an edge detection circuit that comprehensively captures the edges of these signals, and an edge detection circuit that detects the input data to the register. A bit inversion detection circuit consists of a logic gate circuit that compares the output data from the register with the output data from the register, an edge detection circuit that captures the edge of the output data from the register, and a logic gate circuit that determines bit inversion based on the output conditions of these circuits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP331788U JPH01108625U (en) | 1988-01-14 | 1988-01-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP331788U JPH01108625U (en) | 1988-01-14 | 1988-01-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01108625U true JPH01108625U (en) | 1989-07-24 |
Family
ID=31204846
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP331788U Pending JPH01108625U (en) | 1988-01-14 | 1988-01-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01108625U (en) |
-
1988
- 1988-01-14 JP JP331788U patent/JPH01108625U/ja active Pending
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