JPH04331383A - Logic integrated circuit of semiconductor - Google Patents

Abstract

PURPOSE:To discriminate easily an operating frequency of a basic element of an IC chip only by detecting a 'Hi' or 'Lo' level of a measurement terminal of the IC chip without using particularly a measurement equipment of frequency. CONSTITUTION:In a semiconductor logic integrated circuit which has an original functional circuit and an accessory circuit for logic speed evaluation in an IC chip 1. the accessory circuit has following circuit elements: an oscillation circuit elemant 5 where inverters 4 of a reversal logic element are connected in series in a loop state of 51 stages, a dividing circuit element 6 where flip-flop circuits are connected in series of 4 stages to be put to use as a binary counter of 4 bits, and a frequency discrimination circuit element 10 consisting of a delay element 7 to reset the count value of the dividing circuit element 6 and a flip-flop circuit 9 to store the most significant bit 8 of the dividing circuit element 6.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor logic integrated circuits, and more particularly to semiconductor logic integrated circuits for high-speed operation.

0002

[Prior Art] Conventional semiconductor logic integrated circuit (hereinafter referred to as logic I)
When evaluating the operating speed of a logic IC, the clock frequency supplied to the logic IC is generally increased gradually, and the clock frequency at which the output state no longer matches the expected value is determined as the maximum operating frequency of the logic IC. , but logic I
If the operating frequency of C is higher than the measurable frequency of the LSI tester, evaluation cannot be performed.

For this reason, as shown in FIG. 6, for example, an oscillation circuit section 5 is formed by connecting inverter elements 4, which are basic circuit elements, in series in an odd number of stages in a loop, and an oscillation circuit section 5 is formed by connecting inverter elements 4, which are basic circuit elements, in an odd number of stages in a loop. A circuit configured by connecting the frequency dividing circuit section 6a that divides the signal S5 from the section 5 is used as an IC chip as an auxiliary circuit for speed evaluation, in addition to a functional circuit for realizing a desired function with a logic IC. By measuring the oscillation frequency of this attached circuit using a measuring device such as a synchronoscope or a frequency measuring device, it was used as a guide to indirectly guarantee the operating speed of the original functional circuit of the manufactured logic IC. .

0004

[Problem to be Solved by the Invention] In this conventional semiconductor logic integrated circuit, in order to guarantee the operating speed of the original functional circuit of this logic IC, the oscillation frequency of the attached circuit for speed evaluation is measured using a synchroscope or frequency measurement. Since measurements must be performed using a measuring device such as an LSI tester, for example, logic I
There was a drawback that it was not possible to evaluate the operating speed of C.

[0005]

[Means for Solving the Problems] The semiconductor logic integrated circuit of the present invention includes an original functional circuit for realizing a predetermined function,
On the same chip, as an auxiliary circuit for speed evaluation, there is an oscillation circuit section in which logic elements for inverting signals are connected in an odd number of stages in a loop, and a frequency dividing circuit section for counting the number of signal pulses from the oscillation circuit section. In semiconductor logic integrated circuits,
The speed evaluation auxiliary circuit includes a frequency discrimination circuit section that obtains a count value of the frequency division circuit section per unit time and constantly maintains the count state.

[0006]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an auxiliary circuit for speed evaluation according to a first embodiment of the present invention, and FIG. 2 is a schematic plan view of an IC chip having the auxiliary circuit for speed evaluation shown in FIG. The attached circuit 3 includes an oscillation circuit section 5 in which inverters 4 of inverting logic elements are connected in series in a 51-stage loop, and a frequency dividing circuit section in which 4 stages of flip-flop circuits are connected in series to form a 4-bit binary counter. 6, and a frequency discrimination circuit section 10 comprising a delay element 7 for resetting the count value of the frequency dividing circuit section 6 and a flip-flop circuit 9 for storing the most significant bit 8 of the frequency dividing circuit section 6.

FIG. 3 shows the clock signal CLK applied to the input terminal 11 of the block in FIG. 2 and the output signal S7 of the delay element 7.
, is an operation timing chart of the output signal S9 of the flip-flop circuit 9. The frequency dividing circuit section 6 uses the clock signal CL.
The delay element 7 to which K is input is reset when it is at a "Low" level, and counts the signal from the oscillation circuit section 5 when it is at a "Hi" level. The flip-flop circuit 8 stores and outputs the state of the most significant bit 8 of the frequency dividing circuit section 6 at the falling edge of the clock signal CLK.

For this reason, the output signal Q of the flip-flop 9
1, Q2, and Q3 are inputted from the oscillation circuit section 5 at t1, t2, and t3 after the output signal of the delay element 7 rises and the reset of the frequency divider circuit section 6 is released until the clock signal CLK falls. If the number of pulses is 8 or more, “Hi”
If it is 8 or less, it becomes a "Low" level, so it can be easily determined whether the number of pulses output by the oscillation circuit section 5 per unit time is 8 or more or 8 or less.

[0010] The delay time of inverter 4 is 0.1 nsec.
At this time, the delay of 51 stages for one circuit circuit of the oscillation circuit section 5 in this embodiment is 5.1 nsec, and the oscillation frequency at this time is approximately 100 MHz. To check this frequency,
A clock signal CLK of approximately 6.25 MHz whose half cycle is approximately 80 nsec delay value for 8 pulses of the oscillation frequency is applied to the input terminal 11, and the output signal of the flip-flop 9 becomes "H".
All you have to do is make sure that the "i" level is maintained.

In this embodiment, a 4-bit counter is used in the frequency dividing circuit section 6, but more accurate discrimination can be achieved by increasing the number of bits and adjusting the clock frequency given according to the number of counts. It is clear that this will happen.

Further, in this embodiment, the clock frequency to be applied is defined in advance to determine the frequency, but by changing the clock frequency to be applied to the input terminal 11, the output signal S9 of the flip-flop 9 changes from the "Hi" level to the " Lo
The oscillation frequency of the oscillation circuit section 5 can also be determined by determining the clock frequency when the signal changes to the w'' level.

FIG. 4 is a block diagram of an auxiliary circuit for speed evaluation according to a second embodiment of the present invention. The attached circuit 3 of this embodiment includes an oscillation circuit section 4 and a frequency dividing circuit 6, as in FIG.
A two-input NAND gate 15 that connects and disconnects the signal S5 from the oscillation circuit section 4 using the clock signal CLK from the input terminal 11, a one-shot circuit 16 that receives the clock signal CLK, and outputs a one-shot pulse signal S16, and a frequency divider. The frequency discrimination circuit section 10a includes a flip-flop 9 that stores the most significant bit 8 of the circuit 6.

FIG. 5 is an operation timing chart of the clock signal CLK applied to the input terminal 11, the output signal S15 of the two-input NAND 15, the output signal S16 of the one-shot circuit 16, and the output signal S9 of the flip-flop circuit 9.

The frequency dividing circuit section 6 is connected to the one-shot circuit 16.
It is reset by the "Low" pulse, and when the clock signal CLK is at the "Hi" level, the signal S15 from the oscillation circuit unit 4 that enters through the two-input NAND 15 is counted.

Therefore, the count times t1, t2, and t3 are exactly half the period of the clock signal CLK, so although the circuit configuration is somewhat complicated, it is possible to determine the frequency more accurately than in the first embodiment. .

[0017]

[Effects of the Invention] As explained above, the present invention has an auxiliary circuit for evaluating the speed of basic elements, which is provided separately from the original functional circuit for realizing the prescribed functions of a semiconductor logic integrated circuit. We have added a frequency discrimination circuit that calculates the count value of the frequency divider circuit and then constantly maintains the count state, making it easy to determine the frequency of the basic element circuit without having to prepare a measuring device such as a frequency measuring device. It has the effect of being able to discriminate between the two.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an attached circuit for speed evaluation according to a first embodiment of the present invention.

FIG. 2 is a schematic plan view of the semiconductor chip of the first example.

FIG. 3 is a timing chart for explaining the operation of the blocks in FIG. 1;

FIG. 4 is a block diagram of an attached circuit for speed evaluation according to a second embodiment of the present invention.

FIG. 5 is a timing chart for explaining the operation of the blocks in FIG. 4;

FIG. 6 is a block diagram for explaining an example of a conventional semiconductor logic integrated circuit.

[Explanation of symbols]

1 IC chip 2 Functional circuit 3 Attached circuit for speed evaluation 4 Inverter element 5 Oscillation circuit section 6 Frequency division circuit section 7 Delay element 8 Most significant bit 9 Flip-flop circuit 10,10a Frequency discrimination circuit 11 Input terminal 15 2-input NAND element 16 One-shot circuit

Claims (1)

[Claims] Claim 1: An oscillation circuit section in which an original functional circuit for realizing a predetermined function, a logic element for inverting a signal as an auxiliary circuit for speed evaluation are connected in an odd number of loops on the same chip, and the oscillation In a semiconductor logic integrated circuit having a frequency dividing circuit section for counting the number of signal pulses from a circuit section, the auxiliary circuit for speed evaluation calculates the count value of the frequency dividing circuit section per unit time and calculates the count value of the frequency dividing circuit section per unit time. 1. A semiconductor logic integrated circuit comprising a frequency discrimination circuit section that constantly maintains a state.