RU1777118C - Time interval meter - Google Patents

Abstract

The invention relates to a measurement technique. The meter contains: 2 delay elements (1), (2), 2 comparison schemes (3), (4), 3 matching schemes of the second group (5), (6). (7). 3 blocks of storage elements (8), (9), (10) of the second group, 3 coincidence schemes of the first group (11), (12),

Description

The invention relates to a measurement technique and can be used to measure time intervals in the nanosecond range.

A device is known that contains measuring delay lines, the outputs of which are connected to the first inputs of the coincidence circuits, the second inputs of which are connected to the pulse input of the end of the measurement, and the outputs of the coincidence circuits are connected to an encoding device.

The disadvantage of this meter is the small size of the measuring range, which narrows the scope of the device.

Known meter time intervals of the nanosecond range, containing the first and second blocks of the delay line connected in parallel with their outputs through the corresponding matching circuit to the first and second blocks of storage elements, while the input of the start pulses is connected simultaneously with the inputs of all delay lines of the first block directly the second block through the generator-recirculator. The inputs of all coincidence circuits are connected and connected to the input of stop pulses. A disadvantage of this device is the large number of delay lines.

The closest in technical essence to the proposed time interval meter is a time interval to digital code converter containing a reference interval counter, an account control trigger, improved precision bit triggers connected to the low-order binary code generation circuit of the measurement method in a combinational manner.

The disadvantage of this meter is the limited scope of application, due to the need to ensure that the start pulse coincides with the reference frequency pulse in order to eliminate errors at the beginning of the measurement, which imposes corresponding restrictions on the reference pulse generator circuits.

The aim of the invention is to increase the accuracy of the meter by eliminating the quantization error at the beginning of the measurement.

This goal is achieved by the fact that in the time interval meter containing a reference interval counter, an account control trigger, memory elements of the first group, the installation inputs of which are connected to the outputs of the coincidence circuits of the first group, elements of the restraint of lower combination bits, a gate circuit, a control input which is connected to the output of the account control trigger, and the output to the counting input of the reference interval counter,

coincidence schemes of the second group are introduced, the memory elements of the second group and the differentiation scheme, while the first information input of the first comparison circuit is connected to the input of the first delay element, the input of the reference frequency, the input of the differentiation circuit, the output of which is connected to the information input of the valve circuit, the first information input first match patterns

5 of the first and second groups, the second information input of the first comparison circuit is connected to the output of the first delay element, the output of the first comparison circuit is connected to the first information input of the second

0 comparison circuit, the input of the second delay element, the first information input of the second coincidence schemes of the first and second groups, the second information input of the second comparison circuit is connected to the output of the second delay element, the output of the second comparison circuit is connected to the first information inputs of the third coincidence schemes of the first and second groups the outputs of the coincidence circuits of the second group are connected

0 with the setting inputs of the storage elements of the second group, the second information inputs of the coincidence circuits of the second group are combined and connected to the input of the pulse of the beginning of the measurement and the input of the setting of the trigger for counting, the second information inputs of the coincidence circuits of the first group are combined and connected to the input of the pulse of the end of the measurement and the reset input a count enable trigger, the gate circuit further performs the function of expanding the pulses.

In FIG. 1 shows the functional diagram of the meter; in FIG. 2 - an example of a particular embodiment of circuits 3.4, b, 7.17.18, 20

5 meter; in FIG. 3 is a timing diagram of the meter.

The time interval meter (Fig. 1) contains delay elements 1 and 2, comparison circuits 3 and 4, schemes of 5-7 matches of the second group, memory elements 8-10 of the second group, schemes 11-13 of matches of the first group, memory elements 14- 16 of the first group, counting enable trigger 17, gate circuit 5 expander 18 pulses, counter 19 reference intervals, differentiation circuit 20, indication unit 21.

The input of the delay element 1 is connected to the input 30 of the reference frequency, the input of the differentiation circuit 20, the first information input of the comparison circuit 3, the first information inputs of the first second and first group matching circuits 5 and 11, the output of the differentiation circuit is connected to the information input of the fan circuit 18.

The output of delay element 1 is connected to a second information input of comparison circuit 3. The output of the comparison circuit 3 is connected to the input of the delay element 2, the first information input of the comparison circuit 4, the first information inputs of the second coincidence circuits 6 and 12 of the second and first groups.

The output of the delay element 2 is connected to the second information input of the comparison circuit 4. comparison circuit 4 is connected to the first information inputs of coincidence circuits 7 and 13 of the second and first groups.

The second information inputs of the second group coincidence circuits 5-7 are connected to an input 31, from which a pulse of the beginning of the measured time interval is received, and which is also connected to the installation input of the counting resolution trigger 17.

The output of the first coincidence circuit 5 of the second group is connected to the installation input of the first element 8 for storing the second group, the output of which is connected to the output 23 of the meter and the input of the display unit 21.

The outputs of the second circuit b and the third coincidence circuit 7 of the second group are connected respectively to the installation inputs of the memory elements 9 and 10 of the second group, the outputs of which are connected, respectively, with the outputs 24 and 25 of the meter and the inputs of the display unit 21.

The second information inputs of the coincidence circuits 11-12 of the first group are connected to the input 22. from which a pulse is received from the end of the measured time interval and which is also connected to the reset input of the account resolution trigger 17.

The output of the first coincidence circuit 11 of the first group is connected to the installation input of the element 14 for storing the first group, the output of which is connected to the output 26 of the meter and the input of the indicator unit 21.

The outputs of the second circuit 12 and the third coincidence circuit 13 of the first group are connected respectively to the inputs of the memory elements 15 and 16 of the first group, the outputs of which are connected respectively to the outputs 27 and 28 of the meter and the inputs of the display unit 21. B: Odes for setting the memory elements 14-16, 8-10 of the first and second groups and the counter 19 in FIG.

1 are not shown. The outputs of the counter 19 are connected to the external outputs 29 of the meter and the inputs of the display unit 21. Comparison schemes 3 and 4 are logic elements that implement the logic function equivalence Y X Y + X Y.

As the storage elements 14-16, 8-10 of the first and second groups in FIG. 1 shows RS triggers. Prior to the start of measurement, all triggers are set to the zero state (the input of the installation to state O is not shown in Fig. 1).

The differentiation circuit 20 performs the function of logical differentiation - when the logical state at the input of the circuit changes from 1 to O, a short pulse is emitted at the circuit output with an amplitude equal to a single logic level and with a duration minimally sufficient for passing through the VTR circuit - expander 18 pulses. The gate circuit is an expander of 18 pulses in the presence of a unit potential at the control input and if there is a pulse at the information input coming from the output of the differentiation circuit 20, generates a pulse with a duration sufficient to process the counter 19. Standard devices are known that perform a gate function and function pulse expansion, for example a chip 133AP,

In FIG. 2 discloses the construction of circuits 3, 4. 6, 7. 17, 18, 20 of FIG. 1 on standard elements. The groups of elements making up these circuits are shown in FIG. 2 are circled by a dotted line indicating the corresponding circuit numbers of FIG. 1.

Comparison Scheme 3 consists of elements 32 ... 37. Elements 32, 33, 36 are inverting amplifiers, elements 34, 35 are logical elements AND, element 37 is a logical element OR. Elements 32, 33, 36 have a bandwidth of at least 25 GHz. Delayed items

D gz2 A 7zz A gzb 50-100 ps. Elements 34, 35, 37 are implemented on standard microcircuits and have typical non-propagation delays.

Elements 40, 41, 42 are common to circuits 4 and 7. Circuit 4 also includes elements 38, 39 — inverting amplifiers and element 43 — non-inverting amplifiers. Schemes 4 and 7 in FIG. 2 are equivalent to circuits 4 and 7 in FIG. 1, since the logical function they perform is the same:

Y U V-Z + U 7-Z.

Elements 44 and 45 are an RS flip-flop, elements 46, 47 are inverting amplifiers, element 48 is a delay line that determines the magnitude of the coincidence zone when forming the pulse duration in elements 49, 50, when the resolution is received from element 44.

Elements 44, 45, 49 are standard circuits with a typical 1 ns signal propagation delay.

The propagation delays of the signals in all of these elements can be compensated for by a delay in the pulse generation circuit of the beginning of the measurement (this diagram is not shown in Fig. 1) and by adjusting the response threshold of the logic elements. Thus, the uncertainties in the formation of the time intervals of the measuring grid of the lower Raman bits and the zone of uncertainty in the formation - non-formation of the counting pulses of the meter can be made sufficiently small and the reliability of the lower bits of the meter (combinational and the first counting) will be close to 100%.

The meter works as follows.

From input 30, a reference frequency with a period T in the form of a meander, i.e. the duration of a single logical level is equal to the duration of a zero logical level (see Fig. 3). This frequency at the second input of the comparison circuit 3 is time shifted by T / 4 due to the delay element 1. As a result, at the output of the comparison circuit 3, a frequency is formed in the form of a meander with a half-period of T / 4 (see Fig. 3).

Similarly, at the output of the comparison circuit 4, a frequency is generated in the form of a meander with a half-period of T / 8 (see Fig. 3).

From the outputs of the comparison circuits 4 and 3, as well as from the clock input 30, the frequencies with half periods T / 8, T / 4, T / 2, respectively, are supplied to the first inputs of the coincidence circuits 5-7 and 11-13.,

When the pulse of the beginning of the measured interval (Fig. 3 - Start) arrives from input 31 of the pulse, the second inputs of coincidence schemes 5-7 of the second group receive pulses at the outputs of coincidence schemes 5-7 if the start pulse coincides with a single logical level of the half period of the corresponding the frequency supplied to the first inputs of these circuits. These pulses are fed to the corresponding elements 8-10 of storing intervals of the second group, the outputs of which are outputs 23, 24, 25 of the meter. The low-order bits of the measurement start code are generated from these outputs, generated in an uncountable manner. The weight of the bit at output 23 is T / 2, at output 24 it is T / 4, and output 25 is T / 8. The start pulse, in addition, sets the counter enable trigger 17 to state 1 and the gate circuit — the pulse expander 18 passes the reference frequency from the output of the differentiation circuit 20 to the counter 19, in which

0, the number of transitions from state 1 to O potential at input 30 and, thus, a binary code of counting bits of the measurement code is generated at outputs 29, the least significant bit of which has a weight T, i.e. is equal to

5 the value of the period of the reference frequency at the input 30.

At the moment of arrival from the input 22 of the pulse of the end of the measured interval in the circuits 11-13 matches of the first group and elements

0 14-16 storing the first group, which are connected to the outputs 26, 27, 28. In an uncountable way, the values of the bits of the end measurement code are generated. The weight of the bit at the output 26 is equal to T / 2 at the output 27 is equal

5 T / 4, output 28 is T / 8. In addition, with the arrival of a stop pulse, the count enable trigger 17 is set to state O and the gate circuit 18 does not pass the pulses of the reference frequency T to the counter 19.

0 in FIG. Figure 3 shows the measurement case when 2 pulses arrived at the counter 19 between the arrival times of the start pulse and the stop pulse. therefore, on outputs 29 binary code 10 will be issued, which

5 corresponds to the number 2 in the decimal number system. The weight of the least significant bit of this code is T. Given the presence in the meter of the other three least significant bits with T / 2 weights. T / 4, T / 8, which form uncountable

In a way, the counting part of the measurement code for the example in question is written by code 10000.

The moment of arrival of the start pulse in FIG. 3 coincided with a single half-cycle of the T / 4, T / 8 grooves and did not coincide with a single half-cycle of the T / 2 meanders, therefore, outputs 24 and 25 will give a single value, and output 23 will have the zero bits of the least significant bits of the measurement start code,

0 obtained in an uncountable manner, and the corresponding measurement start code will be 011.

The moment of arrival of the stop pulse in FIG. 3 coincided with the unit half-periods of the Me5 T / 2 and T / 8 and did not coincide with the unit half-periods of the T / 4 meander, therefore, outputs 26 and 28 will give a single value, and output 27 - the zero value of the lower-order bits of the measurement end code, obtained in an uncountable way, and accordingly

The appropriate end code will be 101.

Measurement result in general form:

Kism Ketch Kn Kk,

where Kism is the binary code of the measurement result;

KSch binary code of the number of intervals T, fixed in the circuit 19 of the calculation of the reference intervals and issued at the outputs 29;

Kn is the binary code of the start of measurement, fixed in the memory circuits 8-10 and issued at outputs 23-25:

Kk is the binary code of the end of measurement recorded in the storing circuits 14-16 and issued at outputs 26-28.

For the example considered, the measurement result in binary code: Kism Ketch Kn + Kk

10000-011 + 101 10010 or, taking into account the weights of the binary bits, the measurement result for the considered case in units of the reference interval will be:

Kiem 10010 1-21-T + 0-2 ° .T +

+ 0-2 1.T + .T + (2 + 1/4) T.

An indication unit 21 is used to indicate the measurement result. Codes Ksch, Kk, K are displayed on the scoreboard of block 21 in digital form, with the code Ksch as the main value, the code Kk as the positive correction, the code Kn as the negative correction.

Thus, in the proposed meter, the time between the start pulse and the first reference pulse is measured by an uncountable method, and the quantization error at the beginning of the measurement is reduced by almost an order of magnitude (8 times) compared with known meters that do not use the synchronization of the reference frequency generator start pulses.

Claims (1)

SUMMARY OF THE INVENTION A time interval meter comprising a reference interval counter, an account control trigger, memory elements of a first group, installation inputs of which are connected to circuit outputs coincidence of the first group, delay elements of the lower combinational bits, a gate circuit, the control input of which is connected to the output of the counting trigger, and the output is connected to the counting input of the reference interval counter, characterized in that, in order to increase the measurement accuracy, the first and a second comparison circuit, coincidence circuits of the second group, storage elements of the second group and differentiation circuit, the first information input of the first comparison circuit is connected to the input of the first delay element; the reference frequency input, the input of the differentiation circuit, the first information inputs of the first matching circuits of the first and second groups, the second information input of the first comparison circuit is connected to the output of the first delay element, the output of the first comparison circuit is connected to the first information input of the second comparison circuit, the input of the second delay element, the first information inputs of the second matching circuits of the first and second groups, the second information input of the second comparison circuit is connected to the output of the second delay element, the output of the second comparison circuit is connected to the first information inputs of the third matching circuits of the first and second groups, outputs of the matching circuits of the second group are connected to the installation inputs of the storage elements of the second group, the second information inputs of the matching circuits of the second group are combined and connected to the input of the pulse of the beginning of the measurement and the input of the setup of the account control trigger, the second information inputs of the circuits coincidences the first group are combined and connected to the pulse input of the end of the measurement and the reset input of the counting trigger, the information input of the gate circuit is connected to the output of the differentiation circuit wherein the gate circuit further functions as a pulse expander. (/AND jki ritwM4 J jh-TLr JlrtLrLTLTL oh ty, Tg Turn s 31 22 U 17 i and About Start & q counter f9 a Lj-u Zt  3G Stop t Vttt.S