RU6922U1 - DEVICE FOR ACCOUNT OF TIME INTERVALS - Google Patents

Abstract

1. A device for counting time intervals, comprising a clock pulse switch, a pulse counter and a microprocessor, characterized in that a latch register is introduced into the device, in which the information inputs of D-type triggers are connected to the input of the clock pulse switch via delay lines, and C-inputs of the information recording are connected to the stop signal supply channel. 2. The device according to claim 1, characterized in that the number of D-type triggers of the register-latch corresponds to the selected counting error.

Description

The device relates to the field of measuring equipment, in particular, to measuring devices, which fill in the counting of time intervals between two events or between the beginning and the end of an event.

In most cases, the measurement of time intervals using digital measuring devices based on microprocessor means is performed according to the scheme shown in Fig. 1.

The diagram shows:

1- switchboard clock pulses {KTCH),

2- pulse counter {MF),

3 - microprocessor (MP),

RTact - - the supply of clock pulses.

A similar scheme for measuring time intervals was used, for example, in the liquid flow meter URSV 010, manufactured by IHP Rise, the number of the device in the State Register of Schedborry 13716-94.

The operation of the device is as follows: the Start signal allows the passage of pulses of the clock frequency Ch1 frequency to the binary counter. Pulse counting is carried out by the differential signal Ktakt. from low to high. At the Stop signal, the passage of pulses to the stop pulse counter; / e7jJ

- nine -

A signal is sent to the processor about the end of the count. The processor reads from the counter a binary number corresponding to the number of pulses received in the counter during the time between the Start and Stop signals. Moreover, the pulse repetition period is known and equal to. The calculation of the time interval is performed according to the formula

H is the number of pulses read by the processor from the pulse counter.

With such a pulse reading for measuring time intervals, an error is always present due to the mismatch of the Stop signal and the counted pulse difference of the taost frequency. This is shown in the diagrams in FIG. 2.

This disadvantage of the meters used is common to all currently known meter designs. The error in measuring the end of the count for these structures will always be negative and has the form shown in Fig.Z.

A decrease in this type of error with such a measurement scheme is possible only with an increase in the clock frequency, which in itself presents a serious technical difficulty. So, first of all, increasing the clock frequency will require the use of faster, and therefore more expensive circuits used in the pulse switch and counter, and stable clock generators for high frequencies, which are ROADS and GROT

Rtact.

t T X N, where

craps. The presence of high frequency pulses may require shielding of individual microcircuits and careful isolation of the power circuits. In addition, with the increase in the frequency of work of digital microcircuits, their energy consumption sharply increases, which is unacceptable and excluded for portable devices.

The aim of the present invention is to reduce the error of the end of the account in 2, 4, 8, etc. times without increasing the clock frequency. For this, a new scheme of the device for measuring the time interval, shown in Figure 4, is proposed, the distinguishing feature of which is the presence of a D-type trigger (2-fold error reduction).

The information input D of the trigger is connected to the input of the clock pulse switch (signal Ract.), And the Stop signal is connected (supplied) to the input of information recording C.

The device operates as follows:

By the Start signal, the pulses of the clock frequency RTact. begin to pass to the binary counter (to the information input D of the trigger, these pulses arrive constantly).

At the Stop signal, the passage of pulses to the pulse counter is stopped. 1 will be written to the trigger if the signal about the end of the count came at the moment of a positive half-wave of the clock signal (during this time, the value of the count error is less than or equal to T / 2), or О will be recorded if the Stop signal arrived at the moment of the negative half-wave of the clock signal (at this account error will be greater than T / 2). The processor analyzes the trigger state (Bit of a large BWO error) and calculates according to the formula:

t N X T, if BWO 1, or + T / 2, if BWO O.

In this case, the error of the count will have the form shown in Fig-5 by a solid line. In this case, the measurement error will always be depreciating and 2 times less in magnitude than in the prototype. The measurement error of the original circuit is shown by a dotted line.

Another algorithm for processing information read by the processor is possible:

t N X T if BWO 1 and t (N + 1) X T if BWO - O.

In this case, the error will change sign, but in absolute value it will be half as much as the original one and will take the form shown in Fig. 6 by a straight line (the initial error is by a dashed line). It is possible to further reduce the error of the end of the account without increasing the clock frequency at very low cost. With this, the measurement circuit will take the form shown in Fig. 7., where; 1 - switch pulses of clock frequency,

2- pulse counter,

3 - microprocessor, 4,5,6 - delay lines,

7 - register-latch of 1 triggers.

The number of delay lines can theoretically be any, but the number of delay lines, the amount of delay in each of them, and the amount of error reduction are related by specific laws. So if:

k is the number of delay lines,

 i.r

- 4 t - maximum error, s, A - error reduction value {2,4,8, ... etc. times) then

 t T / A

The internally diagrammed devices at k 3 will take the form shown in FIG. 8. At the same time, depending on the moment of arrival of the Stop signal (tl - 1.8), the corresponding code will be written into the latch register, which will be analyzed by the microprocessor and the calculation will be made using the formula:

t: r t X N + X, where

X is the correction value, which varies depending on the correction code recorded in the latch register in accordance with Table 1. The amount of correction depending on the code

Table 1

The error in this case will always be negative and smaller in magnitude than in the original measurement scheme and will take the form shown in Fig.9, where:

Rtact. - clock frequency,

- time of arrival of the Stop signal, Accuracy - the magnitude of the error.

 - error of the initial measurement scheme,

 - the error of the proposed measurement scheme, with RTact. - 10 MHz the duration of the measured time interval biz. - 1 μs, and

T - 1/10 ::: UONS 0, 1MKS

The error of the original circuit:

t T / tM X 100%: g 0.1 / 1 X 100% 10%, The error of the proposed scheme: t ({T: A / Lism.) X 100% {(0.1: 8): 1) x 100 %: 1.25%.

Thus, with insignificant hardware and software costs, it is possible to achieve precision measurement accuracy in measuring instruments, which are currently assigned to the group of instruments of medium and low accuracy.

It follows from the foregoing that a useful model of the device for counting time intervals is proposed, comprising a clock pulse switch, a pulse counter, and a microprocessor

characterized in that

a latch register is introduced into the device, in which the information inputs of D-type triggers are connected to the input of the clock pulse switch via delay lines, and the information recording inputs

 g rhenium. With connected to the feed channel From the analysis of the claimed and identical in technical devices is not available. Stop signal. known solutions it follows that the essence and the problem to be solved

Claims (2)

1. A device for counting time intervals, comprising a clock pulse switch, a pulse counter and a microprocessor, characterized in that a latch register is inserted into the device, in which the information inputs of D-type triggers are connected to the input of the clock pulse switch through the delay lines, and C-inputs of the information recording are connected to the stop signal supply channel.  2. The device according to claim 1, characterized in that the number of D-type triggers of the register-latch corresponds to the selected counting error.