JPH04328629A - Adder circuit - Google Patents

Abstract

PURPOSE:To unify a field memory and an adder into a single body by using them in time division for addition of the lower bits and the upper bits to each other. CONSTITUTION:The 6-bit data is divided into 3 upper bits and 3 lower bits by a multiplexer 12 and then converted into the 4-bit data including a carry bit by a 4-bit latch. An adder 18 adds the lower bits of the precedent field delayed by one on field by a 4-bit field memory 16 to the lower bits of the present field and then adds the upper bits to each other. The addition result of lower bits is latched by a 4-lower bit latch 20. The uppermost bit of the latch 20 is carried up through an AND gate 26 when the upper bits are added together. Then the addition result data on the supper bits given from the adder 18 and the addition result data on the lower bits given from the latch 20 are outputted from a 7-bit latch 22 as the result data.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an adder circuit, and more particularly to an adder circuit for adding 6-bit data such as television signal data.

0002

2. Description of the Related Art FIG. 5 shows a conventional 6-bit data adding circuit 1 that adds 6-bit television signal data using a general-purpose 4-bit adder. In this adder circuit 1, 6-bit data is latched into a 6-bit latch 2, the upper 2 bits of the data in the 6-bit latch 2 are given to a 4-bit field memory 3, and the lower 4 bits are given to a 4-bit field memory 4. It will be done. The high-order 2-bit data of the previous field delayed by one field by this 4-bit field memory 3 and the high-order 2-bit data of the current field latched in the 6-bit latch 2 are given to a 4-bit adder 5, and the 4-bit field memory Lower 4 of previous field delayed by 1 field with 4
The bit data and the lower 4 bit data of the current field of the 6-bit latch 2 are applied to a 4-bit adder 6. Therefore, the 4-bit adder 6 adds the lower 4 bits together, and gives the carry signal to the 4-bit adder 5.
The 4-bit adder 5 adds the upper 2 bits of data. Therefore, the 4-bit adder 4 outputs 4-bit operation result data, and the 4-bit adder 5 outputs 3
Bit operation result data is output. This total 7-bit data is latched by the 7-bit latch 7 in response to the clock signal CLK1 from the same timing signal generator 8 as the 6-bit latch 2.

0003

The conventional 6-bit adder circuit shown in FIG. 5 requires two 4-bit field memories and two 4-bit adders, and therefore has the disadvantage of being wasteful. Therefore, the main object of the present invention is to provide a lean 6-bit adder circuit.

0004

[Means for Solving the Problems] The present invention provides an adder circuit for adding 6-bit data together, a dividing means for dividing the 6-bit data into lower 3 bits and upper 3 bits, and outputting the lower 3 bits. Bit converting means for converting 3 bits and upper 3 bits into 4 bits of first data and second data, respectively; memory means for receiving the first data and second data from the bit converting means at different timings;
Addition in which the first data from the bit conversion means and the first data from the memory means are added at a first timing, and the second data from the bit conversion means and the second data from the memory means are added at a second timing. latch means for latching the 4-bit result data obtained from the adder at the first timing, carry signal means for supplying the most significant bit of the latch means to the adder at the second timing, and 3-bit result data from the latch means. The adder circuit includes output means for outputting the result data and the 4-bit result data obtained from the adder at the second timing as 7-bit data.

[0005]

[Operation] When the first 6-bit data is input to the adder circuit, the dividing means divides it into the lower 3 bits and the upper 3 bits. The lower 3 bits and the upper bit are converted by the bit conversion means into corresponding 4-bit first data and second data, respectively, and stored in the 4-bit memory means at different timings. The next 6-bit data is similarly converted into 4-bit first data and 4-bit second data. Therefore, first, the adder adds the first data of the first 6-bit data read from the memory means and the first data of the next 6-bit data from the bit conversion means at the first timing. This addition result data is latched into a 4-bit latch means. At a second timing following the first timing, the adder adds the second data of the first 6-bit data read from the memory means and the second data of the next 6-bit data from the bit conversion means. However, at this time, the most significant bit is given to the adder as a carry signal from the latch means. Therefore, at the second timing, when a carry signal is generated as a result of the addition at the first timing, the carry signal is added when the second data are added together. At the second timing, 4-bit result data is output from the adder, and this and the remaining 3 bits of the latch means are output from the output means as total 7-bit addition result data.

[0006]

According to the present invention, 6-bit data is divided into the upper 3 bits and the lower 3 bits, and these are stored in one memory means in a time-sharing manner and sequentially operated on in one adder. By doing so, it is possible to reduce the number of memories and 4-bit adders, which conventionally required two each, to one each. In addition, the carry bits generated as a result of the addition of the first data are input to the adder at the timing of the addition of the second data, so 7-bit result data can be obtained without adding a separate carry bit. .

The above objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

[0008]

[Embodiment] A 6-bit adder circuit 10 according to an embodiment of the present invention shown in FIG. In accordance with the clock signal CLK1 from 24, time divisionally (selectively)
Output. That is, the multiplexer 12 divides the input 6-bit data into the lower 3 bits and the upper 3 bits,
Output in that order. "0" is added to the most significant part of the 3-bit output from the multiplexer 12 to create 4-bit data, which is latched into the 4-bit latch 14. The data latched in this 4-bit latch 14 is given to a 4-bit field memory 16, and is also applied to a 4-bit adder 18.
is given to one input. The other input of the 4-bit adder 18 is given 4-bit data read from the 4-bit field memory 16 and delayed by one field. That is, adder 18 adds the 4-bit data from 4-bit field memory 16 and the 4-bit data from 4-bit latch 14.

The addition result output of the 4-bit adder 18 is applied to the lower 4-bit latch 20, and is also applied to the 7-bit latch 22 as upper 4-bit data. The 4-bit latch 14 and the lower 4-bit latch 20 latch data in response to the clock signal CLK2 from the timing signal generation circuit 24. This timing signal generator 2
Carry gate signal from 4 and lower 4 bit latch 20
The most significant bit of the 4-bit adder 18 is applied to the AND gate 26, and the output of the AND gate 26 is applied to the carry input of the 4-bit adder 18. Note that the 7-bit latch 22 latches the upper 4 bits from the 4-bit adder 18 and the lower 3 bits from the lower 4-bit latch 20 as 7-bit data in response to the clock signal CLK3 from the timing generator 24. .

In the 6-bit adder circuit 10 of this embodiment shown in FIG. 1, 6-bit data A is input to the multiplexer 12 as shown by A in FIG. This input 6-bit data is shown in FIG. The multiplexer 12 outputs data in the order of the lower three bits and the upper three bits, as shown by B in FIG. This multiplexer 12
The output B from the 4-bit data latch 14 is latched in response to the rising edge of a clock signal CLK2 having twice the frequency of the clock signal CLK1 shown in FIG. The most significant bit added by the 4-bit data latch 14 is a carry bit and is "0". The state of the data at this time is shown in FIG. In this way, both the lower three bits and the upper three bits from the multiplexer 12 are converted into 4-bit data to which the most significant carry bit is added.

Then, the 4-bit data C with a carry bit added to the lower 3 bits is transferred to the 4-bit field memory 16 and the 4-bit adder 18. 4
In the bit field memory 16, the 4-bit data C is delayed by one field as shown in FIG.
Output as . The data D delayed by one field and the data C of the current field are added by a 4-bit adder 18, and the operation result data shown as E in FIG. 2 is obtained. This operation result data is latched into the lower 4 bit latch 20 in response to the previous fall of the clock signal CLK2. In this way, the 4-bit adder 18 first performs addition of the lower 3 bits (4 bits).

Then, the most significant 1 bit of the 4-bit data latched in the lower 4-bit latch 20 and the carry gate signal are logically summed, and from the AND gate 26,
Carry up to 4-bit adder 18. Therefore, the carry gate signal from the timing signal generator 24 goes high only when the upper bits are added together, as shown in FIG.

Similar to the above-mentioned addition of lower bit data,
The upper bit data divided by the multiplexer 12 is divided into 4
The bit adder 18 adds the bits. Therefore, at this timing, the 4-bit adder 18 obtains a 4-bit operation result including the carry bit when adding the lower bits. The 7-bit latch 22 outputs the operation result data E between the upper bits and the operation result data F between the lower bits using the clock signal CLK as shown in FIG.
It latches in response to the rising edge of 3. In this way, 7-bit data as shown by G in FIG. 2 is obtained from the 7-bit latch 22.

[0014] In the above embodiment, television signal data is used as an example of 6-bit data, and data delayed by one field and data of the current field are added, but this is not limited to this embodiment. Rather, the present invention can be applied to a 6-bit adder circuit that adds arbitrary 6-bit data.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing diagram showing the operation of the embodiment of FIG. 1;

FIG. 3 is an illustrative diagram showing input 6-bit data.

FIG. 4 is an illustrative diagram showing that one carry bit is added to each of the divided lower three bits and upper three bits to convert them into 4-bit data.

FIG. 5 is a block diagram showing an example of a conventional 6-bit adder circuit.

[Explanation of symbols]

10...6-bit addition circuit 12...Multiplexer 14...4 bit latch 16...4-bit field memory 18...4-bit adder 20…lower 4 bits latch 22…7 bit latch 24...Timing signal generator 26…AND gate

Claims (1)

[Claims] Claim 1: An adder circuit that adds 6-bit data to each other, the 6-bit data being added to the lower 3 bits and the upper 3 bits.
a dividing means for dividing and outputting the lower 3 bits and the upper 3 bits into 4-bit first data and second data, respectively; a bit converting means for converting the lower 3 bits and the upper 3 bits into 4-bit first data and second data; memory means for receiving the second data at different timings; adding the first data from the bit converting means and the first data from the memory means at a first timing; and adding the first data from the bit converting means at a second timing; 2 data and second data from the memory means; latch means for latching the 4-bit result data obtained from the adder at the first timing; A carry signal means for giving to the adder at a second timing, and an output for outputting 3-bit result data from the latch means and 4-bit result data obtained from the adder at the second timing as 7-bit data. an adder circuit comprising means.