JPS60247324A - Binary code generator - Google Patents

Abstract

PURPOSE:To obtain plural binary codes generated at optional timing with simple constitution without increasing the numbers of component parts of a circuit, by adding the output signal read out of a prescribed address of a memory with which the writing/reading is possible at all times with the prescribed 1st binary code and deciding whether or not the added signal is coincident with the 2nd binary code. CONSTITUTION:A RAM2 reads out the data written in the first half of an address and writes new data in the latter half respectively. The output signal of a latch 4 is supplied to the outside as a binary code output signal and also to an input terminal at one side of an adder 5. The output signal N of the adder 5 is supplied to an input terminal DSB at one side of a data selector as well as to a constant detecting circuit 7. Then it is decided whether the signal N is coincident or not with a prescribed binary code. When the coincidence is obtained, an H level is outputted to output signal lines Oa-Od of the corresponding channel at a detected time division processing time point.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to equipment that handles digital signals, and particularly to equipment that needs to independently generate a large number of binary codes.

Conventional configurations and their problems In recent years, the development of equipment that handles digital signals has been remarkable, and in particular, applications in the field of digital audio are attracting attention as digital audio. In the process of signal processing, binary codes that advance are often used for memory addresses and the like. FIG. 1 shows an example of a circuit with the most general and simple configuration for obtaining a 4-bit binary code using a counter. Counter 1 counts the number of clock pulses given to the clock terminal ■ and outputs the output terminal @
, ■, ■, ■ represent 4-bit binary codes.

FIG. 2 is a timing waveform diagram, in which A is the applied clock pulse, and B, C, D, and E are output waveforms corresponding to the output terminals of the counter shown in FIG. In this case, to increase the number of bits of the binary code, it is sufficient to connect the colors in series. For example, in order to obtain a 16-bit binary code, four 4-bit counters as shown in FIG. 1 may be used.

However, when processing digital signals, several systems of independent binary codes may be required. An example will be described below. Figure 3 shows the reproduced digital signal and the input signal when a pan-nine-out operation is performed on a multi-channel digital tape recorder, which is a function that rewrites part of an already recorded channel while maintaining signal continuity. FIG. 2 is a block diagram of a cross-fade circuit for smoothly switching between digital signals and digital signals. In FIG. 3, MPL1.2 is a digital multiplier, ADl is a digital adder, and Nv is a logic inversion element.

The operation will be explained below with reference to FIG. Digital data x1 reproduced from the magnetic tape is input to a digital multiplier MPL1, multiplied by a multiplier input Y, and then input to one input end of a digital adder AD1. On the other hand, digital data x2, which is a recording signal input from the outside, is similarly input to the digital multiplier MPL2, and after being multiplied by the complement Y of Y, which is the multiplier of the digital multiplier MPL1, the digital data x2 is inputted to the other side of the digital adder AD1. is input to the input terminal of. Therefore, Z=X+ -Y+X2-Y is obtained as the output signal 2 of the digital adder AD1. Most commonly used digital multipliers use parallel signals for multiplier, multiplicand input, and multiplier output.

Now, if all parallel bits of multiplier Y are logical 0, it corresponds to the absolute value "'0", and when they are logical 1, they correspond to the absolute value n1n. When punching in, the absolute value of multiplier Y is gradually changed from "1" to "σ' (therefore, the absolute value of the multiplier Y is gradually changed from "6o" to "1"). Conversely, when punching out, the absolute value of the multiplier Y is changed to "60". to "'1" (therefore, the absolute value of the multiplier Y is "
(gradually changing from 1'' to 0''), the digital adder output 2 can be smoothly changed from xl to X2 or from x2 to X1. The above operation is called a crossfade operation in a digital tape recorder.

However, in the case of a multi-channel tape recorder, the number of channels is about 16 to 32.

It is necessary to perform pan-nine-out for each channel independently and at arbitrary timing.

Therefore, it is necessary to prepare multiplier generating circuits corresponding to the number of channels that generate the multiplier Y to be input to the digital multiplier. Furthermore, since the multiplicand input signal to the digital multiplier is generally inputted by channel division, it is necessary to also divide the multiplicand input signal corresponding to each channel by channel division according to the multiplicand input signal. If this multiplier generation circuit is configured using a counter as shown in FIG. It is necessary to prepare a 64-bit counter for each channel.If you also include data selectors and 3-state buffers for converting the counter output of each channel into time-division signals, the circuit scale will increase significantly. However, this has been a major obstacle in terms of cost, space, power consumption, etc.

OBJECTS OF THE INVENTION In view of the above-mentioned drawbacks of the conventional art, the present invention provides a binary code generator capable of generating a plurality of binary codes generated at arbitrary timings with a simple configuration without increasing the number of circuit components. be.

Structure of the Invention A binary code generating device of the present invention comprises a memory that can be written to and read from at any time, an adder that adds an output signal read from a predetermined location of the memory and a predetermined first binary code, and an output of the adder. a determination circuit that determines whether the signal matches a predetermined second binary code; a flip-flop that is set by an external command signal and reset by an output signal of the determination circuit; Depending on the output signal, either the output signal of the adder or the third binary code is selected and output, and the selected one is written in a predetermined location of the memory.

With this configuration, the binary code that is to be a multiplier read from the address corresponding to a predetermined channel in the memory is added with a predetermined binary code value by an adder, and then written to the same address in the memory again, so that the binary code is read out from an address corresponding to a predetermined channel in the memory, and is then written to the same address in the memory again, so that the binary code is read out from an address corresponding to a predetermined channel in the memory. You can get binary code output. Furthermore, the generated binary code is configured such that it can be generated at independent timing for each channel by selecting the write signal to the memory using the output signal of the adder and a predetermined third binary code in channel time division. It is something.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 4 is a block diagram showing one embodiment of the present invention. To simplify the explanation, we assume that the generated binary code is 4 bits and the number of channels is 4, and that it is ``oooo''.
Let us take as an example the case where the value is changed from 1-ooolJtl''-0010J by ``Oo○1'' until it reaches ``1111''. In FIG. 4, 2 is a memory that can be written and read at any time (hereinafter referred to as RAM), and 3 is a RAM 2.
4 is a RAM for supplying address signals to
A latch for temporarily storing the read signal from 2, 6[
Adder, 6 is an addend generation circuit, 7 is a constant detection circuit, 8a,
8b, 80. sa is a flip-flop, 9 is a multiplexer, 10 is a data selector, and FIG. 5 is a timing waveform diagram of each part in FIG.
Each signal F'b to Ob corresponds to that in FIG.

The operation of the binary code generation system having the above configuration will be explained below. When all of the binary codes of the four channels do not require operation, that is, in the sections ■ and ■ shown in FIG. ”
level, indicating that it is not in operation. Therefore, the output signal B, which uses the multiplexer 9 to convert the output signals Ga-Gd into channel-corresponding time-division output signals, also maintains the L" level. Therefore, the data selector 10 controlled by the output signal H receives the 4 A predetermined binary code of the bits is selected.In this embodiment, the 4-bit binary code of "0o00" is selected at the terminal D.
Since it is input to SA, a 4-bit binary code of "0000" is also output to the output terminal DSY of the data selector 10. In the data selector output signal I in FIG. 5, this is simply expressed as 0''.The data selector output signal I is sequentially applied to addresses 0 to A3 corresponding to each channel of RAM2 at the rising edge of the write pulse J. written.

The written data is read out when the same address is supplied in the next cycle, and is written to latch 4 at the rising edge of latch pulse L. 0, that is, RAM 2 reads out the data that was written in the first half of 1 address and updates it in the second half. is configured to write data.

Since 1-ooooJ is always written to all channels in the sections (2) and (2), the data read out from the RAM 2 is also "000o". The output signal of the latch 4 is supplied to the outside as a binary code output signal (for example, the multiplier Y of the digital multiplier in FIG. 3), and is also input to one input terminal ADH of the adder 6. The input terminal AD has an addend generating circuit 6.
The 4-bit binary code AD given from is input. In this example, only the least significant bit is set to 1, and the other 3
l'-ooolJ with bit 0 is binary code AD
The 4-bit sum of the 4-bit binary codes input to the input terminals DB and AD is obtained at the 0 adder output ADY. That is, section 1. 'I
In I [ADA...... Ten Crossroads and 2222 ADY... 0001 ...'1"
"oool" is obtained as the output signal N at the output terminal ADY as shown in FIG. In FIG. 5, N is simply 1''. The adder output signal N is input to one input terminal DSB of the data selector and is also input to the constant detection circuit 7.

At the end of the constant detection output, it is determined whether the adder output signal N matches a predetermined binary code. Output signal line ζ ~
It is configured to output to Od. In this example, the predetermined binary code is 1-ooooJ
Then, the adder output N is always 1 in sections I and H.
Since it is Ooo1, no match is detected, therefore 01~O
All d's are L''.

Now, Fa to Fd, which are the start commands for binary code generation.
In this example, we will consider the case where there is a command input signal in F of these. The flip-flop 8b is set at the start slave Fb. Since the output signals Ga+ Go+ "d of the other flip-flops 8a, 8c, and sd remain at nL I+, the output signal H of the multiplexer outputted in channel time division is the output signal of channel b as shown in FIG. °H'' is output only in the section. Therefore, data selector 1o
selects the input signal H to the section input terminal DSB of channel b, and the output signal N1 of the adder 6, that is, "0001" in FIG.
”. is written. This written data is then read out from the RAM 10 when the address A1 is given again, once read into the latch 4, and then outputted as a binary code output M. At this time, the adder output NADB...0001...1"A
DA...Toshio 3 Mo and L... 1”A
DY...0010...'? 2
"... becomes the output signal N and is written to the same address 1 of the RAM 10 through the data selector 1o. In the same way, the binary code M is the address A. -A3 is incremented by 1" each time it goes around. . ) When the binary code M becomes "P15", that is, "1111", the adder output N is such that only the lower 4 bits of the adder are output ADB...1111...
...J511ADA...+)0001 ・
....."1" oooo ....."0" .....output signal H. Therefore, it becomes "ooOQ", and one of the constant detection outputs Oa to Od of the constant detection circuit 7 An output pulse is obtained on the corresponding channel ab, and its falling edge resets the flip-flop 8b. In the subsequent section (2), as in section I, "o" is always written in the RAM 2.

The above explanation has been given using channel b as an example, but similar operations are performed for channels a, c, and d on other channels, and the inari code that occurs in each channel is determined at the timing of any start command F1 to Fd. In addition, the addend AD generated by the addend generation circuit 6 is "oool" in this example, and the match detection code in the constant detection circuit 7 is set to 1-ooooj, but this can also be set arbitrarily. For example, if only the addend AD is "0010", °'0'
A binary code from "0" to 14I+ can be obtained in two steps at a time, and if only the coincidence detection code is I'1111, a binary code can be obtained from "O" to "14" in one step at a time.

As described above, according to this embodiment, the number of channels of the necessary binary code is made to correspond to the RAM address, and an arbitrary value is added to the read data of R^M and written to the same address again. (The inary code can be obtained without using a counter for each channel.Also, by controlling the write value for each channel address of RAM using a data selector using a flip-flop and a constant detection circuit corresponding to the channel) An inary code can be obtained at any timing, up to any value, and at any step. In this example, 4
Although the explanation has been given using a bit binary code as an example, it goes without saying that similar operations can be performed with any number of bits.

Effects of the Invention The present invention provides a randomly accessible memory, a read output signal from a predetermined location in the memory, and a predetermined first pie i.
+7 code; a determination circuit that determines whether the output signal of the adder matches a predetermined second binary code; A flip-flop is reset by the output signal, and one of the output signal of the adder and a predetermined third binary code is selected and output based on the output signal of the flip-flop, and written to a predetermined location of the memory. By doing so, it is possible to provide a binary code generator with a simple configuration and at low cost without proportionally increasing the number of elements required for the circuit configuration even when the number of required binary code channels increases. The effect is great.

[Brief explanation of the drawing]

Fig. 1 is a timing waveform diagram of the conventional binary code generator using a counter, Fig. 2 is a timing waveform diagram of the binary code generator using a counter in Fig. 1, Fig. 3 is a block diagram of the cross-fade circuit, and Fig. 4 6 is a block diagram of a binary code generator according to an embodiment of the present invention, and FIG. 6 is a timing waveform diagram based on the block diagram of FIG. 4. 2...RAM', 5...Adder, 7.
...Constant detection circuit, 8a to 8'd...Flip-flop. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 8 H6 → Figure 4

Claims (4)

[Claims] (1) A memory that can be written and read at any time, an adder that adds a read output signal from a predetermined location of the memory, and a predetermined first binary code, and an adder whose output signal from the adder is added to a predetermined second a determination circuit that determines whether or not the binary code of A binary code generating device characterized in that either one of the output signal of the adder and a predetermined third binary code is selected and outputted, and written in the predetermined location of the memory. (2) The binary code generator according to claim 1, wherein the first binary code is selectively changeable. (3) The binary code generator according to claim 1, wherein the second binary code is selectively changeable. (4) The binary code generator according to claim 1, wherein the third binary honor code is selectively changeable.