JPH04326542A - Burn-in equipment of integrated circuit - Google Patents

Burn-in equipment of integrated circuit

Info

Publication number
JPH04326542A
JPH04326542A JP3125041A JP12504191A JPH04326542A JP H04326542 A JPH04326542 A JP H04326542A JP 3125041 A JP3125041 A JP 3125041A JP 12504191 A JP12504191 A JP 12504191A JP H04326542 A JPH04326542 A JP H04326542A
Authority
JP
Japan
Prior art keywords
burn
pallet
lead
ics
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3125041A
Other languages
Japanese (ja)
Other versions
JP2758510B2 (en
Inventor
Ryoji Nishibashi
西橋 良二
Hidekazu Iwasaki
秀和 岩崎
Seiji Imanaka
今仲 清治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP3125041A priority Critical patent/JP2758510B2/en
Publication of JPH04326542A publication Critical patent/JPH04326542A/en
Application granted granted Critical
Publication of JP2758510B2 publication Critical patent/JP2758510B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Testing Of Individual Semiconductor Devices (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To omit a transferring work wherein an IC is taken out from an accommodation tool and mounted on a substrate for exclusive use, and enable the test in the state that the IC is contained in a pallet as the accommodation tool as it is, in the burn-in process of ICs. CONSTITUTION:An IC is accommodated in a pallet 2 and sandwiched by substrates 3 from above and below. Leads 1a of the IC 1 are pressed against contactors 3a of the lower substrate by a pressing members 3b of the upper substrate 3. The above state is realized in a high temperature vessel by using a pressing means or the like, and the burn-in test is enabled in the state that the IC is contained in the pellet as it is. The above purpose is attained and, at the same time, also the number of pallets accommodated in the high temperature vessel can be increased.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】この発明は、集積回路(以下IC
と呼ぶ)のバーンインテスト(高温槽内でICに通電し
、スクリーニングする試験)に使用されるバーンイン装
置に関するものである。
[Industrial Application Field] This invention relates to integrated circuits (hereinafter referred to as IC).
This relates to a burn-in device used in a burn-in test (a test in which ICs are energized and screened in a high-temperature chamber).

【0002】0002

【従来の技術】図8に従来のバーンイン装置を示す。図
において、11はICを加熱し、通電、テストするバー
ンイン炉、11aは炉内に設けられた基板ソケット、1
2はICを複数個搭載するバーンイン基板、13はバー
ンイン基板12を複数枚、決められたすき間をもって、
保持するキャリアである。図9は上記バーンイン基板1
2を示し、12aは基板12に設けられたICソケット
、12bはソケット12aの各ピンとプリント回路12
cにより接続されている基板コネクタ部分、1はIC、
14はIC1を収納するチューブ、2はIC1を収納す
るパレットである。
2. Description of the Related Art FIG. 8 shows a conventional burn-in device. In the figure, 11 is a burn-in furnace that heats, energizes, and tests the IC, 11a is a board socket provided in the furnace, and 1
2 is a burn-in board on which a plurality of ICs are mounted, 13 is a plurality of burn-in boards 12 with a predetermined gap,
It is a carrier to hold. FIG. 9 shows the burn-in board 1
2, 12a is an IC socket provided on the board 12, and 12b is each pin of the socket 12a and the printed circuit 12.
The board connector part connected by c, 1 is the IC,
14 is a tube that stores the IC1, and 2 is a pallet that stores the IC1.

【0003】次にこの装置を用いてバーンインテストを
行う手順について説明する。図9に示すように、IC1
をチューブ14からとり出して、基板12上のICソケ
ット12aへ装着する。ICが全て装着された基板12
を図8に示すキャリア13へ収納する。基板が全て収納
されたキャリア13をバーンイン炉11へ押し込み収納
する。この時基板12上のコネクタ部分12bは炉内の
基板ソケット11aに挿入され電気的に導通する。この
後、昇温、通電、テストが行なわれ、テスト完了後、キ
ャリア13が炉からとり出され、基板12上のIC1が
とり出されてチューブ14またはパレット2へ戻される
Next, a procedure for performing a burn-in test using this device will be explained. As shown in FIG. 9, IC1
is taken out from the tube 14 and attached to the IC socket 12a on the board 12. Board 12 with all ICs installed
is stored in the carrier 13 shown in FIG. The carrier 13 containing all the substrates is pushed into the burn-in furnace 11 and stored. At this time, the connector portion 12b on the board 12 is inserted into the board socket 11a in the furnace and electrically conductive. Thereafter, the temperature is raised, electricity is applied, and a test is performed. After the test is completed, the carrier 13 is taken out from the furnace, and the IC 1 on the substrate 12 is taken out and returned to the tube 14 or the pallet 2.

【0004】0004

【発明が解決しようとする課題】従来のバーンイン装置
は以上のように構成されているので、ICをこの工程の
ためだけにバーンイン基板へ挿入し、また基板から抜き
取るという作業が必要である。また、基板間にすき間を
設ける必要があるため、炉内に収納できるバーンイン基
板の枚数も制限されるという問題点があった。
Since the conventional burn-in apparatus is constructed as described above, it is necessary to insert the IC into the burn-in board and remove it from the board just for this process. Furthermore, since it is necessary to provide a gap between the substrates, there is a problem in that the number of burn-in substrates that can be stored in the furnace is also limited.

【0005】この発明は上記のような問題点を解消する
ためになされたもので、バーンイン工程後のICソケッ
トへの着脱作業を不要にするとともに、バーンイン炉内
の収納IC個数を増すことを目的とする。
[0005] This invention was made to solve the above-mentioned problems, and aims to eliminate the need for attaching and detaching ICs to IC sockets after the burn-in process, and to increase the number of ICs stored in the burn-in furnace. shall be.

【0006】[0006]

【課題を解決するための手段】この発明に係るバーンイ
ン装置は、ICを複数個搭載、収納した基板層、及びそ
れを収納し内部でテストを行う高温槽からなる。
[Means for Solving the Problems] A burn-in device according to the present invention comprises a substrate layer on which a plurality of ICs are mounted and housed, and a high-temperature bath where the substrate layer is housed and internally tested.

【0007】基板層はICを複数個位置決め搭載したパ
レットと、そのICのリード位置に対応した位置にコン
タクタを有し、且つリードをコンタクタに圧接する押え
具を設けた基板とからなり、上記パレットと基板が交互
に積み重ねられている。
The substrate layer consists of a pallet on which a plurality of ICs are positioned and mounted, and a substrate having a contactor at a position corresponding to the lead position of the IC and a presser for pressing the lead against the contactor. and boards are stacked alternately.

【0008】[0008]

【作用】この発明においては、パレット基板からなる基
板層を高温槽へ収納し、かつ槽内に設けられたプレスが
基板層を加圧する。この時パレットのICは一枚下の基
板に設けられたコンタクタへ押しつけられ、電気的に接
触する。こうして、ICを収納手段であるパレットから
とり出すことなくバーンインテストが行える。
[Operation] In the present invention, a substrate layer made of pallet substrates is stored in a high temperature bath, and a press provided in the bath pressurizes the substrate layer. At this time, the IC on the pallet is pressed against the contactor provided on the board one board below, and makes electrical contact. In this way, a burn-in test can be performed without removing the IC from the pallet that is the storage means.

【0009】[0009]

【実施例】【Example】

実施例1.以下、この発明の一実施例を図について説明
する。図1において、1はIC、2はICを収納するパ
レット、3はパレット2を上下からはさむ基板、3aは
ICリード1aに接触するコンタクタ、3bはICリー
ド1aを上からコンタクタ3aに押しつけるためのリー
ド押え具(以下押え具という)である。図2は上記パレ
ット2と基板3を複数組サンドイッチ状に積み重ねた基
板層4の全体図を示し、図3はパレット2の詳細図であ
り、2aはICを収納、位置決めするポケット、2bは
このポケット2aの側壁に沿う底部にあけられた穴で、
これはICのリード1aを下方のコンタクタ3aに接触
させるためのものである。図4は基板3の詳細図であり
、3aはICリードに接触させるためのコンタクタ、3
cは基板3の一端に設けられた外部コネクタへ接続する
ための電極、3dはコンタクタ3aと電極3cを電気的
に接続するプリント回路、3bは図1にも示すリード押
え具であり、コンタクタ3aの基板3の上面に、押え具
3bは基板3の下面に設けられている。図5において、
5は基板層4を収納する高温槽であり、図中には特に示
さない加熱、昇温手段の他に、基板層4を加圧するプレ
ス5a、上記基板3中の電極3cに接触するソケット5
bを有する。
Example 1. An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 1 is an IC, 2 is a pallet that stores the IC, 3 is a board that sandwiches the pallet 2 from above and below, 3a is a contactor that contacts the IC lead 1a, and 3b is a contactor for pressing the IC lead 1a from above onto the contactor 3a. This is a lead presser (hereinafter referred to as a presser). FIG. 2 shows an overall view of the board layer 4 in which multiple sets of the pallet 2 and the board 3 are stacked in a sandwich-like manner, and FIG. 3 is a detailed view of the pallet 2, in which 2a is a pocket for storing and positioning an IC, and 2b is a pocket for storing and positioning an IC. A hole drilled at the bottom along the side wall of pocket 2a,
This is for bringing the IC lead 1a into contact with the lower contactor 3a. FIG. 4 is a detailed view of the board 3, in which 3a is a contactor for contacting the IC lead;
3d is a printed circuit that electrically connects the contactor 3a and the electrode 3c; 3b is a lead holder shown in FIG. 1; The presser 3b is provided on the upper surface of the substrate 3, and the presser 3b is provided on the lower surface of the substrate 3. In Figure 5,
Reference numeral 5 denotes a high-temperature bath that houses the substrate layer 4, and in addition to heating and temperature raising means not particularly shown in the figure, a press 5a that presses the substrate layer 4, and a socket 5 that contacts the electrode 3c in the substrate 3.
It has b.

【0010】次に動作について説明する。図1に示すよ
うに、IC1を収納しているパレット2を上下から基板
3ではさむと、基板3上のコンタクタ3aは上にあるパ
レット2中のIC1のリード1aへ、図3に示したパレ
ット底面の穴2bを通して接触する。ここで全体を上か
ら加圧すると、リード1aは上にある基板3の下面に設
けられた押え具3bにより下方へ押され、図4に示すコ
ンタクタ3aに押しつけられる。図2に示す基板層4の
各パレット2内のIC1は全て以上のようにしてコンタ
クタ3a、プリント回路3dを通し、基板端の電極3c
と電気的に導通する。
Next, the operation will be explained. As shown in FIG. 1, when the pallet 2 containing the IC1 is sandwiched between the boards 3 from above and below, the contactor 3a on the board 3 connects to the lead 1a of the IC1 in the pallet 2 above, and the pallet 2 shown in FIG. Contact is made through hole 2b on the bottom. When the whole is pressurized from above, the lead 1a is pushed downward by the presser 3b provided on the lower surface of the upper substrate 3, and is pressed against the contactor 3a shown in FIG. 4. All the ICs 1 in each pallet 2 of the board layer 4 shown in FIG.
electrically conductive with.

【0011】次に上記基板層4を図5に示す高温槽5へ
収納し、プレス5aで上から加圧すると、前述のように
ICリードとコンタクタとの間の接触が確実になる。プ
レス完了後、各基板の電極3cを槽内のソケット5bと
接続し、バーンインテストを行なう。テスト終了後、ソ
ケット5bから電極3cを切り離し、プレスを解除し、
基板層4を高温槽5から取り出す。基板層4を解体して
も、IC1はパレット2上に収納されたままなので、そ
のまま次工程へ搬送、投入できる。
Next, the substrate layer 4 is placed in a high-temperature bath 5 shown in FIG. 5, and pressurized from above with a press 5a, thereby ensuring the contact between the IC leads and the contactors as described above. After pressing is completed, the electrode 3c of each substrate is connected to the socket 5b in the tank, and a burn-in test is performed. After the test, disconnect the electrode 3c from the socket 5b, release the press,
The substrate layer 4 is taken out from the high temperature bath 5. Even if the substrate layer 4 is disassembled, the IC 1 remains stored on the pallet 2, so it can be transported and put into the next process as it is.

【0012】実施例2.なお上記実施例では、加圧する
機構を高温槽内に設けたが、図6に示すように高温槽へ
投入前にあらかじめ基板層をネジ等で圧縮、固定してお
いてもよい。
Example 2. In the above embodiment, a pressurizing mechanism is provided in the high temperature bath, but as shown in FIG. 6, the substrate layer may be compressed and fixed with screws or the like before being put into the high temperature bath.

【0013】実施例3.上記実施例では、ICがパレッ
トに収納された例を示したが、ICが位置決めされてお
り、リード部分が上下方向から接触できる形態であれば
同様の手段が適用できる。図7に示すICフレームでも
よい。
Example 3. In the above embodiment, an example was shown in which the IC was housed in a pallet, but similar means can be applied as long as the IC is positioned and the lead portion can be contacted from above and below. An IC frame shown in FIG. 7 may be used.

【0014】実施例4.また、基板下面に設けた押え具
に弾性体を使用してICリードに対してダメージを少な
くすることも可能である。さらに押え具自体を電極にし
てICリードを上下両方からコンタクトして、より良好
な電気的導通を得ることも可能である。
Example 4. Furthermore, it is also possible to reduce damage to the IC leads by using an elastic body as a presser provided on the bottom surface of the substrate. Furthermore, it is also possible to obtain better electrical continuity by using the presser itself as an electrode and contacting the IC lead from both the upper and lower sides.

【0015】[0015]

【発明の効果】以上のように、この発明によればバーン
インを行なう場合、ICをパレット等の治具からバーン
イン基板へ移し替える膨大な作業を省略でき、また高温
槽へ収納できるICの個数もパレット間々隔を基板厚み
程度まで圧縮できるので、従来と比べ大幅に多くでき、
作業能率を向上させることができる。
[Effects of the Invention] As described above, according to the present invention, when performing burn-in, the enormous work of transferring ICs from a jig such as a pallet to a burn-in board can be omitted, and the number of ICs that can be stored in a high-temperature bath can be reduced. Since the spacing between pallets can be compressed to the same level as the board thickness, it is possible to significantly increase the number of pallets compared to conventional methods.
Work efficiency can be improved.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】この発明の実施例1の要部を示す断面図。FIG. 1 is a sectional view showing essential parts of a first embodiment of the invention.

【図2】図1の外観斜視図。FIG. 2 is an external perspective view of FIG. 1.

【図3】パレットの斜視図。FIG. 3 is a perspective view of a pallet.

【図4】基板の斜視図。FIG. 4 is a perspective view of the substrate.

【図5】この発明の実施例1を示す高温槽の断面図。FIG. 5 is a sectional view of a high temperature bath showing Example 1 of the present invention.

【図6】この発明の実施例2を示す基板層の斜視図。FIG. 6 is a perspective view of a substrate layer showing Example 2 of the present invention.

【図7】この発明の実施例3を示すICフレームの平面
図。
FIG. 7 is a plan view of an IC frame showing a third embodiment of the invention.

【図8】従来のバーンイン装置を示す斜視図。FIG. 8 is a perspective view showing a conventional burn-in device.

【図9】従来のバーンイン基板を示す斜視図。FIG. 9 is a perspective view showing a conventional burn-in board.

【符号の説明】[Explanation of symbols]

1    IC 1a  ICのリード 2    パレット 2a  ポケット 2b  穴 3    基板 3a  コンタクタ 3b  押え具 3c  電極 3d  プリント回路 4    基板層 5    高温槽 5a  プレス 5b  ソケット 1 IC 1a IC lead 2 Palette 2a Pocket 2b hole 3     Substrate 3a Contactor 3b Presser 3c Electrode 3d printed circuit 4 Substrate layer 5 High temperature bath 5a Press 5b socket

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】  複数個のICを搭載、収納した基板層
と、この基板層を収容し、内部でテストを行う高温槽か
らなるICのバーンイン装置において、ICを収納する
ポケットのICリードに対応する底部に穴を設けたパレ
ットと、上面には上記ICリードに対応するコンタクタ
を、下面には上記ICリードに対応するリード押え具を
、さらに端面には上記コンタクタとプリント回路により
接続した電極をそれぞれ設けた基板とを備え、上記パレ
ットを上下より上記基板ではさんで基板層を形成したこ
とを特徴とする集積回路のバーンイン装置。
[Claim 1] In an IC burn-in device consisting of a board layer on which a plurality of ICs are mounted and housed, and a high-temperature tank that houses the board layer and performs internal testing, it corresponds to the IC leads of the pocket that houses the ICs. A pallet with a hole in the bottom, a contactor corresponding to the above IC lead on the top surface, a lead holder corresponding to the above IC lead on the bottom surface, and an electrode connected to the above contactor by a printed circuit on the end surface. 1. A burn-in device for an integrated circuit, characterized in that the pallet is sandwiched between the substrates from above and below to form a substrate layer.
【請求項2】  複数個のICを搭載、収納した基板層
と、この基板層を収容し、内部でテストを行う高温槽か
らなるICのバーンイン装置において、複数個のICを
連接しているICフレームと、上面にはICのリードに
対応するコンタクタを、下面にはICのリードに対応す
るリード押え具を、さらに端面には上記コンタクタとプ
リント回路により接続した電極をそれぞれ設けた基板と
を備え、上記ICフレームを上下より上記基板ではさん
で基板層を形成したことを特徴とする集積回路のバーン
イン装置。
[Claim 2] An IC burn-in device comprising a substrate layer on which a plurality of ICs are mounted and housed, and a high-temperature chamber that houses the substrate layer and performs internal tests, in which a plurality of ICs are connected together. It is equipped with a frame, a substrate having a contactor corresponding to the IC lead on the upper surface, a lead holding device corresponding to the IC lead on the lower surface, and an electrode connected to the contactor by a printed circuit on the end surface. . A burn-in device for an integrated circuit, characterized in that a substrate layer is formed by sandwiching the IC frame between the substrates from above and below.
JP3125041A 1991-04-25 1991-04-25 Integrated circuit burn-in device Expired - Fee Related JP2758510B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3125041A JP2758510B2 (en) 1991-04-25 1991-04-25 Integrated circuit burn-in device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3125041A JP2758510B2 (en) 1991-04-25 1991-04-25 Integrated circuit burn-in device

Publications (2)

Publication Number Publication Date
JPH04326542A true JPH04326542A (en) 1992-11-16
JP2758510B2 JP2758510B2 (en) 1998-05-28

Family

ID=14900378

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3125041A Expired - Fee Related JP2758510B2 (en) 1991-04-25 1991-04-25 Integrated circuit burn-in device

Country Status (1)

Country Link
JP (1) JP2758510B2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0350846A (en) * 1989-07-19 1991-03-05 Fujitsu Miyagi Eretokuronikusu:Kk Burn-in apparatus of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0350846A (en) * 1989-07-19 1991-03-05 Fujitsu Miyagi Eretokuronikusu:Kk Burn-in apparatus of semiconductor device

Also Published As

Publication number Publication date
JP2758510B2 (en) 1998-05-28

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