JPH0432591B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video signal dividing circuit that divides an input video signal into signals of multiple channels. The present invention relates to a video signal dividing circuit that converts a high-speed data signal obtained by sampling a signal into a low-speed data signal of multiple channels and outputs the same.

[Background technology and its problems]

2. Description of the Related Art It has been known to digitally perform various types of signal processing on video signals, such as noise reduction processing and enhancement processing. For example, when performing digital signal processing on a standard television video signal such as the NTSC system, the frequency band is approximately 4 MHz, and the sampling clock frequency may be approximately 10 MHz. is possible.

By the way, in recent years, for example, the number of scanning lines has increased.
1125 high resolution (high quality or high definition)
As video systems continue to develop, it is becoming necessary to digitally process such high resolution video signals. The frequency band of this high-resolution video signal is wide, for example, about 25M to 30MHz, and the sampling clock frequency when digitizing it reaches, for example, about 70M to 80MHz, so it is necessary to process the signal using standard TTL. is almost impossible. Therefore, ECL (Emitsuta Katsupurudo)
Also called logic or CML. ) and other high-speed elements, and converting sampled high-speed data signals to low-speed signals and digitally processing them using TTL and the like are being considered.

First, when using high-speed elements such as ECL,
Although they have the advantage of being able to directly digitally process high-speed sampling data signals, high-speed elements such as ECLs are generally expensive and have the disadvantage that they consume a lot of power, which generates a large amount of heat and makes heat dissipation processing difficult. In addition, ROM is used during signal processing.
(read-only memory) and RAM (random access memory) are often used, and since these memories are often slow and TTL interface type, it is difficult to interface with high-speed elements such as ECL. be.

Therefore, it has been proposed to convert a high-speed data signal obtained by sampling a wideband video signal such as the above-mentioned high-resolution video signal into a low-speed data signal, and perform signal processing using ordinary TTL or the like. In this case, it is possible to use a conventional standard system (for example, NTSC system) video signal processing circuit almost as is, and it is easy to interface with a memory or the like.

By the way, when converting a high-speed sampling data signal such as a high-resolution video signal into a low-speed signal, generally, serial-to-parallel conversion is used to perform parallel conversion every N pieces of input serial sampling data. The data is N channel (or N phase) data and the clock is reduced to 1/N. However, according to such serial-to-parallel conversion for every N data, the data of N channels obtained in parallel becomes discontinuous within each channel, that is, the data within one channel is the same as the original sampling. This method has the drawback that the data is extracted every N pieces, and the signal processing becomes complicated even at the subsequent stage. This is because data of pixels that are continuous in the horizontal or vertical direction on the screen is often used in general two-dimensional image processing, such as noise removal or dropout compensation. Alternatively, since the data of a series of pixels are not in the same channel, data must be exchanged between each channel, which complicates the processing.

[Purpose of the invention]

In view of these conventional circumstances, the present invention divides high-speed sampling data of a wideband video signal into N channels and converts it into N-channel low-speed data with a clock frequency of 1/N, thereby using high-speed elements such as ECL. Not only does it enable signal processing using normal TTL, etc., without the need for data transfer, but image processing after conversion can be easily processed almost independently for each channel without exchanging data between channels. The purpose of this invention is to provide a video signal splitting circuit with

[Summary of the invention]

That is, the feature of the video signal dividing circuit according to the present invention is that the video signal dividing circuit divides an input video signal into N channels (N is an integer of 2 or more) to produce N-channel signals. a write address control circuit that controls the write address according to the clock signal; a memory circuit that is write-controlled by the write address control circuit and into which the input video signal is written; and a memory circuit that controls the read address according to the clock signal and writes the input video signal into the memory circuit. a readout address control circuit for sequentially reading signals from the beginning of each of the divided portions obtained by dividing a unit time of the input video signal into N; N latch circuits sequentially latch the signals read out from the memory circuit by N touch pulses whose phases are sequentially shifted by the signal period, and the outputs from these N latch circuits are connected to N channels. This is to extract it as a divided signal.

〔Example〕

First, before explaining specific examples of the present invention, the basic operation of the video signal dividing circuit of the present invention will be explained with reference to the drawings.

FIG. 1 shows a screen S displayed using, for example, a high-resolution (high-definition or high-definition) video signal, and on this screen S, each horizontal line is equally divided into a plurality of parts, for example, four parts. Thus, so-called vertically divided screen blocks A, B, C, and D are formed. The video signal dividing circuit of the present invention divides and extracts, for example, four channels of video signals corresponding to each of the screen blocks A, B, C, and D from the original video signal for displaying the entire screen S. Perform the action. For example, as shown in Figure 2, this is for 1H (1 horizontal period) of the original video signal VS.
is divided into four equal parts, A, B, C, D, and the time axis is expanded to create four channels ChA, ChB,
You can divide them into ChC and ChD respectively. In the video signal VS of FIG. 2, for example, for the signal for 1H from time t ₁ to time t ₅ , from time t ₁ to
The signal between H/4 corresponding to the above block A up to t ₂ is time-axis extended (expanded by 4 times) to the range of 1H from time t ₁ to t ₅ and distributed to channel ChA, and then t ₂
The signal from t ₃ to t 3 is time-extended from t ₂ to t ₆ and distributed to channel ChB, and the signal from t ₃ to _{t 4} is extended from t 3 to t ₆ .
Extend the time axis to t ₇ , distribute to channel ChC, and t ₄
Stretch the time axis of the signal at ~t ₅ to t ₄ ~ t ₈ and channel it
Allocated to ChD.

By the way, in the case of the signal distribution form as shown in Fig. 2, each channel ChA, ChB, ChC, ChD
The connection points of the time-axis expanded signals are shifted by H/4, such as times t ₁ , t ₂ , t ₃ , and t ₄ .
In order to match the signal connection points of these channels in time and distribute them so that they match the H synchronization signal of the original video signal, for example, signal delay and time axis expansion as shown in Figure 3 are necessary. Just let it happen.

In other words, in Fig. 3, the original video signal VS
Each of the above blocks A, B, C, which divided 1H into four equal parts,
Among the parts corresponding to D, block A
The signal part of H/4 corresponding to block B is delayed by 1H and the time axis is expanded by 4 times, and the part corresponding to block B is delayed by 3/4H and block C.
The corresponding part is delayed by H/2, and the part corresponding to block D is delayed by H/4, and the time axis is expanded and each channel ChA, ChB, ChC,
Allocated to each ChD. Therefore, for each signal portion of the video signal VS, for example, divided into 4 equal parts for 1H from time t ₁ to t ₅ , the H/4 period from time t ₁ to t ₂ corresponding to block A is a channel.
It is placed at a position between 1H from time t ₅ to t ₉ in ChA, and also includes a portion corresponding to block B t ₂ to t ₃ , a portion corresponding to block C t ₃ to t ₄ , and a portion corresponding to block D t ₄ to _{t 5} too,
Time t ₅ of each channel ChB, ChC, ChD, respectively
Placed between 1H and _t9 .

By the way, in general, when performing two-dimensional image processing, as mentioned above, data that is continuous in the horizontal direction or data that is continuous in the vertical direction on the screen is often used, but the video signal dividing circuit of the present invention can divide the data. The signals of each channel correspond to, for example, each screen block A, B, C, and D in FIG. 1, so the above image processing can be easily performed using the data in each one channel. .

However, since horizontally adjacent data may be distributed to other channels at the boundaries between screen blocks A, B, C, and D,
It is preferable that data near this boundary portion be distributed to each channel in duplicate or in an overlapping manner.

FIG. 4 shows each block A, B,
Channels ChA, ChB, ChC, and ChD are arranged so that data near the boundary between C and D overlaps.
An example of allocating to In this Figure 4, the effective display area that is actually displayed on the screen is divided into four equal parts out of 1H of the original video signal VS, and the range obtained by adding ΔT before and after each of these divided parts is calculated. The data is expanded on the time axis and distributed to each channel ChA, ChB, ChC, and ChD. That is, when the effective display area is from time t ₁₂ to t ₁₆ during the 1H period from time t ₁₁ to t ₁₇ in FIG. 4, the time T from t ₁₂ to t ₁₆ is divided into four equal parts and ₁₃ , t ₁₄ , and t ₁₅ , respectively. Then, regarding _the video signal VS, ΔT before time _t12 and _time
T/4+ obtained by adding ΔT after t ₁₃
The time axis of the signal VS-A in the time period of 2ΔT is extended by four times, and the signal is distributed to the channel ChA. Similarly, for the portions _t13 to _t14 , _t14 to _t15 , and _t15 to _t16 corresponding to other screen blocks B, C, and D, respectively, only ΔT was added to the front and rear of each portion. Time domain signals VS-B, VS-C, and VS-D
is extended on the time axis and distributed to each channel ChB, ChC, and ChD. In this case, T/4+
If 2ΔT is H/4 or less (T/4+2ΔT≦H/4), the signals obtained by expanding the time axis of each signal VS-A to VS-D by 4 times will fit within 1H, and the signals of each channel will be processed without signal loss. is obtained.

In addition, these partial signals VS-A to VS-D
The signal obtained by expanding the time axis may be placed, for example, at a position between the next 1H of each channel ChA to ChD, as explained with reference to FIG.

Next, an embodiment of a circuit according to the present invention for performing such video signal division will be described with reference to FIG.

In FIG. 5, an input terminal 1 receives, for example, a digital video signal having a sampling clock frequency of about 80 MHz. This input signal corresponds to a digitally converted wideband video signal, such as the aforementioned high-resolution video signal, whose frequency band reaches approximately 30 MHz. This input digital video signal is stored in a RAM having a storage capacity of at least 2 horizontal periods (2H, 2 lines).
(random access memory), etc., is sent to the memory circuit 2. This memory circuit 2 is write-controlled by a write address control circuit 3, and read-out is controlled by a read address control circuit 4. Each of these address control circuits 3 and 4 is supplied with a write clock signal and a read clock signal from a clock signal generation circuit 5, respectively. A sampling clock signal (approximately 80 MHz) of the input digital video signal is supplied to the clock signal generating circuit 5 via an input terminal 6, for example, and based on this sampling clock signal, the writing and the writing of the same frequency are performed. Outputs read clock signal.

Next, the digital video signal read from the memory circuit 2 is divided into multiple latch circuits 7A, 7B, 7C,
7D, and these four latch circuits 7
The latch outputs from A, 7B, 7C, and 7D are taken out from output terminals 9A, 9B, 9C, and 9D via latch circuits 8A, 8B, 8C, and 8D, respectively. Each latch circuit 7A to 7D, 8A to 8D
are operated by the latch pulses LP1 to LP5 from the latch timing pulse generation circuit 10, and the latch circuits 7A to 7D are operated by the latch pulses LP1 to LP4 at different timings (different phases) from each other.
The input signals of the latch circuits 8A to 8D are latched (captured) by the latch pulse LP5 at the same timing.

Here, the memory circuit 2 by each control circuit 3, 4
Writing and reading control may be performed by dividing 1H of the high-speed digital video signal VS supplied to input terminal 1 into four parts, and outputting each divided part sequentially from the temporally first data. , for example, as shown in Figure 3, the original video signal
When data written during 1H of VS (for example, between t ₁ and _{t 5} ) is read out while expanding the time axis during the next 1H (for example, between t ₅ and t ₉ ) and distributed to each channel, the memory circuit As shown in FIG. 6, the line memory 2 may be constructed of two line memories 2a and 2b, and the changeover switches 12 and 13 may be used to alternately switch one for writing and the other for reading.

That is, the input terminal 11 in FIG. 6 is supplied with the data of the digital video signal from the input terminal 1 in FIG. , 2b and written. When one of the line memories 2a and 2b is in a writing state, the other is in a reading state, and the read data is taken out from the output terminal 14 via the changeover switch 13, and each latch circuit 7 shown in FIG.
They are sent to A, 7B, 7C, and 7D, respectively. That is, the selected terminals a and b of each of the changeover switches 12 and 13 are switched and connected in a mutually complementary manner every 1H,
For example, in the state shown in FIG. 6, the switch 12 is connected to the selected terminal a, and the switch 13 is connected to the selected terminal b.

By the way, as data from the output terminal 14, each block A of data written 1H ago,
It is only necessary that the parts corresponding to B, C, and D are sequentially and cyclically output from the respective leading positions. This means, for example, that 1H worth of data from time t ₁ to t ₅ in the video signal VS in FIG.
2000 words of line memory address 0 to 1999
When the data corresponding to each block A, B, C, and D are sequentially written up to
Written to addresses 1499 and 1500 to 1999. Then, during the next 1H (time t ₅ to t ₉ ), the read address is set to 0, 500, 1000, 1500, 1501,
1001, 1501, . . . , each block is scanned cyclically from the first address of each block and read out in time order. The frequency of the read clock CKR at this time is equal to the sampling clock frequency of the original input digital video signal (for example, approximately 80 MHz), and the data at address X (X = 0, 1, 2, ..., 1999) of the line memory is Dx, and the block Y to which it belongs (Y
= A, B, C, D) as Dx (Y), the read clock
Data D ₀ (A), D ₅₀₀ (B), D ₁₀₀₀ according to CKR
(C), D ₁₅₀₀ (D), . . . are sequentially read out. Here, each latch circuit 7A, 7B, 7C, 7 in FIG.
Latch pulses LP1 and LP supplied to D respectively
2, LP3, LP4, as shown in Figure 7,
If a clock with a frequency 1/4 (four times the period) of the clock CKR and a phase difference sequentially shifted by one period of the clock CKR is used, the latch circuit 7
For example, the latch circuits 7B, 7C, and 7D can be configured to sequentially take in only the data belonging to block A, and similarly, the latch circuits 7B, 7C, and 7D can take in only the data belonging to blocks B, C, and D, respectively. Furthermore, latch circuits 8A, 8B, 8C, 8D
, a latch pulse with a frequency of 1/4 of the clock CKR
By supplying LP5 in common, the phases of each channel can be matched.

Therefore, each latch circuit 8A, 8B, 8C, 8D
The channels ChA, ChB, which are taken out through the output terminals 9A, 9B, 9C, and 9D, respectively.
The ChC and ChD data signals each have a frequency (approximately 20MHz) that is 1/4 of the sampling clock frequency of the original input digital video signal, and correspond to screen blocks A, B, C, and D in Figure 1, respectively. This is the data that will be used.

By the way, in the above explanation, the write address is controlled to simply increase from 0 to 1999, and the read address is controlled to increase from 0, 500, 1000, 1500, etc.
Although the control is such that each block is designated cyclically as 1, 501, 1001, 1501, . . . , address control may be performed such that the address is distributed to each block when input data is written. For example, when 2000 pieces of sampling data for one line of an input digital video signal are input sequentially, the write address is set to 0,
4, 8,…, 1996, 1, 5, 9,…, 1997, 2,
6, 10, . . . , 1998, 3, 7, 11, . . . , 1999, and the read address can be simply increased from 0 to 1999. The output data at this time is D ₀
(A), D ₁ (B), D ₂ (C), D ₃ (D), D ₄ (A), D ₅
(B), D ₆ (C), D ₇ (D), etc., the items belonging to each block A, B, C, and D are displayed cyclically,
Similarly to the above explanation, latch circuits 7A to 7D, 8A to
Data signals of each channel ChA to ChD are taken out by 8D.

Next, as explained in conjunction with FIG.
An example of address control when allocating to the following will be explained.

First, 1H in the input digital video signal VS
2000 pieces of data within the effective display area, and 2000 pieces of data within the effective display area within
When the number of display areas is 10, data of T+2ΔT for the effective display area and ΔT before and after it are sequentially written to addresses from 0 to 2019 of the 2020-word line memory. At this time, each screen block A,
500 each on one line corresponding to B, C, D
The data is from line memory address 10 to 509,
Written in 510-1009, 1010-1509, and 1510-2009, respectively. Write address is from 0 to 2019
However, the address becomes 0 at a time ΔT before time t ₁₂ in FIG. 4, and the address becomes 2019 at a time ΔT after time t ₁₆ . Then, when reading, the address is 0, 500, 1000, 1500, 1, 501, 1001, 1501, etc.
However, 520 words are read for each channel during 1H, and near the end of 1H, the read address is..., 519,
It reaches 1019, 1519, 2019. The channel Z to which the data Dx (Y) read at this time belongs is Dx
When expressed as (Y-Z), D ₀ (Δ-A), D ₅₀₀
(A-B), D ₁₀₀₀ (B-C), D ₁₅₀₀ (C-D),...,
D ₅₁₉ (B-A), D ₁₀₁₉ (C-B), D ₁₅₁₉ (D-C),
It will be read out in the order of D ₂₀₁₉ (Δ-D).
Here, the block Y to which arbitrary data Dx(Y-Z) belongs is Δ, which corresponds to the portions ΔT before and after the effective display area in FIG. 4, respectively. Note that among the read data, the belonging block Y
The one that matches the belonging block Z is D ₁₀ (A
-A), D ₅₁₀ (B-B), D ₁₀₁₀ (C-C), D ₁₅₁₀ (D
-D),...,D ₅₀₉ (A-A), D ₁₀₀₉ (B-B), D ₁₅₀₉
(CC), D ₂₀₀₉ (DD).

The data thus read out can be taken out for each channel by latch circuits 7A-7D and 8A-8D, as described above.

According to such an embodiment of the present invention, for example, the memory capacity for two lines (2H minutes) is small.
Since high-speed data of an 80 MHz clock can be converted into low-speed data of, for example, 4 channels (for example, a 20 MHz clock), it is possible to perform image processing using ordinary TTL, etc., without using high-speed elements such as ECL. In addition, since the data divided into these channels corresponds to each screen block equally divided in the line direction on the screen, two-dimensional image processing can be easily performed using only the data in each channel. Ru. In this case, discontinuities at dividing points in the line direction, that is, at the boundaries of each screen block, can be resolved by overlapping the areas near these boundaries and including them in each channel, allowing image processing using a series of data in the horizontal direction. This can only be done using data within the same channel. Furthermore, the overall phase (timing of the leading position) of the data of each divided channel and the clock phase can be aligned, and only approximately one type of control signal is required for data processing after division. becomes easier.

Note that the present invention is not limited to the above-mentioned embodiments, and in the embodiments, an example in which an input video signal is divided into four channels has been described, but in general, N channels are divided into four channels.
Division into channels (N is an integer of 2 or more) can also be easily realized. Further, in the embodiment, 1H is divided into N parts, but other time units may be divided into N parts. Further, each signal divided into N channels does not need to be used for two-dimensional image processing, and may be supplied to other signal processing, a recording system, a signal transmission system, etc.

[Effects of the Invention] According to the video signal dividing circuit according to the present invention, a high-speed clock input video signal can be divided into multiple channels of low-speed clock signals, and the signals in each divided channel are determined based on their relationship on the screen. The signal processing speed is high, and various signal processing, especially image processing, can be easily performed independently for each channel.

[Brief explanation of drawings]

Figure 1 is a plan view showing a screen displayed by a video signal, Figures 2 and 3 are timing charts for explaining different examples of video signal division operations, and Figure 4 is a diagram of the video signal division operation. 5 is a block circuit diagram showing one embodiment of the present invention; FIG. 6 is a block circuit diagram showing a specific example of the memory circuit of FIG. 5; and FIG. 7 is a timing chart for explaining another example. This figure is a timing chart for explaining the operation of each latch circuit in FIG. 1...Video signal input terminal, 2...Memory circuit,
3...Write address control circuit, 4...Read address control circuit, 5...Clock signal generation circuit, 6...Timing pulse generation circuit, 7A-7
D, 8A~8D...Latch circuit, 9A~9D...
Signal output terminal.

Claims (1)

[Claims] 1 Divide the input video signal into N (N is an integer of 2 or more)
In the video signal dividing circuit that converts the input video signal into an N-channel signal, there is a write address control circuit that controls a write address according to a clock signal of the input video signal, and a write address control circuit that controls the write address so that the input video signal is written. control a read address in accordance with the clock signal, and read out cyclically and sequentially from the first signal of each divided portion obtained by dividing the unit time portion of the input video signal written in the memory circuit into N parts. a read address control circuit;
N latch circuits that sequentially latch signals read from the memory circuit using N latch pulses having a frequency of 1/N of the clock signal frequency and whose phases are sequentially shifted by the period of the clock signal; A video signal dividing circuit characterized in that the outputs from these N latch circuits are extracted as divided signals of N channels.