JPS6031378A - Video signal dividing circuit - Google Patents

Abstract

PURPOSE:To attain a signal processing by a TTL or the like by dividing the high speed sampling data of a broad band video signal into N so as to convert the data into an N-channel low speed data where a clock frequency is 1/N. CONSTITUTION:A video signal having, e.g., the clock frequency of 80MHz is fed to a memory circuit 2 having the storage capacity of 2 horizontal periods from an input terminal 1. This video signal is fed by latch circuits having a channel number to be divided, e.g., 4 sets. Each latch pulse, the pulses LP1-LP5 have a frequency being 1/4 of that of a clock C and the relation of phase as shown in Fig. The input signal is latched in the latch circuit 7 by using the pulses LP1- LP4 and in the latch circuit 8 by using the pulse LP5. The memory circuit 2 consists of line memories 2a, 2b so as to switch alternately the write/read by changeover switches 12, 13. The terminals a, b to be selected of the switches 12, 13 are interlocked at each 1H in the complementary relation and switched. Thus, an output which is divided into four, at low speed and whose phase is coincident with the latch pulse LP5 is obtained from each output terminal 9.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video signal dividing circuit that divides an input video signal into signals of multiple channels. The present invention relates to a video signal dividing circuit that converts a high-speed data signal obtained by sampling signals into a plurality of channels of low-speed data signals and outputs the same.

[Background technology and its problems]

2. Description of the Related Art It is conventionally known to digitally perform various types of signal processing on video signals, such as noise reduction processing and processing/hanos processing. For example, when performing digital signal processing on a standard television video signal such as the NTSC system, the frequency band is approximately 4 MHz, and the sampling clock frequency is approximately 10 MHz. Signal processing is possible.

Incidentally, in recent years, the development of high-resolution (high-definition or high-definition) video systems with, for example, 1125 scanning lines has progressed, and it has become necessary to perform digital signal processing on such high-resolution video signals. . The frequency band of this high resolution video signal is, for example, 25M to 3Q.
The frequency range is as wide as MHz (and the assembly/clock frequency when digitizing this signal reaches, for example, 70 to 80 MHz, making it almost impossible to process the signal using standard TTL. Consideration has been given to using high-speed elements such as emitter-coupled logic (also referred to as CML), or converting sampled high-speed data signals to low-speed signals and digitally processing them using TTL or the like.

First, when using a high-speed element such as an ECL, although it has the advantage of being able to directly digitally process a high-speed sampling data signal, a high-speed element such as an ECL is generally expensive and consumes a lot of power, so it generates heat. It has the disadvantage that heat dissipation is difficult due to the large amount of heat dissipation.Furthermore, ROM (read only memory) and RAM (
Random access memory) is often used (and these memories are often slow and TTL interface type, making it difficult to interface with high-speed devices such as ECL).

Therefore, it has been proposed to convert a high-speed data signal obtained by sampling a wideband video signal such as the above-mentioned high-resolution video signal into a low-speed data signal, and to perform signal processing using ordinary TTL or the like. In this case, it is possible to use a conventional standard system (for example, NTSC system) video signal processing circuit almost as is, and it is easy to interface with a memory or the like.

By the way, when converting a high-speed sampling data signal such as a high-resolution video signal into a low-speed signal,
In general, serial-to-parallel conversion is performed by converting every N pieces of input serial Samblinob data into parallel data to obtain N channel (or N phase) data, and lowering the clock to 1H. There is. However, according to this strict serial-to-parallel conversion for every N data, the N channels of data obtained in parallel are discontinuous within each channel, that is, the data within one channel is San, bu 1 nong data N
The disadvantage is that the signal processing at the subsequent stage becomes complicated if the signals are extracted every other time.

In general two-dimensional image processing, such as noise removal and dropout compensation, data of pixels that are continuous in the horizontal or vertical direction on the screen is often used (such as when adjacent pixels on the screen are This is because data for a set of pixels or a series of pixels are not in the same channel, so it is necessary to change the data between channels, which complicates the processing.

[Purpose of the invention]

In view of such conventional circumstances, the present invention divides high-speed sampling data of a wideband video signal into N channels and converts it into N-channel low-speed data with a clock frequency of 1H, thereby using high-speed elements such as EOL. Normal TTL
In addition to making it possible to perform signal processing using methods such as The purpose is to provide a video signal division circuit.

[Summary of the invention]

That is, the feature of the video signal dividing circuit according to the present invention is that the video signal dividing circuit divides an input video signal into N (N is an integer of 2 or more) to produce N-channel signals. a write address control circuit that controls the write address according to the clock signal; a memory circuit that is write-controlled by the write address control circuit and into which the input video signal is written; a read address control circuit that sequentially reads out the first signal of each divided portion obtained by dividing the unit time of the input video signal into and N launch circuits that sequentially latch the signals read from the memory circuit using N latch pulses whose phases are sequentially shifted by the period of the clock signal, and these N latch circuits. The purpose of this is to extract the output from the N-channel signal as divided signals of N channels.

〔Example〕

First, prior to a detailed explanation of the present invention, the basic operation of the video signal dividing circuit of the present invention will be explained with reference to the drawings.

Figure 1 shows, for example, high resolution (high quality or high definition)
The figure shows a screen S that is reversely displayed using a video signal, and on this screen S, each horizontal line is equally divided into a plurality of blocks, for example, four blocks, so-called vertically divided screen blocks A,
B, C, and D are formed. The video signal dividing circuit of the present invention divides and handles the original video signal for displaying the entire screen S, for example, the four-channel video signal corresponding to each of the screen blocks A, B', C, and D. Perform an action that brings out the sound. For example, as shown in Figure 2, 18 intervals (one horizontal period) of the original video signal
Three channels ChA, ChB, ChC.

It is sufficient to allocate them to each ChD. In the video signal vS of FIG. 2, for example, for the 18 signals from time t to time t, the signal from time 1 to 4 corresponding to block A from time t1 to t2 is used as the signal from time 1 to time t2. from t5
The time axis is expanded (expanded by 4 times) to the IH range up to
From t6''!, the time axis is extended to channel 7 Ch'H
The signal from t3 to t4 is time-extended to t3 to t7 and distributed to channel ChC, and the signal from t4 to t5 is distributed to channel ChC.
The time axis is expanded from 4 to t8 and distributed to channel ChD.

By the way, in the case of the signal distribution form as shown in FIG. 2, each channel C11A, ChB, ChC.

The connection points of the time-axis expanded signals of Cb D are I(/4
They are off by one. In order to match the signal connection points of these channels in time and distribute them so that they match the H synchronization signal of the original video signal, signal delay and time axis expansion as shown in Figure 3 are required, for example. Just let it happen.

That is, in FIG. 3, the blocks A, B, and C are divided into four equal parts of 18 of the original video signal vS.

Among the parts corresponding to D, all the signal parts corresponding to block A are delayed by IH and expanded by 4 times the time axis, and the part corresponding to block B is 3'H, which corresponds to block C. Regarding the part,
Regarding the part corresponding to block D, the block D is delayed and the time axis is expanded, and each channel ChA, ChB is
, ChC, and ChD, respectively. Therefore, for each signal portion obtained by equally dividing 18 periods from time t1 to t of the video signal VS into four, the period V4 from time t1 to t2 corresponding to block A is channel Ch.
It is arranged at a position between 18 from time t5 to t9-1 in block B, and the time t, t, of each channel ChB, ChC, ChD corresponding to block B corresponding portions 2 to t3 + block C, respectively.
It is arranged at a position between 18 and t9.

By the way, when two-dimensional image processing is generally performed, as mentioned above, data that is continuous in the horizontal direction or data that is continuous in the vertical direction on the screen is often used, but the video signal dividing circuit of the present invention The signals of each divided channel correspond to, for example, each screen block A, B, C, I) in FIG. 1, so the above image processing can be easily performed using data in one channel. can be done.

However, regarding the boundaries between screen blocks A, B, C, and D, horizontally adjacent data may be allocated to other channels, so data near these boundaries may be duplicated or It is preferable to overramp and distribute it to each channel.

FIG. 4 shows each program 7 A and B on the above screen S.

Channels ChA, ChB, and ChC so that data near the boundaries of C and D overlap.

An example of allocation to ChD is shown. In FIG. 4, the effective display area that is actually displayed on the screen of IH of the original video signal vS is divided into four equal parts, and ΔT is added before and after each of these divided parts. The data of each channel chA are expanded on the time axis, respectively.
, ChB, ChC.

Allocated to ChD. That is, at time t11 in FIG.
During the IH period from to 117, the effective display area is at time t
12 to '16, the time T from t12 to t16 is divided into four to determine tl3 + tl4 + tl5, respectively. Then, regarding the video signal vs, in the part from 112 to '+3 corresponding to the above screen block A,
Signal vs-A in the time period of false +2ΔT obtained by applying ΔT before time 112 and ΔT after time t13, respectively
The time axis is expanded by four times and allocated to channel/channel Ch A. In addition, portions 113 corresponding to other screen blocks B, C, and D, respectively ~"4+tl<~t1.

Similarly, for tl, ~'+6, the time domain signal VS-B is obtained by adding only ΔT before and after each portion.

VS-C and VS-D are expanded on the time axis and distributed to channels ChB, ChC, and ChD, respectively. In this case, +2ΔT is less than or equal to V4 (V4+2ΔT<, V
4) In hlf, the signal obtained by expanding the time axis of each signal VS-A to VS-D by 4 times is stored in IH, so there is no signal loss (
Signals for each channel can be obtained.

Note that these partial signals VS -A-VS -4)
The signal obtained by expanding the time axis may be placed, for example, at the position between the next IH of each channel ChA-ChD, as explained with reference to FIG.

Next, an embodiment of a circuit according to the present invention for performing such video signal division will be described with reference to FIG.

In FIG. 5, a digital video signal with a sampling clock frequency of about 80 M1-(z, for example) is input to the input terminal 1. This corresponds to a digital conversion of a wideband video signal whose frequency band reaches approximately 30 MI (z).

This input digital video signal is sent to a memory circuit 2 constituted by a RAM (random access memory) or the like having a storage capacity of at least two horizontal periods (2H, two lines). This memory circuit 2 includes a write address control circuit 3
The write address is controlled by the read address control circuit 4.
Readout is controlled by A write clock signal and a read clock signal from the clock signal generation circuit 5 are supplied to each of these five address control circuits 3 and 4, respectively. The clock signal generation circuit 5 receives a coupling clock signal (approximately 8
0 MHz) is supplied, for example, via the input terminal 6 - on the basis of this sampling clock signal, the aforementioned write and read clock signals of the same frequency are output.

Next, the digital video signal read from the memory circuit 2 is divided into multiple launch circuits 7A, γB, γC2γD, which correspond to the number of channels to be divided, for example, four launch circuits.

and these four latch circuits γA, γB.

Each latch output from γC1γD is sent to each output terminal 9A via latch circuits 8A, 8B, 8C, and 8D.
, 9B, 9C, and 9D.

Each latch circuit 7A to 7D, 8A to 8D receives a latch pulse LP1 to L from the latch timing pulse generation circuit 10.
P5, and the launch circuits 7A to γD have launch pulses L of different timings (different phases).
In PI to LP4, input signals are latched (taken in) by latch pulses LP5 having the same timing for latch circuits 8A to 8D, respectively.

Here, the writing and reading control of the memory circuit 2 by each of the control circuits 3 and 4 is performed by dividing the IH portion of the high-speed digital video signal vS supplied to the input terminal 1 into four, and dividing the time of each divided portion into four. For example, as shown in FIG. 3, the data written between the original video signal vSOIH (for example, between t1 and t6) can be outputted sequentially from the first data to the next IH (for example, between t1 and t6). 15 to 10) while expanding the time axis and allocating it to each channel, the memory circuit 2 is
It is composed of line memories 2a and 2b, and has a selector switch 1.
In accordance with 2.13, one may be used for writing and the other for reading by alternately switching between them.

That is, the input terminal 11 in FIG. 6 is supplied with digital video signal data from the input terminal 1 in FIG. 5, and the data from this terminal 11 is switched by the changeover switch 12. The data is sent and written to either one of the line memories 2a and 2b. The line memories 2a and 2b are
When one is in writing state, the other is in reading state,
The read data is taken out from the output terminal 14 via the changeover switch 13fj:', and is sent to each launch circuit 7 in FIG.
A.

7B, 7C, and γD, respectively. That is, the selected terminals a and b of each selector switch 12.13 are connected and switched in a complementary manner to each other every 1H. For example, in the state shown in FIG. A switch 12 is selectively connected to the selected terminal a, and a switch 13 is selectively connected to the selected terminal A.

By the way, the data from the output terminal 14 is l f
(Each block of previously written data A, B.

It is sufficient that the portions corresponding to C and D are sequentially and cyclically output from each starting position. this is,
For example, from time t1 to ts in the video signal VS in FIG.
When data for IH at time t is sequentially written to addresses 0 to 1999 of a 2000-word line memory, for example, each block A.

The data corresponding to B, C, and D are respectively 0 to 4.9.9.500 to . 9:99.1oo
.

~゛Engineering 499. and written to addresses 1500-1999. Then, during the next IH (time t, to t.

between), set the read address to o, 500.1o
oo.

↓fi00,1,50i,1o01,150'i,...
・ Each block is cyclically scanned from the first address of each block and read out in chronological order. The frequency of the read clock CK R at this time is equal to the sampling clock frequency (for example, about 80 MHz) of the original input digital video signal, and the frequency of the read clock CK R is equal to the sampling clock frequency (for example, about 80 MHz) of the original input digital video signal, and the frequency of the read clock CK R is equal to the sampling clock frequency (for example, about 80 MHz) of the original input digital video signal, and
Let the data of 9) be DX, and the block Y to which it belongs (y=A.

B, C, D) as Dx(Y), as shown in FIG.
o(A), D, 0o(B), DlooO(C), Dl,
00(D), . . . are sequentially read out. Here, the fifth
As shown in FIG. 7, the launch pulses LPI, LP2, LP3° and LP4 supplied to the latch circuits 7A, 7B, and 7C27D shown in the figure are used as clock pulses CKR and CKR, respectively, as shown in FIG.
For example, if a latch circuit γA is used that has a frequency 1/4 of the frequency (4 times the period) and a phase difference that is shifted by one period of the sequential clock CKR, the latch circuit γA sequentially stores only the data belonging to block A, for example. Order injection, similarly launch circuit γB, 7
C and 7D can be made to respectively take in only the data belonging to example Ehabrosoku B, C and D, respectively. Further, by commonly supplying the latch pulse LP5 having a frequency of 1/4 of the clock CKR to the latch circuits 8A, 8B, 8c, and 8D, the phases of each channel can be matched.

Therefore, the data signals of each channel ChA, ChB, ChC, and ChD taken out from each launch circuit 8A, 8B, 8C, and 8D through the output terminals 9A, 9B, 9C, and 9D, respectively, are the original input digital signals. The frequency is 1/4 of the video signal's sampling clock frequency (approximately 20M
H2), and screen blocks A, B, and B in FIG. 1, respectively.
The data corresponds to C and D.

By the way, in the above explanation, the write address is controlled to simply increase by 0 or 1999-*, and the read address is controlled to increase by 0.500.1000/1500.1.
．． 5 ol, 1oot , , 1501·°°°, and so on, each block is designated cyclically, but address control may be performed such that it is distributed to each block when input data is written. For example, when 2000 pieces of sampling data for one line of an input digital video signal are sequentially input, the write address is set to 0.4.8.゛・
1996, 1.5.

9,"', 199712.6+ 10."-, 1998
,3゜7.11. ..., 1999, and simply increase the read address from O to 1999.

The output data at this time is D. (A), Dl (B), D
2 (C), D3 (D), D4 (A),
D! CB), D6 (C).

D? CD), etc., each block A, B, C,
Things belonging to D appear cyclically, and as in the above explanation,
Data signals of each channel ChA-ChD are taken out by latch circuits 7A-7D and 8A-8D.

Next, as explained in conjunction with FIG. 4, the respective channels ChA, ChB, and ChC overlap near the boundaries of each screen block A, B, C, and D.

An example of address control when allocating to ChD will be explained.

First, when the data in the effective display area in the IH of the input digital video signal S is 2000 pieces, and the data for the 71 minutes before and after which are the overlapping parts are 10 pieces each, the effective display area and ΔT before and after it are T + 2Δ.
Data of T is transferred from 0 to 2 of 2020 words of line memory.
Write sequentially to addresses oi and 9t. At this time, each of the 500 pieces of data on one line corresponding to each screen block A, B, C, and D in FIG.
l' 5.09.

1510 to 2009, respectively. The address is 2Q1 from Ω! It monotonically increases up to ll, but
The address becomes 0 at a time ΔT before time t12 in FIG. 4, and the address becomes 2019 at a time ΔT after time t16. When reading, the address is set to 0.500.1000°1500.
1.501, 1ooi, 1501. ..., but during IH, 520 words are read for each channel, and near the end of IH, the read address is ..., 519,1019°1519
．． It will reach 2019. If the channel Z to which the data Dx(Y) read at this time belongs is expressed as Dx(Y-Z), then Do(Δ-A), D50°(A-B),
Dloooo (B-C), DI, 0O (C-D).

−,,Dso+(BA),I)+o+o(CB)
, DI519 (D-〇), D2019 (Δ-D
) will be read out in this order. Here, let Δ be the block Y to which arbitrary data D′x (Y − Z ) belongs/
The difference is ΔT before and after the effective display area in Fig. 4.
It corresponds to that part. Note that among the read data, those whose belonging block Y and belonging channel Z match are DIo(AA), Dr++o(B B)
, D+o+o (C-C).

DI51(1(D-D),-,Dsoo(A A
), DIC1119 (B-B), DI609 (C-
C), D2009 (D'').

Extracting the data read out in this way for each channel is performed by the launch circuits 7A to γD as described above.
, 8A to 8D.

According to this embodiment of the present invention, two lines (2t
For example, high-speed data of 80MHz clock can be converted to low-speed data of 4 channels (for example,
For example, E
It becomes possible to perform image processing using normal TTL or the like without using a high-speed collector such as CL. In addition, since the data divided into these channels corresponds to each screen block equally divided in the line direction on the screen, two-dimensional image processing can be easily performed using only the data within each channel. Ru. In this case, the discontinuity at the division point in the line direction, that is, the boundary between each screen clock, requires image processing using a series of horizontal data. etc. can be performed using only data within the same channel. Furthermore, the overall phase (timing of the leading position) and clock phase of the data of each divided channel can be aligned, and only approximately one type of control signal is required for data processing after division. becomes easier.

Note that the present invention is not limited to the above-mentioned embodiments, and in the embodiments, an example in which an input video signal is divided into 4 channels is explained, but in general, it is possible to divide the input video signal into N channels/channels (N is an integer of 2 or more). Division can also be easily realized. Further, in the embodiment, the interval l8 is divided into N, but other time units may be divided into N. Further, each signal divided into N channels does not need to be used for two-dimensional image processing, and may be supplied to other signal processing, recording system, signal transmission system, etc.

〔Effect of the invention〕

According to the video signal dividing circuit according to the present invention, a high-speed clock input video signal can be divided into multiple channels of low-speed clock signals, and the signals within each divided channel/channel are shown to be related to each other on the screen. (Various signal processing, especially image processing, can be easily performed independently for each channel.)

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a screen displayed by a video signal;
FIG. 2 and FIG.
The figure is a timing chart for explaining still another example of the video signal division operation, FIG. 5 is a block circuit diagram showing one embodiment of the present invention, and FIG. 6 is a specific example of the memory circuit of FIG. The block circuit diagram shown in FIG. 7 is a timing chart for explaining the operation of each launch circuit in FIG. 5. 1... Video signal input terminal 2... Memory circuit 3... Write address control circuit 4... Read address control circuit 5... Clock signal generation circuit 6... Timing pulse generation circuits γA to γD, 8A to 8D...Latch circuit 98 to 9D.
...Signal output terminal patent applicant Sony Corporation representative Patent attorney Mimi Koike 1) Sakae Mura -

Claims (1)

[Claims] A video signal dividing circuit that divides an input video signal into N (N is an integer of 2 or more) to produce an N-channel signal, comprising: a write address control circuit that controls a write address according to a clock signal of the input video signal; A memory circuit in which the input video signal is written under write control by the write address control circuit, and a unit time of the input video signal written in the memory circuit by controlling the read address in accordance with the clock signal are N. a read address control circuit that cyclically and sequentially reads out the first signal of each of the divided portions; and N read address control circuits that have a frequency of 1 h of the clock signal frequency and whose phases are sequentially shifted by the period of the clock signal. It is characterized by comprising N latch circuits that sequentially latch the signals read out from the memory circuit by means of latch pulses, and outputs from these N latch circuits are taken out as divided signals of N channels. Video signal splitting circuit.