JP2964480B2 - Digital video signal processing circuit - Google Patents

Description

The present invention relates to a digital video signal processing circuit, in particular, a TBC.
The present invention relates to a digital video signal processing circuit suitable for

[Conventional technology]

Conventional TB using dual-port field memory
An example of C is shown in FIG.

In FIG. 4, a reproduced video signal SPVO of a VTR supplied to a terminal 41 is supplied to an A / D conversion circuit 42 and an AFC circuit 43.

The reproduction video signal SPVO is digitized by the A / D conversion circuit 42 and supplied to the field memory 44 as a digital video signal SDV. On the other hand, from the reproduced video signal SPVO, a clock CKW based on the horizontal synchronizing signal is
Is formed and supplied to the write control circuit 45. This clock CKW has the same time axis fluctuation as the reproduced video signal SPVO.

From the clock CKW, a write address / timing signal SWT is formed by the write control circuit 45 and supplied to the field memory 44.

The digital video signal SDV is written into the field memory 44 based on the write address / timing signal SWT. Note that during each period of the horizontal and vertical synchronization signals of the digital video signal SDV, the write address / timing signal SWT
Therefore, the above-described write operation is not performed. Therefore, the reproduced video signal S is stored in the field memory 44.
Only the video signal in the PVO is recorded as valid data.

On the other hand, a clock CKR formed by a clock oscillator 46 composed of a crystal or the like is supplied to a read control circuit 47 and a synchronization signal generator 48.

From the clock CKR, the read address / timing signal SRT is formed by the read control circuit 47 and supplied to the field memory 44. Read address / timing signal S
Valid data is output from the field memory 44 based on the RT and supplied to the adding circuit 49.

Further, a composite synchronization signal generated by the synchronization signal generator 48 in synchronization with the clock CKR is supplied to the addition circuit 49. The digital video signal SDV to which the composite synchronization signal is added from the adding circuit 49 is supplied to the D / A conversion circuit 50. The digital video signal SDV is converted into an analog signal by the D / A conversion circuit 50 and is taken out from the terminal 51 as a reproduced video signal SPV.

[Problems to be solved by the invention]

By the way, the conventionally used synchronization signal generator 48 is
There is a problem that the circuit scale is relatively large and the power consumption is relatively large. This synchronization signal generator 48
Even in the case of an integrated circuit, the size is about 1000 gates. The signal format is PAL, NTSC
In order to be able to share both types, the circuit scale must be further increased, and the power consumption also increases.

Therefore, without using the synchronizing signal generator 48, A / D conversion of the entire reproduced video signal SPVO, that is, the video signal and the synchronizing signal (from the sync chip level to the white peak level) is performed and recorded in the field memory 44. However, in this case, there is a problem that the dynamic range allocated to the video signal in the A / D conversion circuit 42 is reduced, and the accuracy is reduced.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a digital video signal processing circuit which can eliminate the need for a conventional synchronizing signal generator and can allocate an A / D conversion dynamic range only to a video signal.

[Means for solving the problem]

According to the present invention, a code corresponding to a synchronization signal pattern is written in a predetermined area of a memory at the time of an initial operation in accordance with a command from a control unit, valid data of a digital video signal is written in another predetermined area of a memory, and a code is added to a valid area. Data is read, and when writing at least the code corresponding to the synchronization signal pattern and the valid data of the digital video signal to the memory, only the valid data of the digital video signal is sent to the A / D conversion circuit. The code corresponding to the synchronization signal pattern is a code that is not assigned to the valid data of the digital video signal, and is switched by a switch based on a control signal generated corresponding to the digital video signal. Digital video signal processing circuit It is.

[Action]

In response to a command from the memory controller, a code corresponding to the synchronization signal is written in a predetermined area of the memory during the initial period. When the initial period ends, only the video signal in the reproduced video signal is subjected to A / D conversion, and valid data formed is written to another predetermined area of the memory.

On the other hand, when reading the memory, the above-mentioned code is added to the valid data to form a digital video signal,
Read every 1H.

This eliminates the need for a conventional synchronization signal generator, and allows the dynamic range of the A / D conversion circuit to be assigned only to the video signal.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. In this embodiment, the present invention is applied to a TBC. Reference numeral 6 denotes a field memory constituting the TBC. The field memory 6 is provided with control circuits (not shown) for controlling writing and reading.

In the configuration of FIG. 1, a memory controller 2 and registers 3, 4, and 5 are connected via a data bus 1.

For example, during a certain period after the power is turned on, that is, during the initial period, the set value N1 represented by the number of samples of the start point of the horizontal synchronization signal HSY in 1H in the reference signal SST of FIG.
And the set value N2 represented by the number of samples at the end point is output from the memory controller 2, the set value N1 is supplied to the register 3, and the set value N2 is supplied to the register 4. These setting values N1, N2
Is supplied to the comparison circuits 7 and 8 via the registers 3 and 4. The above-described reference signal SST corresponds to the digital video signal SDV and includes the horizontal synchronizing signal HSY and the vertical synchronizing signal VSY.

In addition, the set number of lines N3 including valid data in the number of lines per field, for example, 240, is supplied from the memory controller 2 to the register 5. The set line number N3 is supplied to the comparison circuit 9 via the register 5.

On the other hand, a sample clock CLK having a frequency of 910H (H is the horizontal scanning frequency) is supplied from the terminal 10 to the horizontal counter 11 and counted. Count value
N0 is supplied to the above-described comparison circuits 7 and 8, respectively.
When the count value N0 reaches 910, a carry signal SCRY indicating the end of 1H is supplied to the vertical counter 12 and the memory controller 2.

The count value N0 and the set values N1 and N2 are compared with the comparison circuit 7,
8 are compared.

In the comparison circuit 7, when the set value N1 = count value N0, a signal S7 is formed and supplied to the memory controller 2. In the comparison circuit 8, when the count value N0 = set value N2, a signal S8 is formed and supplied to the memory controller 2.

Carry signal SCRY supplied from horizontal counter 11
Is counted by the vertical counter 12, and the count value N00
Is supplied to the comparison circuit 9.

In the comparison circuit 9, a signal S 9 is formed when the set number of lines N 3 = count value N 00, and is supplied to the memory controller 2.

A high-level control signal Sc as shown in FIG. 2B is output from the memory controller 2 to the switch 13 in response to the supplied signal S7, and the terminals 13b, 1
3c is connected. In this state, the 80 code forming circuit
14 to 80 codes are supplied to the field memory 6. This 80 code (hexadecimal notation) is an 8-bit 2'S complementary code, and is a prohibition code that is not assigned to valid data.

As shown in FIG. 3, the field memory 6 has a horizontal blanking area 15 in which an 80 code corresponding to the horizontal synchronization signal HSY is written, and an 80 corresponding to the vertical synchronization signal VSY.
It is divided into a vertical blanking area 16 where a code is written and a data area 17 where valid data is written.

Therefore, at this stage, the above-mentioned 80 codes are written in the horizontal blanking area 15 of the field memory 6.

Then, as shown in FIG. 2B, the control signal Sc output from the memory controller 2 is set to a low level corresponding to the signal S8 supplied to the memory controller 2,
The switch 13 is switched to connect the terminals 13a and 13c. As a result, the supply of the 80 code from the 80 code forming circuit 14 is cut off. During the initial period, valid data of the digital video signal SDV is not supplied from the terminal 18,
Valid data is not written to the field memory 6.

As a result, 80 codes for 1H are written in the horizontal blanking area 15.

When the count value N0 of the horizontal counter 11 reaches 910, the carry signal SCRY is supplied to the vertical counter 12,
The count value N00 in the vertical counter 12 is incremented by one. Then, the count value N00 is supplied to the comparison circuit 9 and is compared with the set line number N3.

By repeating the above operation, 80 codes corresponding to the horizontal blanking of one field are written in the horizontal blanking area 15 of the field memory 6. When the count value N00 of the vertical counter 12 reaches the set number of lines N3, 80
Writing of the code is completed. At this time, the signal S9 is supplied from the comparison circuit 9 to the memory controller 2. The control signal Sc is output again from the memory controller 2 to control the switch 13. Thereby, the 80 code is supplied to the field memory 6 again.

This 80 code is written in the vertical blanking area 16 of the field memory 6.

In this way, when the writing of the 80 codes to the horizontal blanking area 15 and the vertical blanking area 16 of the field memory 6 is completed, the initial period is completed, and the control signal Sc is output from the memory controller 2. The switch 13 is controlled by the control signal Sc, and the terminals 13a, 13c
Is connected.

At this stage, only valid data of the digital video signal SDV supplied from the terminal 18 is written to the data area 17 of the field memory 6.

The valid data of the digital video signal SDV is formed by A / D converting only the video signal in the reproduced video signal.

 Next, a circuit operation at the time of reading will be described.

In synchronization with the read address / timing signal SRT supplied from the terminal 19 and stabilized by a crystal or the like, an 80 code is added to the effective data from the field memory 6 to form a digital video signal SDV. A
It is supplied to the conversion circuit 20 and the 80 code detection circuit 21.

The digital video signal SDV is converted into an analog signal by the D / A conversion circuit 20 and supplied to the terminal 22a of the switch 22. On the other hand, when the 80 code of the digital video signal SDV is detected by the 80 code detection circuit 21, the switch control signal SSW is supplied to the switch 22.

In the section of 80 codes (section of the horizontal synchronization signal HSY), the switch 22 is controlled by the switch control signal SSW, and the terminal 22
b and 22c are connected. Since a DC power supply 23 having a potential of the sync tip level of the horizontal synchronizing signal HSY is arranged between the terminal 22b and the ground, the horizontal synchronizing signal H
At the timing of SY, the potential of the sync chip level is taken out as the horizontal synchronizing signal HSY.

When the section of 80 codes ends, the switch 22 is controlled by the switch control signal SSW, and the terminals 22a and 22c are connected. Therefore, the digital video signal SDV is converted into an analog signal and is taken out from the terminal 24.

Therefore, from the terminal 24, the reproduced video signal SPV obtained by adding the synchronization signal to the video signal is taken out.

As described above, during the initial period, 80 codes corresponding to the horizontal synchronizing signal HSY and the vertical synchronizing signal VSY are written in a predetermined area of the field memory 6 in advance and read together with valid data. Can be eliminated, realizing space saving, power saving, and cost reduction.

Also, when A / D conversion is performed on the reproduced video signal SPVO before being applied to the TBC, it is not necessary to A / D convert the sync signal portion (sync tip level to pedestal level). Can be assigned, and the accuracy can be improved.

〔The invention's effect〕

According to the digital video signal processing circuit of the present invention, a code corresponding to the synchronization signal pattern at the time of initialization and not assigned to valid data is written in a predetermined area of the memory, and only the video signal in the reproduced video signal is A / D Write the converted valid data to another predetermined area of the memory,
Since the effective data is read by adding a code, the conventional synchronous signal generator can be eliminated, and there is an effect that space saving, power saving, and cost reduction can be realized.

When the reproduced video signal is A / D-converted, the synchronization signal (sync tip level to pedestal level) does not need to be A / D-converted. There is an effect that can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing chart showing the relationship between the output timings of a horizontal synchronizing signal and a control signal, FIG. FIG. 4 is a block diagram showing an example of a conventional TBC circuit. Explanation of main reference numerals in the drawings 2: memory controller, 15: horizontal blanking area,
6, 44: field memory, 16: vertical blanking area,
17: Data area, HSY: horizontal synchronization signal, VSY: vertical synchronization signal, SDV: digital video signal.

Claims (1)

(57) [Claims] 1. A code corresponding to a synchronization signal pattern at the time of initializing is written in a predetermined area of a memory by an instruction from a control unit, valid data of a digital video signal is written in another predetermined area of the memory, and the code is added. The valid data is read out, and at least when the code corresponding to the synchronization signal pattern and the valid data of the digital video signal are written into the memory, the validity of the digital video signal is Only the data is passed through the A / D conversion circuit, and the code corresponding to the synchronization signal pattern is a code that is not assigned to the valid data of the digital video signal, and is generated corresponding to the digital video signal. Output when a switch is switched based on a control signal. Digital video signal processing circuit, characterized in that.