JPS60140261U

JPS60140261U - Video signal processing device

Info

Publication number: JPS60140261U
Application number: JP1984027120U
Authority: JP
Inventors: 笹村　晃平; 徳光　淳亮
Original assignee: 日本ビクター株式会社
Priority date: 1984-02-27
Filing date: 1984-02-27
Publication date: 1985-09-17
Also published as: JPH042542Y2

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は本考案装置の一実施例を示すブロック　　　。系統図、第２図は第１図図示ブロック・系統中の要部の
一実施例を示す回路系統図、第３図は第２図図示回路系
統の動作説明用信号波形図、第４図は本考案装置の他の
要部の動作説明用信号波形図である。　　　　　　　　
　　　　　　　、１・・・再生複合カラー映像信号入力
端子、２・・・油変換器、３・・・フィールドメモリ、
４・・・パスラインコントローラ、５，９・・・タ不ミ
ング制御回路、６・・・検出信号入力端子、７ａ〜７Ｃ
・・・出力端子、８，１９・・・クロック信号入力端子
、１０・・・アドレス信号発生回路、１１・・−ＤＡ変
換器、１２・・・再生複合カラー映像信号出力端子、１
５・・・ディジタルビデオ信号入力端子、１６・・・水
平同期パルス抽出回路、１７・・・垂直同期パ゛ルス抽
出回路、２０・・・ロウアドレスカウンタ、２１・・・
ゲート回路、２３．２７・・・Ｊ−にフリップフロップ
（Ｊ　−ＫＦ。FIG. 1 is a block diagram showing one embodiment of the device of the present invention. System diagram, FIG. 2 is a circuit system diagram showing an example of the main part of the block/system shown in FIG. 1, FIG. 3 is a signal waveform diagram for explaining the operation of the circuit system shown in FIG. 2, and FIG. FIG. 3 is a signal waveform diagram for explaining the operation of other main parts of the device of the present invention.
, 1... Reproduction composite color video signal input terminal, 2... Oil converter, 3... Field memory,
4... Pass line controller, 5, 9... Timing control circuit, 6... Detection signal input terminal, 7a to 7C
...Output terminal, 8, 19...Clock signal input terminal, 10...Address signal generation circuit, 11...-DA converter, 12...Regenerated composite color video signal output terminal, 1
5... Digital video signal input terminal, 16... Horizontal sync pulse extraction circuit, 17... Vertical sync pulse extraction circuit, 20... Row address counter, 21...
Gate circuit, 23.27...J- has a flip-flop (J-KF.

Claims

[Scope of utility model registration request]

an AD converter for converting a composite video signal reproduced from a recording medium in a signal form having at least FM waves and then demodulated into a digital video signal; a field memory to which the digital video signal is supplied; a switch means for selectively outputting one of the Ryokawa digital video signals of the Finilt memory; a circuit Sennari for generating a pulse having a constant logical value near the middle of each field of the output digital video signal of the AD converter; An output signal of the switching means and a detection signal indicating a reproduction period during which the level of the FM wave reproduced from the recording medium is lower than a constant value are supplied, respectively, and the detection signal and the constant value pulse are supplied, respectively. When the signals are input at the same time, the field memory is used for one field period from the time when the first vertical synchronizing pulse in the output signal of the switch means following the time when the signals are input at the same time, and the write operation is performed. At the same time, the switch means causes the AD converter to selectively output the output signal, and at other times, the field memory performs a read operation, and the switch means causes the field memory to read out the digital video output signal. A video signal processing device comprising a control means for selectively outputting a signal, and an output means for obtaining a reproduced composite video signal output from the output signal of the switch means.