JP3268981B2 - Memory control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control circuit, and more particularly, to outputting a moving image by writing, for example, a plurality of video signals to a predetermined memory area by a write signal which switches at predetermined intervals. The present invention relates to a memory control circuit that outputs a still image by inhibiting output of a write signal to a desired memory area based on a still signal corresponding to a video signal.

[0002]

2. Description of the Related Art In a conventional memory control circuit 1 shown in FIG. 11, a video signal selected every three fields by a selector 4 according to an address signal and a write enable signal output from a microcomputer 2 and a signal generation circuit 3, respectively. Each of X, Y, Z and A is written to four memory areas formed in the VRAM 5. That is, when the still control is not performed, FIG.
Since the still signal is at a low level as shown in (D), a signal obtained by applying a gate to the VD signal shown in FIG. 12B by the gate signal shown in FIG. This is output as a write start signal shown in FIG. The microcomputer 2 outputs an address signal of a desired area in accordance with the write start signal, and supplies a write end signal shown in FIG. As can be seen from FIGS. 12F to 12H, the signal generation circuit 3 sets the write enable signal to a high level according to the write start signal and sets the write enable signal to the low level according to the write end signal. In this manner, the moving images of the video signals X, Y, Z, and A are displayed on the monitor.

Further, when still control is applied to the video signals Y and A, for example, the still signal is synchronized with the write timing signal shown in FIG. 13C as shown in FIG. It is at a high level for a predetermined period corresponding to the signals Y and A. Therefore, the write start signal is not output from the logic circuit 6 during that period, and the address signal and the write enable signal are not output from the microcomputer 2 and the signal generation circuit 3. Thus, the still images of the video signals Y and A currently written in the VRAM are displayed on the monitor.

[0004]

However, in such a conventional technique, there is a possibility that an erroneous image is output from the monitor depending on the timing at which the still control is turned off. That is, for example, at timings P5 and P5 shown in FIG.
When the still control is turned off in step 6, since the gate is not applied to the VD signal immediately after that, the write signal is output immediately after timings P5 and P6 as can be seen from FIG. Therefore, the video signals Y and Z and the video signal A are written in the memory area where the video signal Y and the video signal X are to be written. For this reason, the monitor
Incorrect image as shown in FIG.

Therefore, a main object of the present invention is to provide a memory control circuit capable of outputting a desired image from a monitor regardless of the timing at which the still control is turned on / off.

[0006]

According to the present invention, a writing means for writing a plurality of video signals into a predetermined memory area by a write signal output once in a predetermined period, and a desired video signal are provided. In a memory control circuit including a prohibition unit that prohibits output of a write signal to a desired memory area based on a still signal, the memory control circuit further includes a latch unit that latches a still signal every predetermined period, and the output of the latch unit is prohibited. Characterized by giving
It is a memory control circuit.

[0007]

When the still control is not performed, a write signal is applied to each of a plurality of memory areas formed in, for example, a VRAM at predetermined intervals. Each of the plurality of video signals is written to a predetermined memory area by the write signal. Therefore, for example, a plurality of moving images are output from the monitor. When still control is applied to a desired video signal, the still signal of the video signal is latched by the latch means, and the output of the latch means inhibits the output of the write signal. For this reason, a still image is output from a predetermined area of the monitor.

[0008]

According to the present invention, the output of the write signal is inhibited by the output of the latch means. Therefore, the inhibition period does not vary depending on the ON / OFF timing of the still control, and the desired period can be obtained from the monitor. Video can be output. The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

[0009]

Referring to FIG. 1, a memory control circuit 10 of this embodiment includes a timing generator 12. The timing generator 12 supplies a first select signal to the selector 14, which causes the selector 14 to operate at the input terminals C1 to C1.
Each of the composite video signals X, Y, Z and A input from C4 is selected every three fields. 6A, FIG. 7A, and FIG.
The video signals shown in FIGS. 8A and 9A are output. This video signal is converted into a digital signal by the A / D converter 16 and then thinned out every other pixel in the horizontal direction by the filter 18.

Then, the video signal from the filter 18 is
In response to a write signal, that is, an address signal from the microcomputer 40 and a write enable signal from the signal generation circuit 42, 448 in the column direction as shown in FIG.
VRAM2 with 718 dots in line and row direction
Written to 0. Specifically, the video signal X is written to the memory area x, the video signal Y is written to the memory area y, the video signal Z is written to the memory area z, and the video signal A is written to the memory area a. Note that each of the memory areas x to a is (column, row) = (0,
0), (0,359) (224,0) and (224,0)
359) 224 lines × 359 based on the address of (359)
Because of the dot size, the video signals X to A of one field, that is, 224 lines, which have been thinned out only in the horizontal direction, can be written to the VRAM 20.

The video signals X to X written in the VRAM 20
A is read in an interlaced manner by a read signal (not shown), is converted into an analog signal by the D / A converter 22, and is output from the output terminal c5. Then, video signals X to A are output from the monitor as shown in FIG.
The vertical synchronization signals included in the video signals X to A output from the selector 14 are separated by a vertical synchronization separation circuit 26 included in the memory control circuit 10, and the rising of the separated vertical synchronization signals is detected by a rising detection circuit 28. Is detected.
Therefore, from the rising edge detection circuit 28, FIG.
As shown in (B), FIG. 7 (B), FIG. 8 (B) and FIG. 9 (B), a VD signal synchronized with the rise of the vertical synchronization signal included in the video signals X to A is output. Further, the level of the still signal corresponding to each of the video signals X to A is switched from the switch circuit 30 according to the control of the operator. That is, when the switch 30a is turned on by the operator, the still signal passing through the line L1 goes high, when the switch 30b is turned on, the still signal passing through the line L2 goes high, and when the switch 30c is turned on, the line L3 goes high. The transmitted still signal goes high, and when the switch 30d is turned on, the still signal passing through the line L4 goes high.

The selector 32 is supplied with a second select signal from the timing generator 12. The second select signal is 2-bit data, and the data value is switched one field after the output of the selector 14 is switched. That is, the data value becomes “00” one field after the video signal X is output, and becomes “01” one field after the video signal Y is output, and one field after the video signal Z is output. The data value becomes “10” later, and the data value becomes “11” one field after the video signal A is output. Then, in response to each of “00” to “11”, that is, during a period corresponding to each of the video signals X to A, the selector 30 selects a still signal via the lines L1 to L4.

Therefore, the operator operates the switch 30a.
6D, the still signal output from the selector 32 is always at the low level as shown in FIG. 6D. However, the operator can operate the switch 30b and the switch 30b at the timings P1 and P2 shown in FIG. 30d
Is pressed, the still signal output from the selector 32 is
As shown in FIG. 7D, the signal rises at timings P1 and P2, and thereafter, as shown in FIG. 8D, the still signal rises over a period corresponding to the video signals Y and A. Then, when the operator turns off the switches 30b and 30d at the timings P3 and P4 shown in FIG. 9, the still signal falls at the timings P3 and P4 as shown in FIG. Become.

From the timing generator 12,
6 (C), 7 (C), 8 (C) and 9 in synchronism with the switching of the second select signal, that is, one field after the output from the selector 14 is switched.
A write timing signal is output as shown in FIG.
The write timing signal is at a high level during a period corresponding to a clock cycle (not shown). In the flip-flop circuit 34, the still signal from the selector 32 is latched by the write timing signal, so that the flip-flop circuit 34 outputs the still signal shown in FIGS.
(E), mask signals shown in FIGS. 8 (E) and 9 (E) are output. Therefore, if the still signal is always at the low level as shown in FIG.
It is always at the low level as shown in FIG.

However, when the level of the still signal from the selector 32 changes, the flip-flop circuit 34 latches the still signal at the timing when the write timing signal falls, and the level signal at that timing becomes the mask signal. Therefore, FIG.
Since the still signal is at the low level accidentally as shown in FIG. 7D when the write timing signal shown in FIG.
The mask signal is always at a low level as shown in FIG. 7 (E), but in FIG. 8, the still signal is at a high level over a period corresponding to the video signals X and A as shown in FIG. 8 (D). Therefore, as can be seen from FIG. 8E, the mask signal changes one clock later than the still signal. In FIG. 9, the still signal falls at the timings P3 and P4. However, since the still signal is at the high level at the time of the fall of the write timing signal output immediately before the timings P3 and P4, the mask signal becomes
As shown in (E), the high level is maintained until the fall of the write timing signal output after the timings P3 and P4.

The signal generation circuit 36 receives a write timing signal from a set terminal, receives a write enable signal from a reset terminal, and outputs a gate signal. 6 (F), FIG. 7 (F), FIG. 8 (F) and FIG.
As shown in (F), the signal generation circuit 36 raises the gate signal one clock later than the rise of the write timing signal, and lowers the gate signal one clock later than the rise of the write enable signal. The signal generation circuit 36 will be described. As shown in FIG.
Is applied to OR circuit 36c. The write enable signal applied to the reset terminal C7 is supplied to the AND circuit 3 via the inverting circuit 36a.
6b. The output of the flip-flop circuit 36d is also applied to the AND circuit 36b, and the AND circuit
The signal is applied to OR circuit 36c. Then, the OR signal from the OR circuit 36c is supplied to the flip-flop circuit 36d. The output of the flip-flop circuit 36d is output from the terminal C8.

Therefore, for example, when a signal as shown in FIG. 4B is applied to reset terminal C7, according to the signal and the output of flip-flop circuit 36d, AN
An AND signal shown in FIG. 4C is output from the D circuit 36b. On the other hand, when the signal shown in FIG. 4A is given from the set terminal C6, O
An OR signal as shown in FIG. 4D is output from the R circuit 36c. Since the flip-flop circuit 36d latches the OR signal every clock, the flip-flop circuit 3d
From 6d, as shown in FIG.
A signal delayed by a clock is output. In other words, the signal generation circuit 36 outputs a signal that rises one clock after the rising of the input to the set terminal C6 and falls one clock after the rising of the input of the reset terminal C7. The input of the set terminal C6 and the reset terminal C
When the input of 7 simultaneously rises, the input of the set terminal C6 has priority, but in this embodiment, such a situation does not occur, so there is no need to consider it.

Returning to FIG. 1, the logic circuit 38 is supplied with the VD signal from the rise detection circuit 28, the gate signal from the signal generation circuit 36, and the mask signal from the flip-flop circuit 34. When the still control is not performed, that is, when the operator does not turn on any of the switches 30a to 30d, or when the timing P shown in FIG.
When the switches 30b and 30d are turned on at 1 and P2, the mask signal is always at the low level as shown in FIGS. 6 (E) and 7 (E), so that the logic circuit 38 outputs the VD signal and the gate signal. The logical sum is output as a write start signal instructing the start of writing. That is, the logic circuit 38 gates only one VD signal following the write timing signal, as shown in FIG.
On the other hand, during the period when the mask signal is at the high level as shown in FIGS. 8E and 9E, the VD signal and the gate signal are thereby masked, and the output of the write start signal during that period is inhibited. Is done. Therefore, the output of the address signal from the microcomputer 40 and the output of the write enable signal from the signal generation circuit 42 are also prohibited.

Microcomputer 40 receives the write start signal, the second select signal and write timing signal from timing generator 12, and receives the address signal and the write completion signal in accordance with the flowchart shown in FIG. Outputs end signal. The write end signal is obtained when the output of the address signal is completed, that is, as shown in FIGS. 6 (H), 7 (H), 8
As shown in (H) and (H) of FIG. 9, almost one field after the writing start signal is output, the level becomes high for one clock period. On the other hand, the signal generation circuit 42 operates according to the write start signal and the write end signal as shown in FIGS.
(I), and outputs a write enable signal as shown in FIGS. 8 (I) and 9 (I). That is, the write start signal is received from the set terminal, and the write enable signal is raised one clock delay from its rise. Further, the write end signal is received from the reset terminal, and the write enable signal falls with a delay of one clock from the rise of the write end signal. Note that the signal generation circuit 42 is
Since the configuration is the same as that described above, duplicate description will be omitted.

The processing of the microcomputer 40 will be described with reference to the flowchart shown in FIG. The microcomputer 40 first determines in step S1 whether the write timing signal has risen.
If "NO", the process returns to the step S1, but if "YES", the data value of the second select signal is determined in each of the steps S3 to S9. Then, when the data value is “0”
If "0", the write start address is set to (column, row) = (0, 0) in step S11, and the data value is set to "0".
If “1”, the start address is set to (column, row) = (0, 359) in step S13, and the data value is “10”.
If so, the start address is set to (column,
Row) = (224,0), and the data value is “1”.
If "1", the start address is set to (column, row) = (224, 359) in step S17. Then, in step S19, it is determined whether or not a write start signal is given. Returning to step S3, "YE
If S ", the address signal is output to the area of 224 lines and 359 dots based on the start address in step S19. When the output of the address signal ends, a write end signal is output in step S23. Therefore, the write enable signal falls one clock after the end of the output of the address signal, and the video signal is written after the write timing signal rises. Selector 14
The clock can be locked to the vertical synchronizing signal using one field period after the output is switched.

According to this embodiment, when the still control is not performed as shown in FIG. 6, the mask signal output from the flip-flop circuit 34 is always at a low level. According to the signal, only one VD signal following the write timing signal is supplied to the microcomputer 40 and the signal generation circuit 42 as a write start signal. Therefore, the microcomputer 4 operates according to the write start signal.
0 and an address signal and a write enable signal are output from the signal generation circuit 42, and the write enable signal falls due to the write end signal. Therefore, the video signals X to A selected by the selector 14 are written to the memory areas x to a of the VRAM 20. Therefore, a moving image corresponding to the video signals X to A is output from the monitor.

When still control is applied to the video signals Y and A at the timings P1 and P2 shown in FIG. 7, the selector 32 outputs the still signal shown in FIG. 7D. By being latched by the flip-flop circuit 34 in response to the write timing signal shown in FIG. 7C, the mask signal is still at the low level as shown in FIG. Therefore, at this time, a moving image is still output from the monitor 24.

However, from the next time, as shown in FIG. 8D, the still signals corresponding to the video signals Y and A rise in synchronization with the rise of the write timing signal. A mask signal delayed by one clock from the still signal is output. Therefore, while the mask signal is at the high level, the output of the address signal and the write enable signal from the microcomputer 40 and the signal generation circuit 42 is prohibited, and the video signals Y and A are not written in the memory areas y and a of the VRAM 20. . Therefore, the VRA
Still images corresponding to the video signals Y and A written in M20 are output. Thereafter, when the still control is turned off at timings P3 and P4 shown in FIG.
As shown in (D), the still signal falls at that timing. However, the mask signal maintains the high level even after timings P3 and P4 as shown in FIG.
It falls in synchronization with the fall of the write timing signal. Therefore, similarly to the timing shown in FIG.
The video signals Y and A are not written in the memory areas y and a of M20, and the monitor 24 outputs a still image corresponding to the video signals Y and A currently written.

According to this embodiment, since the still signal is latched by the flip-flop circuit 34 in accordance with the write timing signal, the monitor shown in FIG. Thus, a desired image can be output.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is an illustrative view showing a VRAM;

FIG. 3 is a block diagram illustrating a signal generation circuit.

FIG. 4 is a timing chart showing the operation of the embodiment in FIG. 3;
(A) is a waveform diagram showing a set terminal input, (B) is a waveform diagram showing a reset terminal input, and (C) is an AND diagram.
It is a waveform diagram showing a signal, (D) is a waveform diagram showing an OR signal, and (E) is a waveform diagram showing an output of a flip-flop circuit.

FIG. 5 is a flowchart showing a part of the operation of the embodiment in FIG. 1;

FIGS. 6A and 6B are timing charts showing a part of the operation of the embodiment in FIG. 1, wherein FIG. 6A is an illustrative view showing a video signal, FIG. 6B is a waveform chart showing a VD signal, and FIG. FIG. 3 is a waveform diagram showing a write timing signal, (D) is a waveform diagram showing a still signal, (E) is a waveform diagram showing a mask signal,
(F) is a waveform chart showing a gate signal, (G) is a waveform chart showing a write start signal, (H) is a waveform chart showing a write end signal, and (I) is a write enable signal. FIG.

7 is a timing chart showing a part of the operation of the embodiment in FIG. 1, (A) is an illustrative view showing a video signal, (B) is a waveform chart showing a VD signal, and (C) is a waveform chart. FIG. 3 is a waveform diagram showing a write timing signal, (D) is a waveform diagram showing a still signal, (E) is a waveform diagram showing a mask signal,
(F) is a waveform chart showing a gate signal, (G) is a waveform chart showing a write start signal, (H) is a waveform chart showing a write end signal, and (I) is a write enable signal. FIG.

8 is a timing chart showing a part of the operation of the embodiment in FIG. 1, (A) is an illustrative view showing a video signal, (B) is a waveform chart showing a VD signal, and (C) is a waveform chart. FIG. 3 is a waveform diagram showing a write timing signal, (D) is a waveform diagram showing a still signal, (E) is a waveform diagram showing a mask signal,
(F) is a waveform chart showing a gate signal, (G) is a waveform chart showing a write start signal, (H) is a waveform chart showing a write end signal, and (I) is a write enable signal. FIG.

9 is a timing chart showing a part of the operation of the embodiment in FIG. 1, (A) is an illustrative view showing a video signal, (B) is a waveform chart showing a VD signal, and (C) is FIG. 3 is a waveform diagram showing a write timing signal, (D) is a waveform diagram showing a still signal, (E) is a waveform diagram showing a mask signal,
(F) is a waveform chart showing a gate signal, (G) is a waveform chart showing a write start signal, (H) is a waveform chart showing a write end signal, and (I) is a write enable signal. FIG.

FIG. 10 is an illustrative view showing a video signal output from a monitor;

FIG. 11 is a block diagram showing a conventional technique.

12 is a timing chart showing a part of the operation of the conventional technique shown in FIG. 11, (A) is an illustrative view showing a video signal, (B) is a waveform chart showing a VD signal, and (C) ) Is a waveform diagram showing a write timing signal, (D) is a waveform diagram showing a still signal, (E) is a waveform diagram showing a gate signal, and (F) is a waveform diagram showing a write start signal. FIG. 7G is a waveform diagram showing a write end signal, and FIG.
FIG. 4 is a waveform diagram showing a write enable signal.

13 is a timing chart showing a part of the operation of the conventional technique shown in FIG. 11, (A) is an illustrative view showing a video signal, (B) is a waveform chart showing a VD signal, and (C) ) Is a waveform diagram showing a write timing signal, (D) is a waveform diagram showing a still signal, (E) is a waveform diagram showing a gate signal, and (F) is a waveform diagram showing a write start signal. FIG. 7G is a waveform diagram showing a write end signal, and FIG.
FIG. 4 is a waveform diagram showing a write enable signal.

14 is a timing chart showing a part of the operation of the conventional technique shown in FIG. 11, (A) is an illustrative view showing a video signal, (B) is a waveform chart showing a VD signal, and (C) ) Is a waveform diagram showing a write timing signal, (D) is a waveform diagram showing a still signal, (E) is a waveform diagram showing a gate signal, and (F) is a waveform diagram showing a write start signal. FIG. 7G is a waveform diagram showing a write end signal, and FIG.
FIG. 4 is a waveform diagram showing a write enable signal.

FIG. 15 is an illustrative view showing a video signal output from a monitor of the related art;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Memory control circuit 12 ... Timing generator 20 ... VRAM 34 ... Flip-flop circuits 36 and 42 ... Signal generation circuit 38 ... Logic circuit 40 ... Microcomputer

Claims (1)

(57) [Claims] 1. A method according to claim 1, wherein each of the plurality of video signals is performed in a predetermined period.
A memory comprising writing means for writing to a predetermined memory area by a write signal output repeatedly, and prohibiting means for inhibiting output of the write signal to a desired memory area based on a still signal corresponding to a desired video signal. The memory control circuit, further comprising: a latch unit that latches the still signal every predetermined period, wherein an output of the latch unit is provided to the prohibition unit.