JP3249403B2 - Memory control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control circuit, and more particularly to a memory control circuit for writing, for example, a plurality of video signals into a predetermined memory area.

[0002]

2. Description of the Related Art In a conventional memory control circuit 1 of this type shown in FIG. 18, a synchronization signal generation circuit 2 includes synchronization separation circuits 3a to 3a.
The write start signal is generated based on the vertical synchronizing signal output from 3c and the select signal output from the timing generator 4. The signal generating circuit 2 is specifically configured as shown in FIG. 19, and each of the input vertical synchronizing signals is selected by selectors 2a and 2b according to a select signal. The VD counters 2c and 2d are reset by the vertical synchronization signal output from the selectors 2a and 2b, and are incremented by the system clock. The count value generated in this manner is applied to write start signal generation circuits 2e and 2f, and a write start signal is generated according to each count value. That is, the write start signal is output after a predetermined time has elapsed from the fall of the vertical synchronization signal output from selectors 2a and 2b.

The microcomputer 5 has two processors (not shown).
VRAMs 6a and 6b individually receive a write start signal and a write timing signal, and follow the first write start signal after the write timing signal is applied.
Are supplied with a write enable signal and an address signal. Thus, the video signals X and Z output from the selector 7 and partially thinned out by the filter 8a are
The video signals Y and A output from the selector 7 and partially thinned out by the filter 8b have been written to a predetermined memory area of the RAM 6a, and have been written to a predetermined memory area of the VRAM 6b.

[0004]

However, in such a conventional technique, the video signal is converted to the VRA depending on the timing of the select signal output from the timing generator 4.
There was a possibility that writing to M6a and M6b could not be performed properly. That is, as described above, write start signal generation circuits 2e and 2f generate a write start signal based on the time point of the fall of the vertical synchronization signal output from selectors 2a and 2b.
As shown in FIG. 20B, if the vertical synchronization signal is selected while the vertical synchronization signal included in the video signal X is being input, the vertical synchronization signal falls at an erroneous timing. As shown in C), the write start signal is output at an incorrect timing. FIG.
As can be seen from (B) and (C), the write start signal of the video signal X is generated based on the falling edge of the last vertical synchronization signal included in the video signal Z.

For this reason, as shown in FIG. 20E, a write signal, that is, a write enable signal and an address signal are output at erroneous timing, and the VRAM 6
21A and FIG. 22 are stored in the predetermined memory area of FIG.
Instead of (A), video signals were written as shown in FIGS. 21 (B) and 22 (B). Therefore, a main object of the present invention is to appropriately write a video signal in a predetermined memory area. It is to provide a memory control circuit.

[0006]

According to a first aspect of the present invention, a plurality of video signals which are switched at every first predetermined period are changed according to a write start signal output in response to a vertical synchronization signal included in the video signals. A memory control circuit for writing to a predetermined memory area once in a first predetermined period, wherein a prohibiting means for prohibiting output of a write start signal for at least a second predetermined period corresponding to a vertical synchronizing signal from a switching point of a video signal; A memory control circuit, comprising:

According to a second aspect of the present invention, there is provided a memory control circuit for writing each of a plurality of video signals selected at predetermined intervals by a first selection means to a predetermined memory area in accordance with a write start signal. A plurality of counters reset by a vertical synchronizing signal included in each of the video signals; a second selection unit that selects each of the count values of the plurality of counters in synchronization with the first selection unit; And a write start signal generating means for generating a write start signal.

[0008]

In the first invention, the output of the write start signal is inhibited by the inhibiting means for at least the second predetermined period corresponding to the vertical synchronizing signal from the switching point of the video signal. Therefore, the video signal is written to the predetermined memory area according to the write start signal output after the second predetermined period has elapsed.

The prohibiting means gates the write start signal in accordance with, for example, a gate signal generated in the second predetermined period. Thereby, when the write start signal is output in response to the completely obtained vertical synchronization signal, that is, when the write start signal is output at an appropriate timing,
A video signal is written to a predetermined memory area according to the write start signal.

In the second invention, a plurality of counters corresponding to the plurality of video signals are reset by a vertical synchronization signal included in each of the plurality of video signals, and the plurality of counters are incremented by a clock.
The count value of each counter is selected by the second selection means in synchronization with the first selection means for selecting a plurality of video signals at predetermined time intervals, and the writing start signal generation means is selected according to the selected count value. Generate a write start signal. In accordance with the write start signal, the video signal from the first selecting means is written to a predetermined memory area. That is, the write start signal is generated in accordance with the count value of the counter reset by the vertical synchronization signal whose level changes at an appropriate timing, and the video signal is written to a predetermined memory area according to the write start signal.

[0011]

According to the first aspect, the output of the write start signal is inhibited during the second predetermined period, so that the write start signal is not output at an erroneous timing, and the video signal is output. Writing can be appropriately performed in a predetermined memory area. According to the second aspect, by providing a plurality of counters in the preceding stage of the second selecting means, the write start signal is always generated at an appropriate timing, so that the video signal can be appropriately written in a predetermined memory area. Can be.

The above objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

[0013]

Referring to FIG. 1, a memory control circuit 10 according to this embodiment includes selectors 12a to 12 which receive video signals X, Y, Z and A input from terminals C1 to C4, respectively.
c. Each of the selectors 12a to 12c outputs a signal from the timing generator 14 shown in FIG.
(C) and video signals X to A according to the first to third select signals as shown in FIGS.
Select one of That is, the first select signal
Each of the third select signals is a signal having 2-bit data, and the selectors 12a to 12c select the video signal X when the data value indicates "00". When the data value is "01", the selectors 12a to 12a
c selects the video signal Y. When the data value indicates "10", the selectors 12a to 12c select the video signal Z. Furthermore, the data value is "11".
, The selectors 12a to 12c select the video signal A.

FIGS. 8A to 8C and FIGS. 9A to 9 C
As can be seen from (C), the first select signal to the third select signal are signals in which the data value is decremented every three fields and the phases are shifted from each other by four fields. D) and FIG.
As shown in (D), a time-division multiplexed video signal is output, and the selector 12b outputs the signal shown in FIGS. 8 (F) and 9 (F).
8 (H) and 9 (H) are output from the selector 12c.
As shown in (1), time-division multiplexed video signals are output, and each video signal is supplied to the selector circuit 16.

The selector circuit 16 is a circuit including three-input one-output selectors 16a and 16b.
a selects one of the video signals output from the selectors 12a to 12c according to the fourth select signal from the timing generator 14, and the selector 16b outputs the video signal from the selectors 12a to 12c according to the fifth select signal from the timing generator 14. Selected video signal.

More specifically, the fourth select signal corresponds to FIG.
As shown in (J), this is a signal for switching the 2-bit data value between "10", "01" and "00" every two fields, and the selector 16a sets the data value to "0".
When the data value is "0", the video signal from the selector 12b is selected. When the data value is "01", the video signal from the selector 12b is selected. When the data value is "10", the video signal from the selector 12c is selected. Choose, so
As shown in FIG. 8 (K), video signals X and Z are alternately switched and output every two fields as a first predetermined period from selector 16a. The fifth select signal is also a signal in which the 2-bit data value is switched between "10", "01" and "00" every two fields as shown in FIG. 9 (J). As shown in J), the phase is delayed by three fields with respect to the fourth select signal. Therefore, the selector 16b is also connected to the selector 1
The output is switched in the same manner as in FIG. 6A, but the video signals Y and A are output from the selector 16b as shown in FIG.
It is switched and output every two fields as a predetermined period.

The video signal X output from the selector 16a
And Z are converted to digital data by the A / D converter 22a, and then thinned out every other pixel in the horizontal direction by the filter 24a. Then, the video signals X and Z from the filter 24a are converted into the VRAM by the write enable signal and the address signal output from the microcomputer 28.
The data is written to a predetermined memory area 26a. VRAM2
6a includes memory areas x and z as shown in FIG.
Are formed, each of which has a memory capacity equivalent to 360 dots × 224 lines. The video signals X and Z output from the filter 24a are converted into the memory areas x and z by the write enable signal and the address signal.
Is written to each of.

The video signals Y and A output from the selector 16b are converted into digital data by the A / D converter 22b, and then thinned out every other pixel in the horizontal direction by the filter 24b. Then, the video signals Y and A from the filter 24b are applied to the VRAM according to the write enable signal and the address signal from the microcomputer 28.
The data is written to the memory areas y and a formed in the memory area 26b as shown in FIG. The memory areas y and a also have a size of 360 dots × 22 as in the VRAM 26a.
It has a memory capacity of 4 lines.

The video signals X to A stored in the VRAMs 26a and 26b are read out in an interlaced manner by a microcomputer (not shown) different from the microcomputer 28.
Multiplexed by the multiplexer 30. Then, the multiplexed video signal is converted into an analog signal by the D / A converter 32 and output from the terminal C5. Selectors 12a to 12c
The vertical synchronizing signal and the horizontal synchronizing signal included in the video signal output from the video signal are separated by the sync separation circuits 18a to 18c and supplied to the signal generation circuit 20. Therefore, the vertical synchronization signal shown in FIGS. 8E and 9E is input from the synchronization separation circuit 18a, and the vertical synchronization signal shown in FIGS. 8G and 9G from the synchronization separation circuit 18b. , And the vertical synchronizing signal shown in FIGS. 8 (I) and 9 (I) is input from the sync separation circuit 18c. The signal generation circuit 20 also receives a fourth select signal shown in FIG. 8 (J), a fifth select signal shown in FIG. 9 (J), and a write timing signal shown in FIGS. 8 (M) and 9 (M). Given
The signal generation circuit 20 generates a signal based on these signals as shown in FIG.
And a write start signal shown in FIG. 9 (L). The microcomputer 28 receives the write start signal and the write timing signal from the timing generator 14 and responds to the write start signal given first after the write timing signal. A write enable signal as shown in (N) and an address signal as shown in FIGS. 8 (K) and 9 (K) for writing the video signals X to A into the memory areas x to a are generated.

Referring to FIG. 3, sync separation circuits 18a to 18a-1
The vertical synchronization signal input from 8c is applied to the selector 34a, and one of the vertical synchronization signals is selected according to the fourth select signal. The selected vertical synchronizing signal is supplied to a reset terminal of the VD counter 38a which is incremented by a system clock synchronized with the horizontal synchronizing signal. Therefore, the VD counter 38a is reset by the fall of the vertical synchronization signal. In the write start signal generation circuit 40a, the count value of the VD counter 38a is "4".
And when "5" is taken, a write start signal is generated. For this reason, when the selector 34a selects the vertical synchronizing signal during the input of the vertical synchronizing signal included in the video signal X, for example, the selector 34a outputs the signal shown in FIG.
As shown in (B), a partially omitted vertical synchronization signal is output. Therefore, the VD counter 38a is
As shown by 0 (C), reset is performed at an incorrect timing, and the write start signal is output from the write start signal generation circuit 40a at an incorrect timing. In order to prohibit such a write start signal from being output from the signal generation circuit 20, in this embodiment, the OR circuit 48 is used as prohibition means.
a and a gate signal generation circuit 46a, and an erroneous write start signal is gated by a gate signal generated by the gate signal generation circuit 46a and as shown in FIG.

More specifically, the selector 36a selects one of the horizontal synchronizing signals from the synchronizing separation circuits 18a to 18c in accordance with the fourth select signal, and
a is added to the selected horizontal synchronizing signal by the gate signal.
Apply D processing. The counter 44a includes an AND circuit 42a
When the AND signal from is at a high level, it is incremented in accordance with the system clock, and is reset by a write timing signal output at the timing of video signal switching as shown in FIG. This counter 44a is a counter which stops incrementing when incremented to "10" and maintains its count value ("10") unless reset, and the gate signal generation circuit 46a sets the count value to "0" to "9". ”, The gate signal is set to the high level, and the count value is set to“ 1 ”.
When it becomes "0", the gate signal is set to low level.

Therefore, the gate signal is supplied to the selector 16a.
From the time when the video signal output from the switch is switched to the high level, a 10-line period corresponding to the vertical synchronization signal period is at a high level, and the write start signal output during this period is gated. Therefore, from the OR circuit 48a, FIG.
As shown in (G), a write start signal generated based on the fall of the vertical synchronization signal having a complete waveform is output. It is desirable that the write start signal is generated after the elapse of the vertical synchronization signal period. This is because if the write start signal is generated before the elapse of the vertical synchronizing signal period, that is, for example, during the period when the count value of the VD counter 38a takes “1” and “2”, the video signal is switched. This is because, by prohibiting the output of the write start signal for the next ten lines, even when the vertical synchronization signal is obtained in perfect form, the write start signal based on the signal is gated.

The video signal Y output from the selector 16b
And a write start signal for writing A are supplied to selector 34
Although generated by the b-OR circuit 48b, the configuration of these circuits is the same as that of the above-described selectors 34a-OR circuit 48a. Therefore, the circuit is duplicated by replacing "a" attached to the reference number with "b". Description is omitted. The microcomputer 28 includes two processors 28a and 28b, and the processor 28a outputs a write start signal and a write timing signal corresponding to the video signals X and Z output from the selector 16a in accordance with the flow charts shown in FIGS. To process. In addition, the processor 28b processes the write start signal and the write timing signal corresponding to the video signals Y and A output from the selector 16b according to the flowcharts shown in FIGS.

Specifically, the processor 28a first determines in step S1 whether the write timing signal shown in FIG. 8M has risen, and if "YES", the processor 28a proceeds to steps S3, S5 and S7. The data value of the fourth select signal shown in (J) is determined. If the data value is "00", the data value of the first select signal at this time is stored in a memory in step S9, and if the data value of the fourth select signal is "01", the second data is stored in a step S11. The data value of the select signal is stored, and if the data value of the fourth select signal is "10", the data value of the third select signal is stored in step S13. Such processing is performed because the data value of the fourth select signal does not correspond to the video signals X and Z, while the first select signal
The data value of the third select signal and the video signals X and Z have a corresponding relationship, and when the memory data is "00", the VRA
This is because the video signal X is input to the M26a, and the video signal Z is input to the VRAM 26a when the memory data is "10".

Therefore, the processor 28a determines in step S
At steps 15 and S17, the data value of the memory data is determined. If the data value is “00”, step S
At 19, the write start address of the VRAM 26a is set to (column,
Row) = (0,0), and if the data value is “10”, the write start address is (column, row) = (22
4,0). Then, in step S23, FIG.
It is determined whether or not the write start signal shown in (L) has risen. If “NO”, the process returns to the step S3.
If "S", the write enable signal is raised in step S25, and an address signal of a memory area of 224 lines × 360 dots with respect to the write start address is output in step S27. Upon completion, the write enable signal falls in step S29, and the process returns to step S1.

By the processing by the processor 28a in this manner, the write enable signal and the address signal are output only once in two field periods in response to the first write start signal output following the write timing signal. ,
As a result, the video signals X and Z are written into the memory areas x and z of the VRAM 26a. Processor 2
8b receives the write start signal and the write timing signal corresponding to the video signals Y and A and processes the flowcharts shown in FIGS. 6 and 7.
Except that the data value of the fifth select signal is determined at 5 'and S7' and whether the data value of the memory data is "01" or "11" is determined at steps S15 'and S17'. 4 and 5 are the same as those in the flowcharts shown in FIGS. When the processor 28b performs this process, the write enable signal and the address signal are output at appropriate timing, and the video signals Y and A are appropriately written in the memory areas y and a of the VRAM 26b. Therefore,
Video signals as shown in FIGS. 11A and 11B are written in the VRAMs 26a and 26b.

According to this embodiment, the output of the write start signal is inhibited for 10 line periods from the rise of the write timing signal, that is, the period corresponding to the vertical synchronization signal. It is output in response to the input complete vertical synchronization signal. For this reason, the write enable signal and the address signal are output from the microcomputer 26 at an appropriate timing, and the video signals X to A are output from the VRA.
The data can be appropriately written into the memory areas x to a of the M26a and M26b.

In this embodiment, the write start signal is generated on the basis of the rising point of the vertical synchronizing signal. However, the writing start signal may be generated in response to the rising of the vertical synchronizing signal. The good thing is, of course. Although the gate signal is output during the period corresponding to the vertical synchronization signal, the gate signal may be output for a longer period in order to surely prohibit the output of an erroneous write start signal.

However, in the above-described embodiment, as shown in FIG. 3, there is a problem that the scale of the signal generating circuit 20 is larger than that of the related art. Therefore, a new embodiment for solving such a point will be described below. Referring to FIG.
The memory control circuit 10 of another embodiment includes a sync separation circuit 18
a 'to 18c' separate the vertical synchronization signal only, and are the same as the memory control circuit 10 shown in FIG. 1 except that the signal generation circuit 20 'is configured as shown in FIG. By only describing
A duplicate description will be omitted.

FIGS. 14A to 1 show the selector 12a.
Since the video signal shown in FIG. 7A is output, the vertical sync signal shown in FIGS. 14B to 17B is output from the sync separation circuit 18a '. Since the selector 12b outputs the video signals shown in FIGS. 14 (D) to 17 (D), the vertical sync signals shown in FIGS. 14 (E) to 17 (E) are output from the sync separation circuit 18b '. Is output. further,
Since the video signals shown in FIGS. 14G to 17G are output from the selector 12c, the vertical synchronization signals shown in FIGS. 14H to 17H are output from the sync separation circuit 18c '. Is done. VD counters 50a to 50c shown in FIG.
Is incremented by a system clock synchronized with the horizontal synchronization signal, and is also synchronized with the synchronization separation circuits 18a 'to 18a'.
Reset by the vertical synchronizing signal from 18c '.
Therefore, the count value of the VD counter 50a is
(C) to FIG. 17 (C). Also, V
The D counter 50b is incremented as shown in FIGS. 14 (F) to 17 (F). Further, VD counter 5
The count value of 0c is incremented as shown in FIGS. 14 (I) to 17 (I).

The count values of VD counters 50a to 50c are applied to selectors 52a and 52b. The selector 52a serving as the second selecting means is configured as shown in FIG.
One of the count values is selected according to the (J) and the fourth select signal shown in FIG. That is, the fourth
When the data value of the select signal is "00", the count value output from the VD counter 50a is selected. When the data value is "01", the count value output from the VD counter 50b is selected. Is "10", the count value output from the VD counter 50c is selected. Therefore, from the selector 52a, FIG.
(L) and the count value shown in FIG. 15 (L) are output.

On the other hand, the selector 52b as another second selecting means changes one of the count values output from the VD counters 50a to 50c in accordance with the fifth select signal shown in FIG. 16 (J) and FIG. 17 (J). select. That is, similarly to the selector 52a, when the data value of the fifth select signal is "00", the count value output from the VD counter 50a is selected, and when the data value is "01", the count value from the VD counter 50b is selected. Is selected, and when the data value is "10", the count value from the VD counter 50c is selected. Therefore, the count output from the selector 52b is the same as that shown in FIG.
It changes as shown in (L).

Write start signal generating circuits 54a and 54b
Receives the count values output from the selectors 52a and 52b, and outputs a write start signal when the count value takes 4 or 5. Therefore, write start signal generation circuit 54a outputs the write start signals shown in FIGS. 14 (M) and 15 (M), and write start signal 52b outputs FIGS. 16 (M) and 17 (M). ) Is output.

The write start signal shown in FIGS. 14 (M) and 15 (M) generated in this manner and FIGS. 14 (N) and 15 outputted from timing generator 14 are shown.
In accordance with the write timing signal shown in (N), the processor 28a included in the microcomputer 28 provides the VRAM 26a with the write enable signal shown in FIGS. 14 (O) and 15 (O) and an address signal synchronized therewith. Also, the processor 28b of the microcomputer 28 operates according to the write start signal shown in FIGS. 16M and 17M and the write timing signal shown in FIGS. 16N and 17N.
(O) and the write enable signal shown in FIG. 17 (O) and an address signal synchronized therewith are applied to the VRAM 26b. Therefore, the selector circuits 16 as the first selecting means are stored in the memory areas x to a of the VRAMs 26a and 26b.
The video signals X to A output from the filters 24a and 24b are appropriately written.

According to this embodiment, as shown in FIG. 13, the VD counters 50a to 50c are arranged before the selectors 52a and 52b.
50c receive the complete vertical synchronization signal and are reset at the appropriate timing. Therefore, the selector 52a
There is no error in the count values output from write start signal generation circuits 54a and 54b.
Outputs a write start signal at an appropriate timing. As described above, the circuit scale can be greatly reduced as compared with the embodiment of FIG. 1 only by changing the arrangement of the VD counter and the selector as compared with the prior art.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is an illustrative view showing a VRAM;

FIG. 3 is a block diagram illustrating a signal generation circuit.

FIG. 4 is a flowchart showing a part of the operation of the microcomputer.

FIG. 5 is a flowchart showing a part of the operation of the microcomputer.

FIG. 6 is a flowchart showing a part of the operation of the microcomputer.

FIG. 7 is a flowchart showing a part of the operation of the microcomputer.

FIG. 8A is an illustrative view showing a first select signal supplied to a selector 12a, and FIG.
FIG. 9 is an illustrative view showing a second select signal supplied to
(C) is an illustrative view showing a third select signal provided to the selector 12c, (D) is an illustrative view showing a video signal output from the selector 12a, and (E) is an illustrative view showing a video signal shown in (D). 7F is an illustrative view showing a video signal output from the selector 12b, and FIG. 7G is a diagram showing a vertical synchronization signal included in the video signal shown in FIG. (H) is a waveform diagram showing a video signal output from the selector 12c, (I) is a waveform diagram showing a vertical synchronization signal included in the video signal shown in (H), (J) is an illustrative view showing a fourth select signal, (K) is an illustrative view showing a video signal output from the selector 16a, (L) is a waveform diagram showing a write start signal, and (M) is an illustration. ) Is a waveform diagram showing a write timing signal. To (N) is a waveform diagram showing a write enable signal.

FIG. 9A is an illustrative view showing a first select signal supplied to a selector 12a, and FIG. 9B is a diagram showing a selector 12b;
FIG. 9 is an illustrative view showing a second select signal supplied to
(C) is an illustrative view showing a third select signal provided to the selector 12c, (D) is an illustrative view showing a video signal output from the selector 12a, and (E) is an illustrative view showing a video signal shown in (D). 7F is an illustrative view showing a video signal output from the selector 12b, and FIG. 7G is a diagram showing a vertical synchronization signal included in the video signal shown in FIG. (H) is a waveform diagram showing a video signal output from the selector 12c, (I) is a waveform diagram showing a vertical synchronization signal included in the video signal shown in (H), (J) is an illustrative view showing a fifth select signal, (K) is an illustrative view showing a video signal output from the selector 16b, (L) is a waveform diagram showing a write start signal, and (M) is an illustration. ) Is a waveform diagram showing a write timing signal. To (N) is a waveform diagram showing a write enable signal.

10A is an illustrative view showing a video signal output from a selector 16a or 16b, FIG. 10B is a waveform diagram showing a vertical synchronization signal output from a selector 34a or 34b, and FIG. Is the VD counter 38a or 3
8B is an illustrative view showing a count value of FIG. 8B, (D) is a waveform chart showing a write start signal output from the write start signal generation circuit 40a or 40b, and (E) is a timing generator of FIG. FIG. 7F is a waveform diagram showing a write timing signal output from the gate signal generation circuit 4;
6G is a waveform diagram showing a gate signal output from 6a or 46b, and (G) is an OR circuit 48a or 48b.
FIG. 9 is a waveform diagram showing a write start signal output from the LM.

11A is an illustrative view showing a video signal written to a VRAM 26a, and FIG. 11B is an illustrative view showing a video signal written to a VRAM 26b.

FIG. 12 is a block diagram showing another embodiment of the present invention.

FIG. 13 is a block diagram illustrating a signal generation circuit.

14A is an illustrative view showing a video signal output from a selector 12a, FIG. 14B is a waveform diagram showing a vertical synchronization signal included in the video signal shown in FIG. 14A, and FIG.
14 is an illustrative view showing a count value of the VD counter 50a in FIG. 13, (D) is an illustrative view showing a video signal output from the selector 12b, and (E) is included in the video signal shown in (D). It is a waveform diagram which shows a vertical synchronizing signal, (F)
Is an illustrative view showing a count value of the VD counter 50b, (G) is an illustrative view showing a video signal output from the selector 12c, and (H) is a vertical synchronization signal included in the video signal shown in (G). (I) is a waveform diagram showing VD.
It is an illustrative view showing a count value of a counter 50c,
(J) is an illustrative view showing a fourth select signal, (K)
Is an illustrative view showing a video signal output from the selector 16a, (L) is an illustrative view showing a count value output from the selector 52a, (M) is a waveform diagram showing a write start signal, (N) is a waveform diagram showing a write timing signal, and (O) is a waveform diagram showing a write enable signal.

15A is an illustrative view showing a video signal output from a selector 12a, FIG. 15B is a waveform diagram showing a vertical synchronizing signal included in the video signal shown in FIG. 15A, and FIG.
14 is an illustrative view showing a count value of the VD counter 50a in FIG. 13, (D) is an illustrative view showing a video signal output from the selector 12b, and (E) is included in the video signal shown in (D). It is a waveform diagram which shows a vertical synchronizing signal, (F)
Is an illustrative view showing a count value of the VD counter 50b, (G) is an illustrative view showing a video signal output from the selector 12c, and (H) is a vertical synchronization signal included in the video signal shown in (G). (I) is a waveform diagram showing VD.
It is an illustrative view showing a count value of a counter 50c,
(J) is an illustrative view showing a fourth select signal, (K)
Is an illustrative view showing a video signal output from the selector 16a, (L) is an illustrative view showing a count value output from the selector 52a, (M) is a waveform diagram showing a write start signal, (N) is a waveform diagram showing a write timing signal, and (O) is a waveform diagram showing a write enable signal.

16A is an illustrative view showing a video signal output from a selector 12a, FIG. 16B is a waveform diagram showing a vertical synchronization signal included in the video signal shown in FIG.
14 is an illustrative view showing a count value of the VD counter 50a in FIG. 13, (D) is an illustrative view showing a video signal output from the selector 12b, and (E) is included in the video signal shown in (D). It is a waveform diagram which shows a vertical synchronizing signal, (F)
Is an illustrative view showing a count value of the VD counter 50b, (G) is an illustrative view showing a video signal output from the selector 12c, and (H) is a vertical synchronization signal included in the video signal shown in (G). (I) is a waveform diagram showing VD.
It is an illustrative view showing a count value of a counter 50c,
(J) is an illustrative view showing a fifth select signal, (K)
Is an illustrative view showing a video signal output from the selector 16b, (L) is an illustrative view showing a count value output from the selector 52a, (M) is a waveform diagram showing a write start signal, (N) is a waveform diagram showing a write timing signal, and (O) is a waveform diagram showing a write enable signal.

17A is an illustrative view showing a video signal output from a selector 12a, FIG. 17B is a waveform diagram showing a vertical synchronization signal included in the video signal shown in FIG. 17A, and FIG.
14 is an illustrative view showing a count value of the VD counter 50a in FIG. 13, (D) is an illustrative view showing a video signal output from the selector 12b, and (E) is included in the video signal shown in (D). It is a waveform diagram which shows a vertical synchronizing signal, (F)
Is an illustrative view showing a count value of the VD counter 50b, (G) is an illustrative view showing a video signal output from the selector 12c, and (H) is a vertical synchronization signal included in the video signal shown in (G). (I) is a waveform diagram showing VD.
It is an illustrative view showing a count value of a counter 50c,
(J) is an illustrative view showing a fifth select signal, (K)
Is an illustrative view showing a video signal output from the selector 16b, (L) is an illustrative view showing a count value output from the selector 52a, (M) is a waveform diagram showing a write start signal, (N) is a waveform diagram showing a write timing signal, and (O) is a waveform diagram showing a write enable signal.

FIG. 18 is a block diagram showing a conventional technique.

FIG. 19 is a block diagram showing a conventional signal generation circuit.

20A is an illustrative view showing a video signal output from a selector 7, and FIG. 20B is a diagram showing a selector 2 shown in FIG.
FIG. 6 is a waveform diagram showing a vertical synchronization signal output from FIG.
(C) is a waveform diagram showing a write start signal output from the write start signal generation circuit 2e, (D) is a waveform diagram showing a write timing signal output from the timing generator of FIG. FIG. 3E is a waveform diagram showing a write signal output from the microcomputer 5.

FIG. 21A is an illustrative view showing a video signal correctly written in a predetermined memory area of a VRAM 6a;
(B) is an illustrative view showing a video signal erroneously written to a predetermined memory area of the VRAM 6a;

FIG. 22A is an illustrative view showing a video signal correctly written in a predetermined memory area of a VRAM 6b;
(B) is an illustrative view showing a video signal erroneously written to a predetermined memory area of the VRAM 6b;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Memory control circuit 16 ... Selector circuit 20 ... Signal generation circuit 28 ... Microcomputer

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/76-5/956 H04N 5/44-5/46

Claims (3)

(57) [Claims] 1. A method according to claim 1, wherein a plurality of video signals switched every first predetermined period are determined once in the first predetermined period in accordance with a write start signal output in response to a vertical synchronization signal included in the video signal. A memory control circuit for writing data into the memory area, comprising: a prohibition unit for prohibiting the output of the write start signal for at least a second predetermined period corresponding to the vertical synchronization signal from a point in time when the video signal is switched. , Memory control circuit. 2. The apparatus according to claim 1, wherein said prohibiting means includes gate signal generating means for generating a gate signal during said second predetermined period, and gate means for applying a gate to said write start signal in accordance with said gate signal. Memory control circuit. 3. A memory control circuit for writing each of a plurality of video signals selected at predetermined intervals by a first selection means to a predetermined memory area in accordance with a write start signal, wherein the memory control circuit increments by a clock and outputs the plurality of video signals. A plurality of counters reset by a vertical synchronization signal included in each of the plurality of counters; a second selection unit that selects each of the count values of the plurality of counters in synchronization with the first selection unit; A memory control circuit, comprising: a write start signal generating means for generating the write start signal.