JPH04324711A - Semiconductor relay circuit - Google Patents

Abstract

PURPOSE:To reduce the chip size in the case of forming the relay circuit as a semiconductor integrated circuit. CONSTITUTION:A charging path of a stored charge between a gate and a source for quickening turn-on of an output FET 5 consists of one element of a photo thyristor 10. The photo thyristor 10 is coupled optically with a same light emitting diode 3 as that of a photovoltaic diode array 4 driving an output FET 5. Thus, the chip size is reduced in the case of forming the relay circuit as a semiconductor integrated circuit in comparison with a conventional relay circuit in which the charging path of a stored charge between a gate and a source for quickening turn-on of the output FET 5 consists of two elements being a photo transistor and a reverse flow blocking diode.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optically coupled semiconductor relay circuit in which input and output are coupled by optical signals.

0002

2. Description of the Related Art FIG. 3 is a circuit diagram of a conventional semiconductor relay circuit. The circuit configuration will be explained below. A light emitting diode 3 is connected between the pair of input terminals 1 and 2. A photovoltaic diode array 4 and a phototransistor 11 are optically coupled to the light emitting diode 3 . The photovoltaic diode array 4 uses its photovoltaic power as an output F.
It is connected so that it is applied between the gate and source of ET5. The drain and source of the output FET 5 are connected to a pair of output terminals 6 and 7. A diode 12 and a phototransistor 1 are connected between the drain and gate of the output FET 5 in order to speed up the turn-on of the output FET 5.
1 series circuit is connected. In addition, output FET5
A control circuit 8 is connected between the gate and source of the output FET 5 in order to speed up the turn-off of the output FET 5.

The operation of the above circuit will be explained below. When an input signal is applied between the input terminals 1 and 2, the light emitting diode 3 generates an optical signal. Upon receiving this optical signal, the photovoltaic diode array 4 generates a photovoltaic force. Further, the phototransistor 11 becomes conductive. Now, assuming that a voltage is applied between the output terminals 6 and 7 such that the drain of the output FET 5 has a high potential with respect to the source, the phototransistor 11 becomes conductive, so that the high potential side Diode 1 from output terminal 6
2. A current flows to the output terminal 7 on the low potential side through the phototransistor 11 and the gate-source capacitance of the output FET 5, and the gate-source capacitance of the output FET 5 is charged. Further, the gate-source capacitance of the output FET 5 is also charged by the photocurrent from the photovoltaic diode array 4, and the gate of the output FET 5 has a high potential with respect to the source. Here, if the output FET 5 is an N-channel enhancement mode FET, when the gate-source voltage of the output FET 5 exceeds a predetermined threshold voltage, the drain-source of the output FET 5 becomes conductive. , the output terminals 6 and 7 are in a conductive state.

Next, when the input signal between the input terminals 1 and 2 is cut off, the optical signal from the light emitting diode 3 disappears. As a result, the photovoltaic diode array 4 stops generating photovoltaic force, and the phototransistor 11 becomes non-conductive. At this time, the control circuit 8 configures a discharge path for the accumulated charge between the gate and source of the output FET 5, and
The drain and source of the transistor are brought into a non-conducting state. As a result, the output terminals 6 and 7 are cut off.

[0005]

[Problems to be Solved by the Invention] In the above conventional technology, the parts other than the light emitting diode 3 and the output FET 5 are as follows.
A dielectric isolation substrate is used to separate the individual diodes that constitute the photovoltaic diode array 4, which is composed of semiconductor integrated circuits. This is because the dielectric isolation substrate has better isolation performance during light irradiation than a normal PN junction isolation substrate. However, the manufacturing method for dielectric isolation substrates is more complicated than that of ordinary PN junction isolation substrates, so they are very expensive, and in order to reduce costs, it is desirable to reduce the chip size as much as possible.

The present invention has been made in view of the above points, and its purpose is to provide a semiconductor relay circuit whose chip size can be reduced when integrated into a semiconductor integrated circuit. be.

[0007]

[Means for Solving the Problems] In order to solve the above problems, in the present invention, as shown in FIG. 1, a light emitting diode 3 that generates an optical signal in response to an input signal, A photovoltaic diode array 4 is arranged to receive the optical signal of No. 3, and the photovoltaic force of the photovoltaic diode array 4 is applied between the gate and source to create a conducting state and a non-conducting state between the drain and source. In the semiconductor relay circuit, the semiconductor relay circuit includes an output FET 5 that switches between the output FET 5 and a control circuit 8 that forms a discharge path for accumulated charges between the gate and source of the output FET 5. The present invention is characterized in that a photoconductive thyristor 10 is connected between the drain and gate of the output FET 5.

Note that instead of the photoconductive thyristor 10,
As shown in FIG. 2, an ordinary thyristor 13 may be used and the thyristor 13 may be configured to be triggered using the photovoltaic force of the photovoltaic diode array 4.

[0009]

[Effect] Generally, in order to reduce the chip size of a dielectric isolation substrate, it is more efficient to reduce the number of dielectric isolation islands than to reduce the size of each component of the circuit. reduction will be effective. In the conventional example shown in FIG. 3, the charging path for the accumulated charge between the gate and source to speed up the turn-on of the output FET 5 is formed by two elements: a photoconductive semiconductor element such as a phototransistor 11 and a diode 12 for blocking reverse current. In contrast, in the present invention shown in FIG. 1, the photothyristor 10 is composed of one element. Therefore, in the present invention shown in FIG. 1, it is possible to reduce the chip size when integrated into a semiconductor circuit.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram of an embodiment of the present invention. The circuit configuration will be explained below. A pair of input terminals 1
, 2, a light emitting diode 3 is connected between them. A photovoltaic diode array 4 and a photothyristor 10 are optically coupled to the light emitting diode 3 . The photovoltaic diode array 4 is connected so that its photovoltaic force is applied between the gate and source of the output FET 5. The drain and source of the output FET 5 are connected to a pair of output terminals 6,
7 is connected. The anode and cathode of a photothyristor 10 are connected between the drain and gate of the output FET 5 in order to speed up turn-on of the output FET 5. Further, a control circuit 8 is connected between the gate and source of the output FET 5 in order to speed up the turn-off of the output FET 5.

The operation of this embodiment will be explained below. When an input signal is applied between the input terminals 1 and 2, the light emitting diode 3 generates an optical signal. Upon receiving this optical signal, the photovoltaic diode array 4 generates a photovoltaic force. Also, the photothyristor 10 is triggered. Now, assuming that a voltage is applied between the output terminals 6 and 7 such that the drain of the output FET 5 has a high potential with respect to the source, the triggering of the photothyristor 10 causes an output on the high potential side. A current flows from the terminal 6 to the output terminal 7 on the low potential side via the anode/cathode of the photothyristor 10 and the gate/source capacitance of the output FET 5, charging the gate/source capacitance of the output FET 5. Further, the gate-source capacitance of the output FET 5 is also charged by the photocurrent from the photovoltaic diode array 4, and the gate of the output FET 5 has a high potential with respect to the source. Here, if the output FET 5 is an N-channel enhancement mode FET, when the gate-source voltage of the output FET 5 exceeds a predetermined threshold voltage, the drain-source of the output FET 5 becomes conductive. , the output terminals 6 and 7 are in a conductive state.

When the drain and source of the output FET 5 become conductive, the drain has a lower potential than the gate of the output FET 5, so a reverse voltage is applied between the anode and cathode of the photothyristor 10. As a result, the photothyristor 10 is turned off. Since the photothyristor 10 has a PNPN four-layer structure, reverse current can be blocked, and the diode 12 for blocking reverse current as shown in the conventional example of FIG. 3 is not required.

Next, when the input signal between the input terminals 1 and 2 is cut off, the optical signal from the light emitting diode 3 disappears. As a result, the photovoltaic diode array 4 stops generating photovoltaic force. At this time, the control circuit 8 forms a discharge path for the accumulated charge between the gate and source of the output FET 5, and makes the drain and source of the output FET 5 non-conductive. As a result, the output terminals 6 and 7 are cut off.

When using a dielectric isolation substrate with a dielectric isolation island having a depth of 70 μm, the phototransistor 11 and diode 12 shown in FIG.
When only one photothyristor 10 is used, the chip area can be reduced by about 114 μm square.

FIG. 2 is a circuit diagram of another embodiment of the present invention. In this embodiment, a normal thyristor 13 is used in place of the photothyristor 10 of the embodiment shown in FIG. In order to apply a trigger voltage between the gate and cathode of this thyristor 13, a resistor 9 is inserted in series between the anode of the photovoltaic diode array 4 and the gate of the output FET 5. This resistor 9 also has the role of biasing the depletion mode control FET 14 constituting the control circuit 8 to a high impedance state.

The operation of this embodiment will be explained below. When the light emitting diode 3 generates an optical signal in response to an input signal and the photovoltaic diode array 4 generates a photovoltaic force upon receiving this optical signal, a voltage is generated across the resistor 9.
A trigger voltage is applied between the gate and cathode of the thyristor 13. Now, assuming that a voltage is applied between the output terminals 6 and 7 such that the drain of the output FET 5 has a high potential with respect to the source, the triggering of the thyristor 13 causes the output terminal on the high potential side to A current flows from the output terminal 7 on the low potential side through the anode/cathode of the thyristor 13 and the gate-source capacitance of the output FET 5, and the gate-source capacitance of the output FET 5 is charged. At this time, the depletion mode control FE
T14 is biased into a high impedance state by the voltage developed across resistor 9. Furthermore, the gate-source capacitance of the output FET 5 is charged by the photocurrent from the photovoltaic diode array 4 via the resistor 9.
The gate of the output FET 5 has a higher potential than the source. Here, if the output FET5 is an N-channel enhancement mode FET, the output FET5
When the gate-source voltage exceeds a predetermined threshold voltage, the drain-source of the output FET 5 becomes conductive, and the output terminals 6 and 7 become conductive.

When the drain and source of the output FET 5 become conductive, the drain has a lower potential than the gate of the output FET 5, so a reverse voltage is applied between the anode and cathode of the thyristor 13. Then, the thyristor 13 is turned off. Thyristor 13 is PNPN4
Since it has a layered structure, reverse current can be blocked, and a reverse current blocking diode 1 as shown in the conventional example of FIG.
2 becomes unnecessary.

Next, when the input signal between the input terminals 1 and 2 is cut off, the optical signal from the light emitting diode 3 disappears. As a result, the photovoltaic diode array 4 stops generating photovoltaic force. At this time, since the voltage across the resistor 9 disappears, the depletion mode control FET 14 returns to a low impedance state, discharges the accumulated charge between the gate and source of the output FET 5, and discharges the charge accumulated between the gate and source of the output FET 5. Make the sources non-conductive. As a result, the output terminals 6 and 7 are cut off.

[0019]

According to the present invention, in an optically coupled semiconductor relay circuit, a photothyristor that is triggered by an optical signal generated by a light emitting diode in response to an input signal, or a photothyristor that receives the optical signal and outputs it. A thyristor triggered by the photovoltaic force generated by the photovoltaic diode array for driving the FET was connected between the drain and gate of the output FET to form a charging path for the gate-source capacitance of the output FET. Therefore, compared to the conventional case in which the charging path for the gate-source capacitance of the output FET is configured with two elements: a photoconductive semiconductor element such as a phototransistor and a diode for reverse current blocking, one thyristor element This has the effect of reducing the number of circuit elements. Therefore, when a concentrator circuit is formed using a dielectric isolation substrate, the chip size can be reduced and costs can be reduced.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a circuit diagram of another embodiment of the present invention.

FIG. 3 is a circuit diagram of a conventional example.

[Explanation of symbols]

1 Input terminal 2 Input terminal 3 Light emitting diode 4 Photovoltaic diode array 5 Output FET 6 Output terminal 7 Output terminal 8 Control circuit 9 Resistance 10 Photothyristor 11 Phototransistor 12 Diode 13 Thyristor

Claims (3)

[Claims] 1. A light emitting diode that generates an optical signal in response to an input signal, a photovoltaic diode array arranged to receive the optical signal of the light emitting diode, and a photovoltaic power source of the photovoltaic diode array. A semiconductor comprising: an output FET to which a conductive state and a non-conductive state are applied between the drain and source when applied between the gate and source; and a control circuit that forms a discharge path for accumulated charges between the gate and source of the output FET. 1. A semiconductor relay circuit, wherein a photoconductive thyristor arranged to receive an optical signal from the light emitting diode is connected between the drain and gate of the output FET. 2. A light emitting diode that generates an optical signal in response to an input signal, a photovoltaic diode array arranged to receive the optical signal of the light emitting diode, and a photovoltaic diode array connected in series with the photovoltaic diode array. resistance and
An output FET to which the photovoltaic force of the photovoltaic diode array is applied between the gate and source through this resistor to switch between a conductive state and a non-conductive state between the drain and source.
and a control circuit for forming a discharge path for accumulated charges between the gate and source of an output FET, the voltage generated across the resistor when a photovoltaic force is generated by the photovoltaic diode array When triggered, a thyristor that forms a charging path for the accumulated charge between the gate and source of the output FET is connected to the output FET.
A semiconductor relay circuit characterized in that it is connected between the drain and gate of. 3. The semiconductor relay circuit according to claim 1, further comprising a current limiting resistor connected in series with the thyristor.