JPH0432421B2 - - Google Patents
Info
- Publication number
- JPH0432421B2 JPH0432421B2 JP57144308A JP14430882A JPH0432421B2 JP H0432421 B2 JPH0432421 B2 JP H0432421B2 JP 57144308 A JP57144308 A JP 57144308A JP 14430882 A JP14430882 A JP 14430882A JP H0432421 B2 JPH0432421 B2 JP H0432421B2
- Authority
- JP
- Japan
- Prior art keywords
- channel
- input
- connection request
- channels
- control device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14430882A JPS5935224A (ja) | 1982-08-20 | 1982-08-20 | デ−タ処理システムのチヤネル制御方式 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14430882A JPS5935224A (ja) | 1982-08-20 | 1982-08-20 | デ−タ処理システムのチヤネル制御方式 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5935224A JPS5935224A (ja) | 1984-02-25 |
| JPH0432421B2 true JPH0432421B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1992-05-29 |
Family
ID=15359058
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14430882A Granted JPS5935224A (ja) | 1982-08-20 | 1982-08-20 | デ−タ処理システムのチヤネル制御方式 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5935224A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61163455A (ja) * | 1985-01-16 | 1986-07-24 | Fujitsu Ltd | チャネル制御方法 |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5220295B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * | 1974-08-21 | 1977-06-02 | ||
| JPS532049A (en) * | 1976-06-29 | 1978-01-10 | Hitachi Ltd | Input output processing device |
| JPS54531A (en) * | 1977-06-03 | 1979-01-05 | Hitachi Ltd | Channel control system |
-
1982
- 1982-08-20 JP JP14430882A patent/JPS5935224A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5935224A (ja) | 1984-02-25 |