JPH04323833A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04323833A JPH04323833A JP9211891A JP9211891A JPH04323833A JP H04323833 A JPH04323833 A JP H04323833A JP 9211891 A JP9211891 A JP 9211891A JP 9211891 A JP9211891 A JP 9211891A JP H04323833 A JPH04323833 A JP H04323833A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- hydrogen
- polycrystalline silicon
- silicon thin
- plasma treatment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 46
- 239000001257 hydrogen Substances 0.000 claims abstract description 40
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 40
- 239000010409 thin film Substances 0.000 claims abstract description 33
- 238000009832 plasma treatment Methods 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims description 38
- 239000013078 crystal Substances 0.000 claims description 13
- 230000005669 field effect Effects 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 31
- 230000007547 defect Effects 0.000 abstract description 15
- 239000010408 film Substances 0.000 description 18
- 239000000758 substrate Substances 0.000 description 18
- 239000010410 layer Substances 0.000 description 12
- 229910021417 amorphous silicon Inorganic materials 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 230000003647 oxidation Effects 0.000 description 8
- 238000007254 oxidation reaction Methods 0.000 description 8
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 5
- 239000007790 solid phase Substances 0.000 description 5
- 238000011282 treatment Methods 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 238000005984 hydrogenation reaction Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229910021424 microcrystalline silicon Inorganic materials 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 150000002431 hydrogen Chemical class 0.000 description 2
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- YZCKVEUIGOORGS-UHFFFAOYSA-N Hydrogen atom Chemical compound [H] YZCKVEUIGOORGS-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000013081 microcrystal Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は半導体装置の製造方法に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device.
【０００２】0002
【従来の技術】非晶質シリコン薄膜、微結晶シリコン薄
膜、多結晶シリコン薄膜等の非単結晶半導体薄膜には、
ダングリングボンドが多数存在する。例えば多結晶シリ
コン薄膜に関しては、結晶粒界に存在するダングリング
ボンド等の欠陥が、キャリアに対するトラップ準位とな
り、キャリアの伝導に対して障壁として働く（Ｊ．Ｙ．
Ｗ．Ｓｅｔｏ，Ｊ．Ａｐｐｌ．Ｐｈｙｓ．，４６，ｐ５
２４７（１９７５））。キャリアの伝導が妨げられた結
果、多結晶シリコン薄膜をチャネル領域として用いた多
結晶シリコン薄膜トランジスタ（ｐｏｌｙ−ＳｉＴＦＴ
）のＯＮ電流は減退し、またトラップ準位の増加から電
子−正孔対の生成が起こりｐｏｌｙ−ＳｉＴＦＴのＯＦ
Ｆ電流が増大してしまう。[Prior Art] Non-single crystal semiconductor thin films such as amorphous silicon thin films, microcrystalline silicon thin films, and polycrystalline silicon thin films include
There are many dangling bonds. For example, in polycrystalline silicon thin films, defects such as dangling bonds existing at grain boundaries become trap levels for carriers and act as a barrier to carrier conduction (J.Y.
W. Seto, J. Appl. Phys. ,46,p5
247 (1975)). As a result of hindering carrier conduction, polycrystalline silicon thin film transistors (poly-SiTFTs) using polycrystalline silicon thin films as channel regions
) decreases, and electron-hole pairs are generated due to an increase in the trap level, which increases the OF of the poly-SiTFT.
The F current will increase.
【０００３】従って、ｐｏｌｙ−ＳｉＴＦＴの性能を向
上させるためには、前記欠陥を少なくする必要がある（
Ｊ．Ａｐｐｌ．Ｐｈｙｓ．，５３（２），ｐ１１９３（
１９８２））。[0003] Therefore, in order to improve the performance of poly-Si TFTs, it is necessary to reduce the defects (
J. Appl. Phys. , 53(2), p1193(
1982)).
【０００４】この目的のために水素による前記欠陥の終
端化が行なわれており、この様な水素化の方法としては
、水素プラズマ処理、水素イオン注入法、或るいはプラ
ズマ窒化膜からの水素の拡散法等が知られている。For this purpose, the defects are terminated with hydrogen, and such hydrogenation methods include hydrogen plasma treatment, hydrogen ion implantation, or terminating hydrogen from a plasma nitride film. Diffusion methods and the like are known.
【０００５】水素イオン注入法に於いては、イオン注入
装置という高価な装置を必要とし、数百Å程度の多結晶
シリコン層に水素を打ち込む際の制御性が悪い等の欠点
がある。また、プラズマ窒化膜からの水素の拡散法に於
いては、水素の供給が不十分であるために、水素プラズ
マ処理に比して特性が十分には向上しない等の欠点があ
る。The hydrogen ion implantation method requires an expensive device called an ion implantation device, and has drawbacks such as poor controllability when implanting hydrogen into a polycrystalline silicon layer with a thickness of about several hundred Å. Furthermore, in the method of diffusing hydrogen from a plasma nitride film, the supply of hydrogen is insufficient, so there are drawbacks such as the characteristics not being sufficiently improved compared to hydrogen plasma treatment.
【０００６】水素プラズマ処理法は、大面積に亘って制
御性良く半導体装置の特性を向上できる水素化方法であ
る。水素プラズマ処理の方法としては、例えば平行平板
型のプラズマ発生装置では真空チェンバー内に被処理材
を保持する基板側電極と対向させて電極（対向電極）を
配置し、対向電極側に高周波を印加することにより真空
チェンバー内に導入した水素ガスを分解し被処理材に水
素ラジカルを供給する方法が一般的である。The hydrogen plasma treatment method is a hydrogenation method that can improve the characteristics of a semiconductor device over a large area with good controllability. For hydrogen plasma treatment, for example, in a parallel plate type plasma generator, an electrode (counter electrode) is placed in a vacuum chamber facing the substrate side electrode that holds the material to be processed, and high frequency waves are applied to the counter electrode side. A common method is to decompose the hydrogen gas introduced into the vacuum chamber and supply hydrogen radicals to the material to be treated.
【０００７】[0007]
【発明が解決しようとする課題】しかし従来の水素プラ
ズマ処理法を用いた場合は、ｐｏｌｙ−ＳｉＴＦＴのゲ
ート耐圧不良やスレッシュホールド電圧シフトその他の
不良が発生することがある。However, when conventional hydrogen plasma processing methods are used, gate breakdown voltage defects, threshold voltage shifts, and other defects may occur in poly-Si TFTs.
【０００８】そこで、本発明は水素化によるＴＦＴ特性
の向上効果を維持しつつ不良の発生を防止するものであ
り、その目的とするところは、良好な特性となる半導体
装置の製造方法を提供するところにある。[0008] Therefore, the present invention aims to prevent the occurrence of defects while maintaining the effect of improving TFT characteristics due to hydrogenation, and its purpose is to provide a method for manufacturing a semiconductor device with good characteristics. It's there.
【０００９】[0009]
【課題を解決するための手段】本発明の半導体装置の製
造方法は、絶縁ゲート型電界効果トランジスタのチャネ
ル領域の少なくとも一部が非単結晶半導体からなる半導
体装置の製造方法に於いて、多結晶半導体薄膜を形成す
る工程と、前記多結晶半導体薄膜に複数回の水素プラズ
マ処理を施す工程とを少なくとも含むことを特徴とする
。Means for Solving the Problems The method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device in which at least a part of the channel region of an insulated gate field effect transistor is made of a non-single crystal semiconductor. The method is characterized in that it includes at least a step of forming a semiconductor thin film and a step of subjecting the polycrystalline semiconductor thin film to hydrogen plasma treatment a plurality of times.
【００１０】0010
【実施例】本発明の実施例を、図１の本発明に於けるＴ
ＦＴの工程図に従って説明する。図１（ａ）は、ガラス
、石英などの絶縁性非晶質基板若しくは基板上に積層し
たＳｉＯ２等の絶縁性非晶質材料層などの絶縁性非晶質
材料からなる支持層１００表面上に、多結晶シリコン等
の非単結晶シリコン薄膜１０１を積層し、その後ホトリ
ソグラフィー法により該非単結晶シリコン薄膜をパタニ
ングする工程である。該非単結晶シリコン薄膜の成膜方
法としては以下に述べるような方法がある。 （１）
減圧ＣＶＤ法で５８０℃〜６５０℃程度で多結晶シリコ
ン薄膜を成膜する。[Example] An example of the present invention will be described below with reference to FIG.
This will be explained according to the FT process diagram. FIG. 1(a) shows a support layer 100 made of an insulating amorphous material such as an insulating amorphous substrate such as glass or quartz, or an insulating amorphous material layer such as SiO2 laminated on the substrate. , a process in which a non-single-crystal silicon thin film 101 such as polycrystalline silicon is laminated, and then the non-single-crystal silicon thin film is patterned by photolithography. As a method for forming the non-single crystal silicon thin film, there are the following methods. (1)
A polycrystalline silicon thin film is formed at about 580° C. to 650° C. by low pressure CVD method.
【００１１】（２）ＥＢ蒸着法、スパッタ法、プラズマ
ＣＶＤ法等で非晶質シリコン薄膜を堆積後、５５０℃〜
６５０℃程度で２〜７０時間程度固相成長アニールを行
ない、粒径１〜２μｍ以上の大粒径の多結晶シリコン薄
膜を成膜する。(2) After depositing an amorphous silicon thin film by EB evaporation method, sputtering method, plasma CVD method, etc.
Solid phase growth annealing is performed at about 650° C. for about 2 to 70 hours to form a polycrystalline silicon thin film with a large grain size of 1 to 2 μm or more.
【００１２】（３）減圧ＣＶＤ法等で多結晶シリコン薄
膜を堆積後、イオンインプランテーション法によりＳｉ
等を打ち込み、該多結晶シリコン薄膜を非晶質化した後
、５５０℃〜６５０℃程度で固相成長アニールを行い、
粒径１〜２μｍ程度の大粒径多結晶シリコン薄膜を成膜
する。(3) After depositing a polycrystalline silicon thin film by low pressure CVD method etc., Si is deposited by ion implantation method.
etc. to make the polycrystalline silicon thin film amorphous, solid phase growth annealing is performed at about 550°C to 650°C,
A large grain polycrystalline silicon thin film having a grain size of about 1 to 2 μm is formed.
【００１３】尚、非単結晶シリコン薄膜１０１としては
、上述の多結晶シリコン薄膜以外にも微結晶シリコン薄
膜若しくは非晶質シリコン薄膜を用いてもよい。また、
成膜方法についても、上述の（１）〜（３）の方法のみ
で限定されるものではない。次に図１（ｂ）に示すよう
に熱酸化法等によりゲート酸化膜１０２を形成する。ド
ライ酸化法を用いれば酸素雰囲気中で約１１５０℃の熱
処理を行なうことによって、絶縁耐圧の高いゲート酸化
膜を得ることが出来る。ウェット酸化法を用いれば９０
０℃程度の低温の熱処理でもゲート酸化膜が形成される
が、ドライ酸化法で形成されたゲート酸化膜に比べれば
絶縁耐圧は低く、膜質は劣る。前記非単結晶シリコン薄
膜１０１として多結晶シリコン薄膜を用いた場合は、こ
の熱酸化工程で熱処理による結晶成長が進み、対体積結
晶化率が向上し、結晶粒径が拡大する。Note that as the non-single crystal silicon thin film 101, a microcrystalline silicon thin film or an amorphous silicon thin film may be used in addition to the above-mentioned polycrystalline silicon thin film. Also,
The film forming method is also not limited to the methods (1) to (3) described above. Next, as shown in FIG. 1(b), a gate oxide film 102 is formed by a thermal oxidation method or the like. If dry oxidation is used, a gate oxide film with high dielectric strength can be obtained by performing heat treatment at about 1150° C. in an oxygen atmosphere. 90 using wet oxidation method
Although a gate oxide film can be formed by heat treatment at a low temperature of about 0° C., the dielectric strength is lower and the film quality is inferior to that of a gate oxide film formed by dry oxidation. When a polycrystalline silicon thin film is used as the non-monocrystalline silicon thin film 101, crystal growth due to heat treatment progresses in this thermal oxidation step, the crystallization ratio to volume improves, and the crystal grain size increases.
【００１４】また、前記非単結晶シリコン薄膜１０１と
して非晶質シリコン薄膜若しくは微結晶シリコン薄膜を
用いた場合にも、この熱酸化工程で熱処理による結晶成
長が進み、結晶粒径５０００Åから数μｍの大きさの多
結晶シリコンに結晶成長する。Further, even when an amorphous silicon thin film or a microcrystalline silicon thin film is used as the non-single crystal silicon thin film 101, crystal growth due to heat treatment progresses in this thermal oxidation step, and the crystal grain size ranges from 5000 Å to several μm. Crystals grow into polycrystalline silicon of the same size.
【００１５】尚、ゲート酸化膜の形成方法としては上述
の熱酸化法に限らず、ＣＶＤ法、プラズマＣＶＤ法、Ｅ
ＣＲプラズマＣＶＤ法、光ＣＶＤ法、スパッタ法等でＳ
ｉＯ２膜を形成する方法、プラズマ酸化法等で低温酸化
する方法等もある。これらの方法は、工程の温度を６０
０℃程度以下の低温に出来るため、基板として安価なガ
ラス基板を用いることも可能となる点で優れている。Note that the method for forming the gate oxide film is not limited to the above-mentioned thermal oxidation method, but also CVD method, plasma CVD method, E
S by CR plasma CVD method, optical CVD method, sputtering method, etc.
There are also a method of forming an iO2 film, a method of low-temperature oxidation using a plasma oxidation method, etc. These methods reduce the process temperature to 60
Since the temperature can be kept at a low temperature of about 0° C. or lower, it is advantageous in that an inexpensive glass substrate can be used as the substrate.
【００１６】次に図１（ｃ）に示すようにゲート電極１
０３を形成する。該ゲート電極材料としては、一般的に
多結晶シリコンが用いられている。該多結晶シリコン層
の形成方法としては、減圧ＣＶＤ法で多結晶シリコン層
を形成し、ＰＣｌＯ３等を用いた熱拡散法により、ｎ＋
ｐｏｌｙ−Ｓｉを形成する方法、プラズマＣＶＤ法等で
、例えばＢ（ボロン）若しくはＰ（燐）を不純物として
ドープした非晶質シリコン層を形成し、５５０℃〜６５
０℃程度の固相成長アニールを２時間〜７０時間程度行
い、該非晶質シリコン層を多結晶化することで、ｐ＋ｐ
ｏｌｙ−Ｓｉ層若しくはｎ＋ｐｏｌｙ−Ｓｉ層を形成す
る等の方法がある。続いて該ゲート電極１０３をマスク
として不純物元素をイオン注入して、ソース領域１０４
及びドレイン領域１０５を形成する（この工程に伴って
、チャネル領域１０６も自動的に形成される）。前記不
純物元素としては、Ｐ（燐）、Ａｓ（砒素）、またはＢ
（ボロン）等が用いられている。Next, as shown in FIG. 1(c), the gate electrode 1
Form 03. Polycrystalline silicon is generally used as the gate electrode material. As a method for forming the polycrystalline silicon layer, the polycrystalline silicon layer is formed by a low pressure CVD method, and the n+
For example, an amorphous silicon layer doped with B (boron) or P (phosphorus) as an impurity is formed by a method of forming poly-Si, a plasma CVD method, etc., and heated at 550°C to 65°C.
By performing solid phase growth annealing at about 0°C for about 2 to 70 hours and polycrystallizing the amorphous silicon layer, p+p
There are methods such as forming an oly-Si layer or an n+poly-Si layer. Next, using the gate electrode 103 as a mask, impurity elements are ion-implanted to form the source region 104.
and a drain region 105 (channel region 106 is also automatically formed along with this step). The impurity element may be P (phosphorus), As (arsenic), or B.
(Boron) etc. are used.
【００１７】続いて図１（ｄ）に示すように層間絶縁膜
１０７を積層する。ここで水素プラズマ処理を行う。水
素プラズマ処理は２回〜１０回に分けて行った（この処
理を断続的な複数回の水素プラズマ処理と呼ぶ）が、詳
細については後述する。水素プラズマ処理を行うプラズ
マ発生装置としては、容量結合型の平行平板型の装置を
用いた。処理条件は以下のようにした。層間絶縁膜積層
後の前記基板等を基板側電極に装着し、水素ガスを導入
し、対向電極（平行平板型のプラズマ発生装置では基板
側電極と対向して配置しているのでこう呼称する）に１
３．５６ＭＨｚの高周波を印加して水素ガスをガス分解
する。その時のＲＦパワーは対向電極に２５０〜７００
ｍＷ／ｃｍ２であった。処理時間は高周波を印加してい
た時間の総計で５分〜５時間、基板温度２５０℃〜３５
０℃、水素ガス流量１００〜６００ｓｃｃｍ、電極間距
離２７〜４５ｍｍであった。但し処理条件はこれに限定
されるものではない。Subsequently, as shown in FIG. 1(d), an interlayer insulating film 107 is laminated. Here, hydrogen plasma treatment is performed. The hydrogen plasma treatment was performed in 2 to 10 times (this treatment is referred to as intermittent multiple hydrogen plasma treatment), and the details will be described later. A capacitively coupled parallel plate type device was used as a plasma generation device for performing the hydrogen plasma treatment. The processing conditions were as follows. After laminating the interlayer insulating film, the substrate, etc. is attached to the substrate side electrode, hydrogen gas is introduced, and the counter electrode (in a parallel plate type plasma generator, it is called this because it is placed opposite to the substrate side electrode). to 1
A high frequency of 3.56 MHz is applied to decompose hydrogen gas. The RF power at that time is 250 to 700 to the counter electrode.
It was mW/cm2. The processing time is 5 minutes to 5 hours in total including the time when high frequency is applied, and the substrate temperature is 250℃ to 35℃.
The temperature was 0° C., the hydrogen gas flow rate was 100 to 600 sccm, and the distance between the electrodes was 27 to 45 mm. However, the processing conditions are not limited to these.
【００１８】この水素プラズマ処理により、プラズマに
よりガス分解された原子状の水素が層間絶縁膜、ゲート
絶縁膜、多結晶シリコン中に拡散し、多結晶シリコン中
のダングリングボンドが終端化されるので、後述のよう
に特性が向上した多結晶シリコン薄膜トランジスタが得
られる。水素プラズマ処理後にソース領域及びドレイン
領域のコンタクト電極１０８を形成すれば薄膜トランジ
スタが完成する（図１（ｅ））。該コンタクト電極材料
としてはＡｌ、Ｃｒ、Ｎｉ等の金属材料が用いられてい
る。尚、水素プラズマ処理は層間絶縁膜積層後ではなく
、コンタクト電極形成後に行ってもかまわない。By this hydrogen plasma treatment, atomic hydrogen gas-decomposed by the plasma diffuses into the interlayer insulating film, gate insulating film, and polycrystalline silicon, and dangling bonds in the polycrystalline silicon are terminated. As will be described later, a polycrystalline silicon thin film transistor with improved characteristics can be obtained. After hydrogen plasma treatment, a thin film transistor is completed by forming contact electrodes 108 in the source and drain regions (FIG. 1(e)). Metal materials such as Al, Cr, and Ni are used as the contact electrode material. Note that the hydrogen plasma treatment may be performed not after the interlayer insulating film is laminated, but after the contact electrode is formed.
【００１９】本発明により形成した多結晶シリコンＴＦ
Ｔ（ｐｏｌｙ−ＳｉＴＦＴ）の電界効果易動度はＮｃｈ
ＴＦＴで５０ｃｍ２／Ｖ・ｓ（減圧ＣＶＤ法５９０℃で
多結晶シリコンを形成した場合）〜１６０ｃｍ２／Ｖ・
ｓ（プラズマＣＶＤ法で成膜した非晶質シリコンを６０
０℃で約１７時間固相成長させて多結晶シリコンを形成
した場合）となり、水素ガス雰囲気中でアニールしただ
けの場合（〜１０ｃｍ２／Ｖ・ｓ）と比べて大幅な特性
向上が為された。Polycrystalline silicon TF formed according to the present invention
The field effect mobility of T (poly-SiTFT) is Nch
TFT: 50cm2/V・s (when polycrystalline silicon is formed by low pressure CVD at 590°C) ~ 160cm2/V・
s (amorphous silicon formed by plasma CVD method)
When polycrystalline silicon was formed by solid-phase growth at 0°C for approximately 17 hours), the properties were significantly improved compared to when only annealing was performed in a hydrogen gas atmosphere (~10cm2/V・s). .
【００２０】また本発明により形成したｐｏｌｙ−Ｓｉ
ＴＦＴのＯＮ電流はトランジスタサイズＬ／Ｗ＝５μｍ
／１０μｍのＮｃｈＴＦＴで４００μＡ、ＯＦＦ電流は
同じサイズのＮｃｈＴＦＴで１０〜３０ｆＡであり、ス
イング（サブスレッシュホールド領域の傾きの逆数）は
０．４５Ｖ／ｄｅｃ．であった。[0020] Furthermore, poly-Si formed according to the present invention
The ON current of TFT is transistor size L/W = 5μm
/10 μm Nch TFT is 400 μA, the OFF current is 10 to 30 fA for the same size Nch TFT, and the swing (reciprocal of the slope of the subthreshold region) is 0.45 V/dec. Met.
【００２１】また、従来の水素プラズマ処理によるＴＦ
ＴのＶｇ−Ｉｄ特性のシフト（スレッシュホールド電圧
のシフト）量が−２Ｖ〜−５Ｖであるのに比べ、本発明
の断続的な複数回の水素プラズマ処理によるＴＦＴでは
該シフト量は高々−１．５Ｖ程度であった。[0021] Furthermore, TF by conventional hydrogen plasma treatment
The amount of shift in the Vg-Id characteristic (shift in threshold voltage) of TFT is -2V to -5V, whereas in the TFT processed by intermittent hydrogen plasma treatment multiple times according to the present invention, the amount of shift is -1 at most. It was about .5V.
【００２２】次に、従来の水素プラズマ処理で発生し易
いプラズマダメージによる不良が、本発明の断続的な複
数回の水素プラズマ処理では発生しにくい理由に関して
述べる。水素プラズマ処理で発生するダメージの原因は
、今のところ明らかではないが、プラズマ雰囲気中に浸
されたことにより基板にチャージアップが起こり、ゲー
ト−チャネル間に電圧がかかった状態になり、また基板
温度が３００℃程度と比較的高いため、疑似的にＢＴス
トレス（バイアス及び温度ストレス）が加わるために、
ＴＦＴに不良が生じたとするモデルが現象をよく説明し
ている。Next, we will discuss the reason why defects due to plasma damage, which tend to occur in conventional hydrogen plasma processing, are less likely to occur in the intermittent hydrogen plasma processing of the present invention. The cause of damage caused by hydrogen plasma processing is not clear at present, but being immersed in the plasma atmosphere causes a charge-up on the substrate, which creates a state in which voltage is applied between the gate and channel, and the substrate Since the temperature is relatively high at around 300℃, pseudo BT stress (bias and temperature stress) is applied, so
A model that assumes that a defect occurs in a TFT explains the phenomenon well.
【００２３】このモデルに則ると、本発明の断続的な複
数回の水素プラズマ処理では、一回のプラズマ処理の後
、次のプラズマ処理までの間の時間（処理間時間）で、
基板のチャージアップが緩和されると考えることができ
る。また、処理間時間に高周波を印加せずに水素ガスを
被処理材の付近に導入していると、■被処理材の余熱に
より雰囲気の水素ガスが多結晶シリコン中に拡散し多結
晶シリコン中のダングリングボンドを終端化する、■雰
囲気の水素ガスが高周波の熱励起で温まった基板を冷却
し温度ストレスがかかり難くなる、という利点がある。According to this model, in the multiple intermittent hydrogen plasma treatments of the present invention, the time between one plasma treatment and the next plasma treatment (inter-treatment time) is
It can be considered that the charge-up of the substrate is alleviated. In addition, if hydrogen gas is introduced near the material to be processed without applying high frequency during the inter-processing time, hydrogen gas in the atmosphere will diffuse into the polycrystalline silicon due to the residual heat of the material to be processed. (1) The hydrogen gas in the atmosphere cools the substrate heated by high-frequency thermal excitation, making it less likely to be subjected to temperature stress.
【００２４】すなわち本発明の断続的な複数回の水素プ
ラズマ処理では疑似的なＢＴストレスがかかり難くなる
ので、従来の水素プラズマ処理で発生する前述のスレッ
シュホールド電圧のシフト等の不良を皆無とすることが
出来るのである。断続的な複数回の水素プラズマ処理の
条件は、例えば次のようなものである。一回のプラズマ
処理を中断して水素ガスを流した状態を保つと、基板温
度は休止後５分程度はよく下降するが、その後は下降の
速度はそれほど速くはない。よって処理間時間は５分〜
３０分程度の範囲が最もよいと考えられる（図４参照）
。処理間時間が前記範囲よりも短い時間であると、基板
温度が充分下がりきらないので次のプラズマ処理に於い
て疑似的なＢＴストレスを起こし易くなり、スレッシュ
ホールド電圧のシフト量が増加する。In other words, in the intermittent multiple hydrogen plasma treatments of the present invention, pseudo BT stress is less likely to occur, so defects such as the above-mentioned threshold voltage shift that occur in conventional hydrogen plasma treatments are completely eliminated. It is possible. The conditions for the intermittent hydrogen plasma treatment multiple times are as follows, for example. If one plasma treatment is interrupted and hydrogen gas is kept flowing, the substrate temperature will drop well for about 5 minutes after the pause, but the rate of decline will not be so fast after that. Therefore, the time between processing is 5 minutes ~
A range of about 30 minutes is considered best (see Figure 4).
. If the inter-processing time is shorter than the above-mentioned range, the substrate temperature will not be lowered sufficiently, which will likely cause pseudo BT stress in the next plasma processing, and the amount of threshold voltage shift will increase.
【００２５】また、処理間時間が前記範囲よりも長い時
間であるとスループットが悪化すると考えられる。処理
中断回数については該回数を増やすに連れスレッシュホ
ールド電圧のシフト量が減少する傾向にあるが、９回以
上にすると殆ど変わりがなくなる（図５参照）。例えば
処理時間の総計が２時間の場合、処理間時間１０分、処
理中断回数４回で水素プラズマ処理を施したＴＦＴのス
レッシュホールド電圧のシフト量は−１．３Ｖにまで減
少する。複数回に分けた水素プラズマ処理の一回のプラ
ズマ処理時間及び処理間時間は均等に分ける必要はない
。[0025] Furthermore, if the inter-processing time is longer than the above range, it is thought that the throughput will deteriorate. As for the number of processing interruptions, the shift amount of the threshold voltage tends to decrease as the number of interruptions increases, but there is almost no difference when the number of interruptions is 9 or more (see FIG. 5). For example, when the total treatment time is 2 hours, the amount of shift in the threshold voltage of a TFT subjected to hydrogen plasma treatment is reduced to -1.3V when the inter-treatment time is 10 minutes and the number of interruptions is 4 times. It is not necessary to equally divide the plasma processing time and the inter-processing time of the hydrogen plasma processing divided into multiple steps.
【００２６】また本実施例では、容量結合型の平行平板
型のプラズマ発生装置を用いた水素プラズマ処理の場合
について説明したが、該装置の形状はこれに限定される
ものではない。基板側電極にも高周波を印加できる装置
を用い、基板側電極と対向電極の両方に高周波を印加し
て（例えば基板側電極にはＲＦパワー０〜２８０ｍＷ／
ｃｍ２の高周波を印加する）水素プラズマ処理を行った
ＴＦＴでは、対向電極のみに高周波を印加して水素プラ
ズマ処理を行ったＴＦＴと比べてスレッシュホールド電
圧のシフトが更に起き難くなる。Further, in this embodiment, a case has been described in which hydrogen plasma processing is performed using a capacitively coupled parallel plate type plasma generator, but the shape of the apparatus is not limited to this. Using a device that can also apply high frequency to the substrate side electrode, apply high frequency to both the substrate side electrode and the counter electrode (for example, apply RF power of 0 to 280 mW/2 to the substrate side electrode).
In a TFT that has been subjected to hydrogen plasma treatment (by applying a high frequency wave of cm2), a threshold voltage shift is more difficult to occur than in a TFT that has been subjected to hydrogen plasma treatment by applying a high frequency wave only to the counter electrode.
【００２７】以上述べたように、本発明を応用すれば、
ＯＮ電流が大きくＯＦＦ電流が小さくサブスレッシュホ
ールド電圧の立ち上がりが急峻なトランジスタを、プラ
ズマダメージ等による不良を皆無にして製造可能となる
。As described above, if the present invention is applied,
A transistor with a large ON current, a small OFF current, and a steep subthreshold voltage rise can be manufactured without any defects due to plasma damage or the like.
【００２８】本発明の応用としては、例えば、非結晶シ
リコンを素子材としたＴＦＴによって構成された液晶表
示パネル、密着型イメージセンサ、ドライバ内蔵型のサ
ーマルヘッド、有機系ＥＬ等を発光素子としたドライバ
内蔵型の光書き込み素子や表示素子、三次元ＩＣ等が考
えられる。本発明を用いることで、これらの素子の高速
化、高解像度化等の高性能化が実現される。Applications of the present invention include, for example, liquid crystal display panels constructed of TFTs using amorphous silicon as an element material, contact type image sensors, thermal heads with built-in drivers, organic EL, etc. as light emitting elements. Possible devices include an optical writing element with a built-in driver, a display element, and a three-dimensional IC. By using the present invention, higher performance such as higher speed and higher resolution of these elements can be realized.
【００２９】尚、図１では、ｐｏｌｙ−ＳｉＴＦＴ製造
工程に本発明を適用した場合を例としたが、本発明はこ
れに限定されるものではない。本発明は、チャネル領域
の少なくとも一部が多結晶である絶縁ゲート型電界効果
トランジスタ全てに対し有効である。また、チャネル領
域の少なくとも一部が微結晶である絶縁ゲート型トラン
ジスタや、チャネル領域の一部がスパッタ法や蒸着法等
で形成した水素化の不十分な非晶質半導体からなるトラ
ンジスタに於いても有効である。Although FIG. 1 shows an example in which the present invention is applied to a poly-SiTFT manufacturing process, the present invention is not limited to this. The present invention is effective for all insulated gate field effect transistors in which at least a portion of the channel region is polycrystalline. In addition, in insulated gate transistors in which at least part of the channel region is made of microcrystals, and in transistors in which part of the channel region is made of an insufficiently hydrogenated amorphous semiconductor formed by sputtering or vapor deposition, etc. is also valid.
【００３０】また、チャネル領域が単結晶であっても、
三次元ＩＣのように再結晶化若しくは固相成長させたシ
リコン層に素子を形成する場合、結晶内に生じ易い、亜
粒界などの欠陥を、本発明に基づく半導体装置の製造方
法で、ダングリングボンドの終端化を行なうと特性の向
上に効果がある。Furthermore, even if the channel region is a single crystal,
When forming an element in a silicon layer that has been recrystallized or grown in a solid phase, such as in a three-dimensional IC, defects such as sub-grain boundaries, which tend to occur in crystals, can be eliminated by the semiconductor device manufacturing method based on the present invention. Terminating the ring bond is effective in improving the characteristics.
【００３１】更に、ＨＢＴ（ヘテロバイポーラトランジ
スタ）等のヘテロ接合界面の欠陥密度の低減に対しても
本発明は有効である。特に、ヘテロ接合を形成する二つ
の半導体層のうちの少なくとも一方が非単結晶半導体よ
りなる場合には、本発明による水素化処理により、膜中
及び界面の欠陥を同時に低減することが出来る。Furthermore, the present invention is also effective in reducing the defect density at the heterojunction interface of HBTs (hetero-bipolar transistors) and the like. In particular, when at least one of the two semiconductor layers forming a heterojunction is made of a non-single crystal semiconductor, the hydrogenation treatment according to the present invention can simultaneously reduce defects in the film and at the interface.
【００３２】また、非単結晶半導体を素子材とした太陽
電池・光センサやバイポーラトランジスタ、静電誘導ト
ランジスタをはじめとして、本発明は幅広く半導体プロ
セス全般に応用することが出来る。Further, the present invention can be widely applied to semiconductor processes in general, including solar cells, optical sensors, bipolar transistors, and static induction transistors using non-single crystal semiconductors as element materials.
【００３３】[0033]
【発明の効果】以上述べたように、本発明によればｐｏ
ｌｙ−ＳｉＴＦＴ等のチャネル領域の少なくとも一部が
非単結晶半導体よりなる絶縁ゲート型電界効果トランジ
スタの高性能化を、プラズマダメージによる不良もなく
実現できる。また、本発明は絶縁ゲート型電界効果トラ
ンジスタに限らず、半導体プロセス全般に亘り広く応用
することが出来、その効果はきわめて大きい。[Effects of the Invention] As described above, according to the present invention, the po
It is possible to improve the performance of an insulated gate field effect transistor, such as a ly-SiTFT, in which at least a portion of the channel region is made of a non-single crystal semiconductor, without causing defects due to plasma damage. Further, the present invention can be widely applied not only to insulated gate field effect transistors but also to semiconductor processes in general, and its effects are extremely large.
【図１】図１（ａ）〜（ｅ）は、本発明の実施例に於け
る半導体装置の製造方法の一例を示す工程断面図である
。FIGS. 1A to 1E are process cross-sectional views showing an example of a method for manufacturing a semiconductor device in an embodiment of the present invention.
【図２】図２は、本発明の実施例に於ける断続的な複数
回の水素プラズマ処理を施したＮｃｈＴＦＴのＶｇ−Ｉ
ｄ特性図である。FIG. 2 shows the Vg-I of an Nch TFT subjected to intermittent hydrogen plasma treatment multiple times in an embodiment of the present invention.
d characteristic diagram.
【図３】図３は、従来の水素プラズマ処理を施したＮｃ
ｈＴＦＴのＶｇ−Ｉｄ特性図である。[Figure 3] Figure 3 shows Nc subjected to conventional hydrogen plasma treatment.
It is a Vg-Id characteristic diagram of hTFT.
【図４】図４は、本発明の実施例に於ける断続的な複数
回の水素プラズマ処理を施したＮｃｈＴＦＴのスレッシ
ュホールド電圧のシフト量の平均処理間時間依存性を示
す図である。FIG. 4 is a diagram showing the average inter-processing time dependence of the shift amount of the threshold voltage of an Nch TFT subjected to intermittent hydrogen plasma processing multiple times in an example of the present invention.
【図５】図５は、本発明の実施例に於ける断続的な複数
回の水素プラズマ処理を施したＮｃｈＴＦＴのスレッシ
ュホールド電圧のシフト量のプラズマ処理中断回数依存
性を示す図である。FIG. 5 is a diagram showing the dependence of the shift amount of the threshold voltage of an Nch TFT subjected to intermittent hydrogen plasma treatment a plurality of times in an example of the present invention on the number of interruptions in plasma treatment.
１００ 絶縁性支持層 １０１ 非単結晶シリコン薄膜 １０２ ゲート酸化膜 １０３ ゲート電極 １０４ ソース領域 １０５ ドレイン領域 １０６ チャネル領域 １０７ 層間絶縁膜 １０８ コンタクト電極 100 Insulating support layer 101 Non-single crystal silicon thin film 102 Gate oxide film 103 Gate electrode 104 Source area 105 Drain region 106 Channel area 107 Interlayer insulation film 108 Contact electrode
Claims (1)
チャネル領域の少なくとも一部が非単結晶半導体からな
る半導体装置の製造方法に於いて、多結晶半導体薄膜を
形成する工程と、前記多結晶半導体薄膜に複数回の水素
プラズマ処理を施す工程とを少なくとも含むことを特徴
とする半導体装置の製造方法。1. A method for manufacturing a semiconductor device in which at least a portion of a channel region of an insulated gate field effect transistor is made of a non-single crystal semiconductor, comprising the steps of: forming a polycrystalline semiconductor thin film; 1. A method of manufacturing a semiconductor device, the method comprising at least the step of performing hydrogen plasma treatment multiple times.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3092118A JP2976569B2 (en) | 1991-04-23 | 1991-04-23 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3092118A JP2976569B2 (en) | 1991-04-23 | 1991-04-23 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04323833A true JPH04323833A (en) | 1992-11-13 |
| JP2976569B2 JP2976569B2 (en) | 1999-11-10 |
Family
ID=14045522
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3092118A Expired - Lifetime JP2976569B2 (en) | 1991-04-23 | 1991-04-23 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2976569B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004095671A (en) * | 2002-07-10 | 2004-03-25 | Seiko Epson Corp | Thin film transistor, switching circuit, active element substrate, electro-optical device, electronic equipment, thermal head, droplet discharging head, printer device, and thin film transistor driven light emitting display device |
-
1991
- 1991-04-23 JP JP3092118A patent/JP2976569B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004095671A (en) * | 2002-07-10 | 2004-03-25 | Seiko Epson Corp | Thin film transistor, switching circuit, active element substrate, electro-optical device, electronic equipment, thermal head, droplet discharging head, printer device, and thin film transistor driven light emitting display device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2976569B2 (en) | 1999-11-10 |
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