JPH04313271A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH04313271A
JPH04313271A JP7922591A JP7922591A JPH04313271A JP H04313271 A JPH04313271 A JP H04313271A JP 7922591 A JP7922591 A JP 7922591A JP 7922591 A JP7922591 A JP 7922591A JP H04313271 A JPH04313271 A JP H04313271A
Authority
JP
Japan
Prior art keywords
electrode
hydrogen
hydrogen plasma
substrate
side electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7922591A
Other languages
Japanese (ja)
Other versions
JP3239372B2 (en
Inventor
Junji Sato
淳史 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP07922591A priority Critical patent/JP3239372B2/en
Publication of JPH04313271A publication Critical patent/JPH04313271A/en
Application granted granted Critical
Publication of JP3239372B2 publication Critical patent/JP3239372B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To obtain a semiconductor device with improved characteristics by performing hydrogen plasma treatment with hydrogen plasma which is produced at a polycrystalline semiconductor thin film by applying a high frequency to both a substrate-side electrode and an opposing electrode of a plasma generation device. CONSTITUTION:A polycrystalline silicon film 101 with a large grain diameter is formed on a supporting layer 100 which consists of an insulation amorphous material, a gate oxide film 102 is formed, a gate electrode 103 is formed, and then a source region 104 and a drain region 105 are formed with this electrode as a mask (a channel region 106 is also formed automatically). Then, an interlayer insulation film 107 is laminated and hydrogen plasma treatment is performed. A hydrogen plasma device is used, a substrate, etc., after laminating the interlayer insulation film is laminated is fitted to a substrate-side electrode, hydrogen gas is introduced, and a high frequency is applied to an opposing electrode 301 and a substrate-side electrode 301, thus enabling hydrogen gas to be cracked. Therefore, the cracked atom-shaped hydrogen is dissipated into the interlayer insulation film, a gate insulation film, a polycrystalline silicon and a polycrystalline silicon thin-film transistor with improved characteristics can be obtained.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は半導体装置の製造方法に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device.

【0002】0002

【従来の技術】非晶質シリコン薄膜、微結晶シリコン薄
膜、多結晶シリコン薄膜等の非単結晶半導体薄膜には、
ダングリングボンドが多数存在する。例えば多結晶シリ
コン薄膜に関しては、結晶粒界に存在するダングリング
ボンド等の欠陥が、キャリアに対するトラップ準位とな
り、キャリアの伝導に対して障壁として働く(J.Y.
W.Seto,J.Appl.Phys.,46,p5
247(1975))。キャリアの伝導が妨げられた結
果、多結晶シリコン薄膜をチャネル領域として用いた多
結晶シリコン薄膜トランジスタ(poly−SiTFT
)のON電流は減退し、またトラップ準位の増加から電
子−正孔対の生成が起こりpoly−SiTFTのOF
F電流が増大してしまう。
[Prior Art] Non-single crystal semiconductor thin films such as amorphous silicon thin films, microcrystalline silicon thin films, and polycrystalline silicon thin films include
There are many dangling bonds. For example, in polycrystalline silicon thin films, defects such as dangling bonds existing at grain boundaries become trap levels for carriers and act as a barrier to carrier conduction (J.Y.
W. Seto, J. Appl. Phys. ,46,p5
247 (1975)). As a result of hindering carrier conduction, polycrystalline silicon thin film transistors (poly-SiTFTs) using polycrystalline silicon thin films as channel regions
) decreases, and electron-hole pairs are generated due to an increase in the trap level, which increases the OF of the poly-SiTFT.
The F current will increase.

【0003】従って、poly−SiTFTの性能を向
上させるためには、前記欠陥を少なくする必要がある(
J.Appl.Phys.,53(2),p1193(
1982))。
[0003] Therefore, in order to improve the performance of poly-Si TFTs, it is necessary to reduce the defects (
J. Appl. Phys. , 53(2), p1193(
1982)).

【0004】この目的のために水素による前記欠陥の終
端化が行なわれており、この様な水素化の方法としては
、水素プラズマ処理、水素イオン注入法、或るいはプラ
ズマ窒化膜からの水素の拡散法等が知られている。
For this purpose, the defects are terminated with hydrogen, and such hydrogenation methods include hydrogen plasma treatment, hydrogen ion implantation, or terminating hydrogen from a plasma nitride film. Diffusion methods and the like are known.

【0005】水素イオン注入法に於いては、イオン注入
装置という高価な装置を必要とし、数百程度の多結晶シ
リコン層に水素を打ち込む際の制御性が悪い等の欠点が
ある。また、プラズマ窒化膜からの水素の拡散法に於い
ては、水素の供給が不十分であるために、水素プラズマ
処理に比して特性が十分には向上しない等の欠点がある
The hydrogen ion implantation method requires an expensive device called an ion implanter, and has drawbacks such as poor controllability when implanting hydrogen into several hundred polycrystalline silicon layers. Furthermore, in the method of diffusing hydrogen from a plasma nitride film, the supply of hydrogen is insufficient, so there are drawbacks such as the characteristics not being sufficiently improved compared to hydrogen plasma treatment.

【0006】水素プラズマ処理法は、大面積に亘って制
御性良く半導体装置の特性を向上できる水素化方法であ
る。水素プラズマ処理の方法としては、例えば平行平板
型のプラズマ発生装置では真空チェンバー内に被処理材
を保持する基板側電極と相対させて電極(対向電極)を
配置し、対向電極側に高周波を印加することにより真空
チェンバー内に導入した水素ガスを分解し被処理材に水
素ラジカルを供給する方法が一般的である。
The hydrogen plasma treatment method is a hydrogenation method that can improve the characteristics of a semiconductor device over a large area with good controllability. As a method for hydrogen plasma treatment, for example, in a parallel plate type plasma generator, an electrode (counter electrode) is placed in a vacuum chamber facing the substrate side electrode that holds the material to be processed, and high frequency is applied to the counter electrode side. A common method is to decompose the hydrogen gas introduced into the vacuum chamber and supply hydrogen radicals to the material to be treated.

【0007】[0007]

【発明が解決しようとする課題】しかし従来の水素プラ
ズマ処理法を用いた場合は、poly−SiTFTのゲ
ート耐圧不良やスレッシュホールド電圧シフトその他の
不良が発生することがある。
However, when conventional hydrogen plasma processing methods are used, gate breakdown voltage defects, threshold voltage shifts, and other defects may occur in poly-Si TFTs.

【0008】そこで、本発明は水素化によるTFT特性
の向上効果を維持しつつ不良の発生を防止するものであ
り、その目的とするところは、良好な特性となる半導体
装置の製造方法を提供するところにある。
[0008] Therefore, the present invention aims to prevent the occurrence of defects while maintaining the effect of improving TFT characteristics due to hydrogenation, and its purpose is to provide a method for manufacturing a semiconductor device with good characteristics. It's there.

【0009】[0009]

【課題を解決するための手段】本発明の半導体装置の製
造方法は、絶縁ゲート型電界効果トランジスタのチャネ
ル領域の少なくとも一部が非単結晶半導体からなる半導
体装置の製造方法に於いて、多結晶半導体薄膜を形成す
る工程と、前記多結晶半導体薄膜にプラズマ発生装置の
基板側電極と相対電極との両方に高周波を印加して生成
した水素プラズマにより水素プラズマ処理を施す工程と
を少なくとも含むことを特徴とする。
Means for Solving the Problems The method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device in which at least a part of the channel region of an insulated gate field effect transistor is made of a non-single crystal semiconductor. The method includes at least a step of forming a semiconductor thin film, and a step of subjecting the polycrystalline semiconductor thin film to hydrogen plasma treatment using hydrogen plasma generated by applying high frequency to both a substrate side electrode and a counter electrode of a plasma generator. Features.

【0010】0010

【実施例】本発明の実施例を、図1の本発明に於けるT
FTの工程図に従って説明する。図1(a)は、ガラス
、石英などの絶縁性非晶質基板若しくは基板上に積層し
たSiO2等の絶縁性非晶質材料層などの絶縁性非晶質
材料からなる支持層100表面上に、多結晶シリコン等
の非単結晶シリコン薄膜101を積層し、その後ホトリ
ソグラフィー法により該非単結晶シリコン薄膜をパタニ
ングする工程である。該非単結晶シリコン薄膜の成膜方
法としては以下に述べるような方法がある。
[Example] An example of the present invention will be described below with reference to FIG.
This will be explained according to the FT process diagram. FIG. 1(a) shows a support layer 100 made of an insulating amorphous material such as an insulating amorphous substrate such as glass or quartz, or an insulating amorphous material layer such as SiO2 laminated on the substrate. , a process in which a non-single-crystal silicon thin film 101 such as polycrystalline silicon is laminated, and then the non-single-crystal silicon thin film is patterned by photolithography. As a method for forming the non-single crystal silicon thin film, there are the following methods.

【0011】(1)減圧CVD法で580℃〜650℃
程度で多結晶シリコン薄膜を成膜する。
(1) 580°C to 650°C by low pressure CVD method
A polycrystalline silicon thin film is formed at about

【0012】(2)EB蒸着法、スパッタ法、プラズマ
CVD法等で非晶質シリコン薄膜を堆積後、550℃〜
650℃程度で2〜70時間程度固相成長アニールを行
ない、粒径1〜2μm以上の大粒径の多結晶シリコン薄
膜を成膜する。
(2) After depositing an amorphous silicon thin film by EB evaporation method, sputtering method, plasma CVD method, etc., 550° C.
Solid phase growth annealing is performed at about 650° C. for about 2 to 70 hours to form a polycrystalline silicon thin film with a large grain size of 1 to 2 μm or more.

【0013】(3)減圧CVD法等で多結晶シリコン薄
膜を堆積後、イオンインプランテーション法によりSi
等を打ち込み、該多結晶シリコン薄膜を非晶質化した後
、550℃〜650℃程度で固相成長アニールを行い、
粒径1〜2μm程度の大粒径多結晶シリコン薄膜を成膜
する。
(3) After depositing a polycrystalline silicon thin film by low pressure CVD method etc., Si is deposited by ion implantation method.
etc. to make the polycrystalline silicon thin film amorphous, solid phase growth annealing is performed at about 550°C to 650°C,
A large grain polycrystalline silicon thin film having a grain size of about 1 to 2 μm is formed.

【0014】尚、非単結晶シリコン薄膜101としては
、上述の多結晶シリコン薄膜以外にも微結晶シリコン薄
膜若しくは非晶質シリコン薄膜を用いてもよい。また、
成膜方法についても、上述の(1)〜(3)の方法のみ
で限定されるものではない。次に図1(b)に示すよう
に熱酸化法等によりゲート酸化膜102を形成する。ド
ライ酸化法を用いれば酸素雰囲気中で約1150℃の熱
処理を行なうことによって、絶縁耐圧の高いゲート酸化
膜を得ることが出来る。ウェット酸化法を用いれば90
0℃程度の低温の熱処理でもゲート酸化膜が形成される
が、ドライ酸化法で形成されたゲート酸化膜に比べれば
絶縁耐圧は低く、膜質は劣る。
As the non-single crystal silicon thin film 101, a microcrystalline silicon thin film or an amorphous silicon thin film may be used in addition to the above-mentioned polycrystalline silicon thin film. Also,
The film forming method is also not limited to the methods (1) to (3) described above. Next, as shown in FIG. 1(b), a gate oxide film 102 is formed by a thermal oxidation method or the like. If dry oxidation is used, a gate oxide film with high dielectric strength can be obtained by performing heat treatment at about 1150° C. in an oxygen atmosphere. 90 using wet oxidation method
Although a gate oxide film can be formed by heat treatment at a low temperature of about 0° C., the dielectric strength is lower and the film quality is inferior to that of a gate oxide film formed by dry oxidation.

【0015】前記非単結晶シリコン薄膜101として多
結晶シリコン薄膜を用いた場合は、この熱酸化工程で熱
処理による結晶成長が進み、対体積結晶化率が向上し、
結晶粒径が拡大する。また、前記非単結晶シリコン薄膜
101として非晶質シリコン薄膜若しくは微結晶シリコ
ン薄膜を用いた場合にも、この熱酸化工程で熱処理によ
る結晶成長が進み、結晶粒径5000Åから数μmの大
きさの多結晶シリコンに結晶成長する。
When a polycrystalline silicon thin film is used as the non-monocrystalline silicon thin film 101, crystal growth due to heat treatment progresses in this thermal oxidation step, and the crystallization ratio to volume improves.
Grain size expands. Further, even when an amorphous silicon thin film or a microcrystalline silicon thin film is used as the non-single crystal silicon thin film 101, crystal growth due to heat treatment progresses in this thermal oxidation step, resulting in crystal grain sizes ranging from 5000 Å to several μm. Crystals grow into polycrystalline silicon.

【0016】尚、ゲート酸化膜の形成方法としては上述
の熱酸化法に限らず、CVD法、プラズマCVD法、E
CRプラズマCVD法、光CVD法、スパッタ法等でS
iO2膜を形成する方法、プラズマ酸化法等で低温酸化
する方法等もある。これらの方法は、工程の温度を60
0℃程度以下の低温に出来るため、基板として安価なガ
ラス基板を用いることも可能となる点で優れている。
Note that the method for forming the gate oxide film is not limited to the above-mentioned thermal oxidation method, but also CVD method, plasma CVD method, E
S by CR plasma CVD method, optical CVD method, sputtering method, etc.
There are also a method of forming an iO2 film, a method of low-temperature oxidation using a plasma oxidation method, etc. These methods reduce the process temperature to 60
Since the temperature can be kept at a low temperature of about 0° C. or lower, it is advantageous in that an inexpensive glass substrate can be used as the substrate.

【0017】次に図1(c)に示すようにゲート電極1
03を形成する。該ゲート電極材料としては、一般的に
多結晶シリコンが用いられている。該多結晶シリコン層
の形成方法としては、減圧CVD法で多結晶シリコン層
を形成し、PClO3等を用いた熱拡散法により、n+
poly−Siを形成する方法、プラズマCVD法等で
、例えばB(ボロン)若しくはP(燐)を不純物として
ドープした非晶質シリコン層を形成し、550℃〜65
0℃程度の固相成長アニールを2時間〜70時間程度行
い、該非晶質シリコン層を多結晶化することで、p+p
oly−Si層若しくはn+poly−Si層を形成す
る等の方法がある。続いて該ゲート電極103をマスク
として不純物元素をイオン注入して、ソース領域104
及びドレイン領域105を形成する(この工程に伴って
、チャネル領域106も自動的に形成される)。前記不
純物元素としては、P(燐)、As(砒素)、またはB
(ボロン)等が用いられている。
Next, as shown in FIG. 1(c), the gate electrode 1
Form 03. Polycrystalline silicon is generally used as the gate electrode material. As a method for forming the polycrystalline silicon layer, the polycrystalline silicon layer is formed by a low pressure CVD method, and the n+
For example, an amorphous silicon layer doped with B (boron) or P (phosphorus) as an impurity is formed by a method of forming poly-Si, a plasma CVD method, etc., and heated at 550°C to 65°C.
By performing solid phase growth annealing at about 0°C for about 2 to 70 hours and polycrystallizing the amorphous silicon layer, p+p
There are methods such as forming an oly-Si layer or an n+poly-Si layer. Next, using the gate electrode 103 as a mask, impurity elements are ion-implanted to form the source region 104.
and a drain region 105 (channel region 106 is also automatically formed along with this step). The impurity element may be P (phosphorus), As (arsenic), or B.
(Boron) etc. are used.

【0018】続いて図1(d)に示すように層間絶縁膜
107を積層する。ここで水素プラズマ処理を行う。水
素プラズマ処理を行うプラズマ発生装置としては、容量
結合型の平行平板型の装置を用いた。処理条件は以下の
ようにした。層間絶縁膜積層後の前記基板等(以下被処
理材)を基板側電極に装着し、水素ガスを導入し、対向
電極(相対電極の一種。平行平板型のプラズマ発生装置
では基板側電極と対向して配置しているのでこう呼称す
る。)及び基板側電極に13.56MHzの高周波を印
加して水素ガスをガス分解する。その時のRFパワーは
対向電極には250〜700mW/cm2、基板側電極
には0〜280mW/cm2であった。処理時間は5分
〜5時間、基板温度250℃〜350℃、水素ガス流量
100〜600sccm、電極間距離27〜45mmで
あった。但し処理条件はこれに限定されるものではない
。この水素プラズマ処理により、プラズマによりガス分
解された原子状の水素が層間絶縁膜、ゲート絶縁膜、多
結晶シリコン中に拡散し、多結晶シリコン中のダングリ
ングボンドが終端化されるので、後述のように特性が向
上した多結晶シリコン薄膜トランジスタが得られる。
Subsequently, as shown in FIG. 1(d), an interlayer insulating film 107 is laminated. Here, hydrogen plasma treatment is performed. A capacitively coupled parallel plate type device was used as a plasma generation device for performing the hydrogen plasma treatment. The processing conditions were as follows. After laminating the interlayer insulating film, the substrate, etc. (hereinafter referred to as the treated material) is attached to the substrate side electrode, hydrogen gas is introduced, and a counter electrode (a type of relative electrode. In a parallel plate type plasma generator, the substrate side electrode is opposite to the substrate side electrode). 13.56 MHz high frequency is applied to the electrode on the substrate side to decompose the hydrogen gas. The RF power at that time was 250 to 700 mW/cm2 for the counter electrode and 0 to 280 mW/cm2 for the substrate side electrode. The processing time was 5 minutes to 5 hours, the substrate temperature was 250°C to 350°C, the hydrogen gas flow rate was 100 to 600 sccm, and the distance between the electrodes was 27 to 45 mm. However, the processing conditions are not limited to these. Through this hydrogen plasma treatment, atomic hydrogen gas-decomposed by the plasma diffuses into the interlayer insulating film, gate insulating film, and polycrystalline silicon, and dangling bonds in the polycrystalline silicon are terminated. Thus, a polycrystalline silicon thin film transistor with improved characteristics can be obtained.

【0019】尚、処理条件の中で基板側電極に0W/c
m2のRFパワーで高周波を印加する場合があるが、こ
れは従来の対向電極のみに高周波を印加する装置の場合
とは条件が違う。その理由とするところは、従来の対向
電極のみに高周波を印加する装置では基板側電極は接地
電位である(図3)が、本発明で使用した基板側電極に
も高周波を印加できる装置では、高周波のマッチングボ
ックスを介して接地されている(図2)からである。 (マッチングボックスは一般に可変コンデンサ等を擁し
ているため基板側電極は接地されていない。)基板側電
極にも高周波を印加できる装置を用いた本発明の水素プ
ラズマ処理では、従来の対向電極のみに高周波を印加す
る装置を用いた水素プラズマ処理と比べて、水素イオン
や水素ラジカルを選択的に多結晶シリコン中へ拡散させ
ることができ、処理後のTFTのVg−Id特性のシフ
ト(スレッシュホールド電圧のシフト)量を少なくでき
るという点で優れている。その際に重要な変数となるの
は基板側電極の電位VDCであるが詳細な条件について
は後述する。
[0019] In addition, under the processing conditions, 0 W/c was applied to the substrate side electrode.
There is a case where a high frequency is applied with an RF power of m2, but the conditions are different from the conventional device that applies a high frequency only to the counter electrode. The reason for this is that in the conventional device that applies high frequency only to the counter electrode, the substrate side electrode is at ground potential (Figure 3), but in the device used in the present invention that can also apply high frequency to the substrate side electrode, This is because it is grounded via a high frequency matching box (Fig. 2). (The matching box generally has a variable capacitor, etc., so the substrate side electrode is not grounded.) In the hydrogen plasma treatment of the present invention, which uses a device that can apply high frequency waves to the substrate side electrode, only the conventional counter electrode can be used. Compared to hydrogen plasma treatment using a device that applies high frequency, hydrogen ions and hydrogen radicals can be selectively diffused into polycrystalline silicon, and the Vg-Id characteristic shift (threshold voltage It is excellent in that the amount of shift) can be reduced. An important variable in this case is the potential VDC of the substrate-side electrode, and detailed conditions will be described later.

【0020】基板側電極にも高周波を印加できる装置を
用いた本発明の水素プラズマ処理では、図2の基板側電
極マッチングボックス306内の可変コンデンサ等によ
り基板側電極の接地電位に対する交流インピーダンスを
変えることが可能であるので基板側電極に高周波を印加
しなくても(基板側電極に0W/cm2のRFパワーで
高周波を印加する場合でも)前記電位VDCを制御する
ことができる。また、対向電極マッチングボックス30
4および基板側電極マッチングボックス306の内部の
回路構造は、図2及び図3に於ける回路構造に限定され
るものではない。
In the hydrogen plasma treatment of the present invention using a device capable of applying high frequency waves to the substrate side electrode, the alternating current impedance of the substrate side electrode with respect to the ground potential is changed using a variable capacitor or the like in the substrate side electrode matching box 306 in FIG. Therefore, the potential VDC can be controlled without applying high frequency to the substrate side electrode (even when applying high frequency to the substrate side electrode with RF power of 0 W/cm2). In addition, the counter electrode matching box 30
4 and the circuit structure inside the substrate side electrode matching box 306 are not limited to the circuit structure in FIGS. 2 and 3.

【0021】高周波を印加する基板側電極や対向電極か
ら交流インピーダンスを介して接地されている構造であ
ることが重要である。水素プラズマ処理後にソース領域
及びドレイン領域のコンタクト電極108を形成すれば
薄膜トランジスタが完成する(図1(e))。該コンタ
クト電極材料としてはAl、Cr、Ni等の金属材料が
用いられている。本発明により形成した多結晶シリコン
TFT(poly−SiTFT)の電界効果易動度はN
chTFTで50cm2/V・s(減圧CVD法590
℃で多結晶シリコンを形成した場合)〜160cm2/
V・s(プラズマCVD法で成膜した非晶質シリコンを
600℃で約17時間固相成長させて多結晶シリコンを
形成した場合)となり、水素ガス雰囲気中でアニールし
ただけの場合(〜10cm2/V・s)と比べて大幅な
特性向上が為された。
[0021] It is important that the structure is such that the substrate-side electrode and counter electrode to which high frequency is applied are grounded via AC impedance. After hydrogen plasma treatment, a thin film transistor is completed by forming contact electrodes 108 in the source and drain regions (FIG. 1(e)). Metal materials such as Al, Cr, and Ni are used as the contact electrode material. The field effect mobility of the polycrystalline silicon TFT (poly-SiTFT) formed according to the present invention is N
chTFT: 50 cm2/V・s (low pressure CVD method 590
When polycrystalline silicon is formed at ℃)~160cm2/
V・s (when polycrystalline silicon is formed by solid-phase growth of amorphous silicon deposited by plasma CVD method at 600°C for about 17 hours), and when it is simply annealed in a hydrogen gas atmosphere (~10 cm2 /V・s), the characteristics were significantly improved.

【0022】また本発明により形成したpoly−Si
TFTのON電流はトランジスタサイズL/W=5μm
/10μmのNchTFTで400μA、OFF電流は
同じサイズのNchTFTで10〜30fAであり、ス
イング(サブスレッシュホールド領域に於けるVg−I
d特性曲線の傾きの逆数)は0.35V/dec.であ
った。また、従来の水素プラズマ処理によるTFTのス
レッシュホールド電圧のシフト量が−2V〜−5Vであ
る(図5)のに対し、基板側電極にも高周波を印加でき
る装置を使用した本発明の水素プラズマ処理では該シフ
ト量は−1V以下であった(図4)。
[0022] Furthermore, poly-Si formed according to the present invention
The ON current of TFT is transistor size L/W = 5μm
/10 μm Nch TFT is 400 μA, the OFF current is 10 to 30 fA for the same size Nch TFT, and the swing (Vg-I in the subthreshold region)
d) is 0.35V/dec. Met. In addition, while the shift amount of the TFT threshold voltage due to conventional hydrogen plasma treatment is -2V to -5V (Fig. 5), the hydrogen plasma treatment of the present invention uses a device that can also apply high frequency waves to the substrate side electrode. In the treatment, the shift amount was −1 V or less (FIG. 4).

【0023】尚、従来の水素プラズマ処理によるTFT
のスレッシュホールド電圧のシフト等のダメージは、例
えば50cm×50cm以上の広い電極面積を持つ大型
の量産装置で多発する傾向にあるが、基板側電極にも高
周波を印加できる装置を使用した本発明の水素プラズマ
処理では、前述の広い電極面積を持つ装置であってもダ
メージを皆無にすることができる。
[0023] It should be noted that TFTs by conventional hydrogen plasma treatment
Damage such as a shift in the threshold voltage tends to occur frequently in large-scale mass production equipment that has a wide electrode area of 50 cm x 50 cm or more. Hydrogen plasma treatment can completely eliminate damage even to the above-mentioned device having a wide electrode area.

【0024】次に、従来の水素プラズマ処理で発生し易
いプラズマダメージによる不良が、基板側電極にも高周
波を印加できる装置を使用した本発明の水素プラズマ処
理では発生しにくい理由に関して述べる。水素プラズマ
処理で発生するダメージの原因は、今のところ明らかで
はないが、プラズマ雰囲気中に浸されたことにより基板
にチャージアップが起こり、ゲート−チャネル間に電圧
がかかった状態になり、また基板温度が300℃程度と
比較的高いため、疑似的にBTストレス(バイアス及び
温度ストレス)が加わるために、TFTに不良が生じた
とするモデルが現象をよく説明している。このモデルに
則ると、基板側電極にも高周波を印加できる装置を使用
した本発明の水素プラズマ処理では基板側電極の電位V
DCを基板側電極に高周波を印加することにより制御す
ることが可能であるので、基板にチャージアップが生じ
ないようにすることが出来ると考えられる。そのため従
来の水素プラズマ処理で発生する前述のスレッシュホー
ルド電圧のシフト等の不良を皆無とすることが出来るの
である。
Next, we will discuss the reason why defects due to plasma damage, which tend to occur in conventional hydrogen plasma processing, are less likely to occur in the hydrogen plasma processing of the present invention, which uses a device that can also apply high frequency waves to the substrate side electrode. The cause of damage caused by hydrogen plasma processing is not clear at present, but being immersed in the plasma atmosphere causes a charge-up on the substrate, which creates a state in which voltage is applied between the gate and channel, and the substrate The phenomenon is well explained by a model in which a defect occurs in the TFT due to pseudo BT stress (bias and temperature stress) being applied due to the relatively high temperature of about 300°C. According to this model, in the hydrogen plasma treatment of the present invention using a device that can apply high frequency waves to the substrate side electrode, the potential of the substrate side electrode V
Since DC can be controlled by applying a high frequency to the substrate side electrode, it is considered possible to prevent charge-up from occurring on the substrate. Therefore, defects such as the shift of the threshold voltage mentioned above that occur in conventional hydrogen plasma processing can be completely eliminated.

【0025】前記電位VDCは従来の対向電極のみに高
周波を印加する装置を用いた水素プラズマ処理に於いて
は恒に0Vであるが、基板側電極にも高周波を印加でき
る装置を用いた本発明の水素プラズマ処理に於いては可
変である。前記電位VDCを10V〜−100Vとする
ことにより水素プラズマ処理後のTFTのスレッシュホ
ールド電圧のシフト量を−1V以下とすることができる
。また、前記電位VDCを5V〜−50Vとすると特に
望ましく、この場合スレッシュホールド電圧のシフトは
ほとんど見られない。前記電位VDCを−100V以下
とすることにより更にスレッシュホールド電圧のシフト
量は減ると考えられるが、この時は電極がスパッタされ
てしまう可能性が高くなるため、余り望ましくない。
The potential VDC is always 0 V in conventional hydrogen plasma processing using a device that applies high frequency only to the opposing electrode, but the present invention uses a device that can apply high frequency to the substrate side electrode as well. The hydrogen plasma treatment is variable. By setting the potential VDC to 10V to -100V, the shift amount of the threshold voltage of the TFT after hydrogen plasma treatment can be set to -1V or less. Further, it is particularly preferable that the potential VDC is set to 5 V to -50 V, and in this case, almost no shift in the threshold voltage is observed. It is thought that the shift amount of the threshold voltage can be further reduced by setting the potential VDC to -100V or less, but this is not so desirable because the possibility that the electrode will be sputtered increases.

【0026】本実施例では、容量結合型の平行平板型の
プラズマ発生装置を用いた水素プラズマ処理の場合につ
いて説明したが、該装置の形状はこれに限定されるもの
ではない。水素プラズマ処理を施す被処理材を支える電
極に高周波を印加できる装置を用いた点が重要である。 尚、水素プラズマ処理は層間絶縁膜積層後ではなく、コ
ンタクト電極形成後に行ってもかまわない。
In this embodiment, a case has been described in which hydrogen plasma processing is performed using a capacitively coupled parallel plate type plasma generator, but the shape of the apparatus is not limited to this. It is important to use a device that can apply high frequency waves to the electrodes that support the material to be treated with hydrogen plasma. Note that the hydrogen plasma treatment may be performed not after the interlayer insulating film is laminated, but after the contact electrode is formed.

【0027】以上述べたように、本発明を応用すれば、
ON電流が大きくOFF電流が小さくサブスレッシュホ
ールド電圧の立ち上がりが急峻なトランジスタを、プラ
ズマダメージ等による不良を皆無にして製造可能となる
As described above, if the present invention is applied,
A transistor with a large ON current, a small OFF current, and a steep subthreshold voltage rise can be manufactured without any defects due to plasma damage or the like.

【0028】本発明の応用としては、例えば、非結晶シ
リコンを素子材としたTFTによって構成された液晶表
示パネル、密着型イメージセンサ、ドライバ内蔵型のサ
ーマルヘッド、有機系EL等を発光素子としたドライバ
内蔵型の光書き込み素子や表示素子、三次元IC等が考
えられる。本発明を用いることで、これらの素子の高速
化、高解像度化等の高性能化が実現される。
Applications of the present invention include, for example, liquid crystal display panels constructed of TFTs using amorphous silicon as an element material, contact type image sensors, thermal heads with built-in drivers, organic EL, etc. as light emitting elements. Possible devices include an optical writing element with a built-in driver, a display element, and a three-dimensional IC. By using the present invention, higher performance such as higher speed and higher resolution of these elements can be realized.

【0029】尚、図1では、poly−SiTFT製造
工程に本発明を適用した場合を例としたが、本発明はこ
れに限定されるものではない。本発明は、チャネル領域
の少なくとも一部が多結晶である絶縁ゲート型電界効果
トランジスタ全てに対し有効である。また、チャネル領
域の少なくとも一部が微結晶である絶縁ゲート型トラン
ジスタや、チャネル領域の一部がスパッタ法や蒸着法等
で形成した水素化の不十分な非晶質半導体からなるトラ
ンジスタに於いても有効である。
Although FIG. 1 shows an example in which the present invention is applied to a poly-SiTFT manufacturing process, the present invention is not limited to this. The present invention is effective for all insulated gate field effect transistors in which at least a portion of the channel region is polycrystalline. In addition, in insulated gate transistors in which at least part of the channel region is made of microcrystals, and in transistors in which part of the channel region is made of an insufficiently hydrogenated amorphous semiconductor formed by sputtering or vapor deposition, etc. is also valid.

【0030】また、チャネル領域が単結晶であっても、
三次元ICのように再結晶化若しくは固相成長させたシ
リコン層に素子を形成する場合、結晶内に生じ易い、亜
粒界などの欠陥を、本発明に基づく半導体装置の製造方
法で、ダングリングボンドの終端化を行なうと特性の向
上に効果がある。
Furthermore, even if the channel region is a single crystal,
When forming an element in a silicon layer that has been recrystallized or grown in a solid phase, such as in a three-dimensional IC, defects such as sub-grain boundaries, which tend to occur in crystals, can be eliminated by the semiconductor device manufacturing method based on the present invention. Terminating the ring bond is effective in improving the characteristics.

【0031】更に、HBT(ヘテロバイポーラトランジ
スタ)等のヘテロ接合界面の欠陥密度の低減に対しても
本発明は有効である。特に、ヘテロ接合を形成する二つ
の半導体層のうちの少なくとも一方が非単結晶半導体よ
りなる場合には、本発明による水素化処理により、膜中
及び界面の欠陥を同時に低減することが出来る。
Furthermore, the present invention is also effective in reducing the defect density at the heterojunction interface of HBTs (hetero-bipolar transistors) and the like. In particular, when at least one of the two semiconductor layers forming a heterojunction is made of a non-single crystal semiconductor, the hydrogenation treatment according to the present invention can simultaneously reduce defects in the film and at the interface.

【0032】また、非単結晶半導体を素子材とした太陽
電池・光センサやバイポーラトランジスタ、静電誘導ト
ランジスタをはじめとして、本発明は幅広く半導体プロ
セス全般に応用することが出来る。
Further, the present invention can be widely applied to semiconductor processes in general, including solar cells, optical sensors, bipolar transistors, and static induction transistors using non-single crystal semiconductors as element materials.

【0033】[0033]

【発明の効果】以上述べたように、本発明によればpo
ly−SiTFT等のチャネル領域の少なくとも一部が
非単結晶半導体よりなる絶縁ゲート型電界効果トランジ
スタの高性能化を、プラズマダメージによる不良もなく
実現できる。また、本発明は絶縁ゲート型電界効果トラ
ンジスタに限らず、半導体プロセス全般に亘り広く応用
することが出来、その効果はきわめて大きい。
[Effects of the Invention] As described above, according to the present invention, the po
It is possible to improve the performance of an insulated gate field effect transistor, such as a ly-SiTFT, in which at least a portion of the channel region is made of a non-single crystal semiconductor, without causing defects due to plasma damage. Further, the present invention can be widely applied not only to insulated gate field effect transistors but also to semiconductor processes in general, and its effects are extremely large.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】(a)〜(e)は、本発明の実施例に於ける半
導体装置の製造方法の一例を示す工程断面図である。
FIGS. 1A to 1E are process cross-sectional views showing an example of a method for manufacturing a semiconductor device in an embodiment of the present invention.

【図2】本発明の実施例に於ける対向電極にばかりでな
く基板側電極にも高周波を印加できる平行平板型水素プ
ラズマ処理装置の電気的な接地関係を示す図である。
FIG. 2 is a diagram showing the electrical grounding relationship of a parallel plate type hydrogen plasma processing apparatus that can apply high frequency not only to a counter electrode but also to a substrate side electrode in an embodiment of the present invention.

【図3】従来の対向電極のみに高周波を印加できる平行
平板型水素プラズマ処理装置の電気的な接地関係を示す
図である。
FIG. 3 is a diagram showing the electrical grounding relationship of a conventional parallel plate type hydrogen plasma processing apparatus that can apply high frequency only to a counter electrode.

【図4】本発明の実施例に於ける対向電極にばかりでな
く基板側電極にも高周波を印加できる平行平板型水素プ
ラズマ処理装置を用いて水素プラズマ処理を施したNc
hTFTのVg−Id特性図である。
FIG. 4: Nc subjected to hydrogen plasma treatment using a parallel plate type hydrogen plasma treatment apparatus that can apply high frequency not only to the counter electrode but also to the substrate side electrode in the embodiment of the present invention.
It is a Vg-Id characteristic diagram of hTFT.

【図5】従来の対向電極のみに高周波を印加できる平行
平板型水素プラズマ処理装置を用いて水素プラズマ処理
を施したNchTFTのVg−Id特性図である。
FIG. 5 is a Vg-Id characteristic diagram of an Nch TFT subjected to hydrogen plasma treatment using a conventional parallel plate type hydrogen plasma treatment apparatus capable of applying high frequency only to a counter electrode.

【符号の説明】[Explanation of symbols]

100  絶縁性支持層 101  非単結晶シリコン薄膜 102  ゲート酸化膜 103  ゲート電極 104  ソース領域 105  ドレイン領域 106  チャネル領域 107  層間絶縁膜 108  コンタクト電極 301  対向電極 302  基板側電極 303  チェンバー 304  対向電極マッチングボックス305  対向
電極高周波電源 306  基板側電極マッチングボックス307  基
板側電極高周波電源
100 Insulating support layer 101 Non-single crystal silicon thin film 102 Gate oxide film 103 Gate electrode 104 Source region 105 Drain region 106 Channel region 107 Interlayer insulating film 108 Contact electrode 301 Counter electrode 302 Substrate side electrode 303 Chamber 304 Counter electrode matching box 305 Opposite Electrode high frequency power supply 306 Substrate side electrode matching box 307 Substrate side electrode high frequency power supply

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  絶縁ゲート型電界効果トランジスタの
チャネル領域の少なくとも一部が非単結晶半導体からな
る半導体装置の製造方法に於いて、多結晶半導体薄膜を
形成する工程と、前記多結晶半導体薄膜にプラズマ発生
装置の基板側電極と相対電極との両方に高周波を印加し
て生成した水素プラズマにより水素プラズマ処理を施す
工程とを少なくとも含むことを特徴とする半導体装置の
製造方法。
1. A method for manufacturing a semiconductor device in which at least a portion of a channel region of an insulated gate field effect transistor is made of a non-single crystal semiconductor, comprising the steps of: forming a polycrystalline semiconductor thin film; 1. A method for manufacturing a semiconductor device, comprising at least the step of performing hydrogen plasma treatment using hydrogen plasma generated by applying high frequency to both a substrate-side electrode and a counter electrode of a plasma generator.
JP07922591A 1991-04-11 1991-04-11 Method for manufacturing semiconductor device Expired - Lifetime JP3239372B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP07922591A JP3239372B2 (en) 1991-04-11 1991-04-11 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP07922591A JP3239372B2 (en) 1991-04-11 1991-04-11 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH04313271A true JPH04313271A (en) 1992-11-05
JP3239372B2 JP3239372B2 (en) 2001-12-17

Family

ID=13683967

Family Applications (1)

Application Number Title Priority Date Filing Date
JP07922591A Expired - Lifetime JP3239372B2 (en) 1991-04-11 1991-04-11 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP3239372B2 (en)

Also Published As

Publication number Publication date
JP3239372B2 (en) 2001-12-17

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