JPH04323740A - Wdt circuit - Google Patents

Abstract

PURPOSE:To easily apply the WDT circuit to various systems by continuing the processing without shutdown in the case of a slight abnormality and sufficiently securing abnormality information regardless of reset of a CPU. CONSTITUTION:An up/down counter 10 is provided which can vary the abnormality monitor time based on write data of the CPU; and when the duration of access from the CPU exceeds the abnormality monitor time of the up/down counter 10, operation abnormality is decided to send a count value zero signal S2, and an NMI request signal is sent from an NMI request signal generating means 13 to the CPU. When the CPU performs access within a prescribed time after reception of the NMI request signal, the NMI request is released; but it does not perform access then, a reset signal is sent from a reset signal generating means 14 to the CPU to reset the CPU.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a central processing unit (hereinafter referred to as CPU) of a computer used in various technical fields.
The present invention relates to a WDT circuit that monitors the operating state of a device (referred to as ``WDT''), and particularly relates to a WDT circuit that has flexibility in monitoring time.

0002

[Prior art] WDT (watchdog timer: wat
The ch dog timer) circuit resets a counter at fixed intervals when the CPU is operating normally, and detects that the program is abnormal or running out of control when the access time from the CPU exceeds a fixed cycle. be. Normally, in real-time processing and control systems, a WDT circuit is used to report an overflow signal to the outside after a certain predetermined time has elapsed to ensure system switching and system safety. In addition, this WDT circuit interrupts the monitoring program when the first overflow occurs, and when an overflow occurs again after a certain period of time, it reports this to the outside, and distinguishes between abnormalities in the application program and abnormalities in the system program. things are being done.

By the way, the conventional WDT circuit of this type is
As mentioned above, the access time from the CPU is fixed in advance by hardware, and when there is no access from the CPU to the WDT port even after the access time has elapsed, it is impossible to mask the CPU by resetting it or prohibiting it by software control. Interrupt NMI (non mask
ableinterrupt) and then forcefully resets the CPU after a certain period of time has elapsed.

0004

[Problem to be solved by the invention] However, in the above WDT circuit, the WDT monitoring time (access time) is set in advance.
Since this method is fixed, it lacks flexibility, and is not necessarily suitable for system-based operation processing, depending on the software processing method.

[0005] Moreover, even if an NMI interrupt is applied,
Since the CPU is forcibly reset after a certain period of time, it is necessary to start shutdown processing immediately after the NMI occurs, and furthermore, since the shutdown processing time is fast, there is a limit to how much abnormality information can be left.

The present invention has been made in view of the above-mentioned circumstances, and provides a WDT circuit that can continue processing without shutting down in response to a minor abnormality, and that can secure sufficient time to leave abnormality information. The purpose is to provide

[0007]

[Means for Solving the Problems] In order to solve the above problems, the WDT circuit according to the present invention determines that the CPU is malfunctioning when the CPU does not write data for a certain period of time. , a time setting means for presetting an abnormality monitoring time based on write data sent from the CPU; and an operation abnormality is determined when an access from the CPU exceeds the abnormality monitoring time preset by the time setting means. Determine the CP
NMI request signal generating means for sending an NMI request signal to U, and when there is no access within a predetermined time after the NMI request signal generating means generates the NMI request signal, the C
This configuration includes reset signal generation means for sending a reset signal to the PU.

[0008]

[Operation] Therefore, by taking the above-mentioned measures, the present invention can set any abnormality monitoring time by writing data from the CPU, and can also set the abnormality monitoring time when a WDT abnormality occurs.
By sending an NMI request signal to the PU, restarting WDT monitoring if there is an access from the CPU within a predetermined time, and resetting the CPU only when there is no access from the CPU after the predetermined time elapses. Processing can be continued without shutting down due to an abnormality,
Furthermore, even when actually resetting the CPU, sufficient abnormality information can be secured.

[0009]

Embodiment An embodiment of the present invention will be described below with reference to FIG. In the figure, reference numeral 10 denotes an up/down counter (ALS191) as a time setting means that can arbitrarily preset the WDT monitoring time. Reference clock signal S1 and WDT
When the port select signal S5 is introduced and the preset value is counted down every time the reference clock signal S1 rises and reaches zero, a count value zero signal S is sent from the MIN terminal.
2, and outputs a ripple clock signal S6 from the RC terminal at the falling edge of the reference clock signal S1 with the count value set to zero.

Reference numeral 12 denotes a WDT permission determination circuit using, for example, a D-FF (ALS74), which outputs a WDT prohibition/permission signal S3 depending on the presence or absence of the WDT port select signal S5. A certain WDT prohibition signal or WDT enable signal S3 is activated by a subsequent AND logic circuit (
The signal is sent to the NMI request signal generating means 13 such as ALS08). When this NMI request signal generation means 13 receives the WDT permission signal S3 from the WDT permission determination circuit 12,
Count value zero signal S from up/down counter 10
2, it has a function of generating an NMI request signal S4 to the CPU based on the NMI request signal S4. 14 is a D-FF, for example, which outputs the CPU reset signal S7 at the rising edge of the ripple clock signal S6 output from the RC terminal of the up/down counter 10.
This is a reset signal generation means using, etc.

Next, the operation of the WDT circuit as described above will be explained with reference to FIG. First, when the CPU sends the WDT port select signal S5 to the up/down counter 10 and the CPU writes data to the up/down counter 10 via the data bus 11, the up/down counter 10 receives the data. The WDT monitoring time, that is, the preset value, is set according to the
Further, a WDT permission signal S3 is sent from the WDT permission determination circuit 12.
is sent.

In this state, when the reference clock signal S1 is input while the CPU is executing a program, the up/down counter 10 executes a down operation of the preset value at the rising edge of the clock every time it receives the reference clock signal S1. do. Here, when the preset value, that is, the count value becomes zero due to the down operation, the up/down counter 10 outputs a count value zero signal S2 from the MIN (minimum) terminal. Therefore, the NMI request signal generating means 13 receives the count value zero signal S2 and outputs the C
Sends an NMI request signal S4 to the PU.

After receiving the NMI request signal S4, the CPU accesses the WDT port in the processing program as shown in section A in FIG. If NM can be written, the NM
The I request signal S4 disappears and returns to normal, and along with this, R
The ripple clock signal S6 is not output from the C terminal, and therefore the reset signal S7 is not output from the reset signal generating means 14 to the CPU. Therefore, this WDT circuit is determined to have a slight abnormality, and abnormality monitoring continues.

However, as shown in section B of FIG.
If there is no response from the CPU to the MI request signal S4, the reference clock signal S
After one half cycle, that is, the time from the rising edge to the falling edge of the clock, the ripple clock signal S6 is sent from the RC terminal of the up/down counter 10, and the reset signal generating means 14 is activated at the rising edge of the ripple clock signal S6. Sends a reset signal S7 from the CPU
This is a forced reset.

Therefore, according to the configuration of the embodiment as described above, the WDT monitoring time can be arbitrarily changed by a simple method of accessing the WDT port from the CPU and writing data, and this makes it possible to use it in various systems. can. Furthermore, after the NMI request signal S4 is generated after the WDT monitoring time has elapsed, if the CPU accesses the WDT port within the half cycle period of the reference clock signal S1, processing can be continued without shutting down. In addition to re-extension, it is possible to easily prohibit WDT monitoring.

Note that in the above embodiment, the NMI request signal S
Although the time for generating the reset signal S7 after the generation of the clock signal S7 is defined as the half cycle time of the reference clock signal, it goes without saying that this time is not specific. In addition, the present invention can be implemented with various modifications without departing from the gist thereof.

[0017]

[Effects of the Invention] As explained above, according to the present invention, W
You can freely change the DT monitoring time, and if you access the WDT port from the CPU within a certain time after generating the NMI request signal, you can avoid resetting the CPU.
Processing can be continued without shutting down when a minor abnormality occurs, and sufficient abnormality information can be secured even when resetting the CPU.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an embodiment of a WDT circuit according to the present invention.

FIG. 2 is a timing diagram illustrating the operation of the WDT circuit in FIG. 1.

[Explanation of symbols]

10...up/down counter, 11...data bus, 1
2...WDT permission determination circuit, 13...NMI request signal generation means, 14...Reset signal generation means, S1...Reference clock signal, S2...Count value zero signal, S3...WDT prohibition/permission signal, S4...NMI request signal, S5 ...WDT port select signal, S6...ripple clock signal, S7...reset signal.

Claims (1)

[Claims] 1. In a WDT circuit that determines that the CPU is malfunctioning when data is not written by the CPU for a certain period of time, an abnormality monitoring time is preset based on write data sent from the CPU. NMI request signal generating means that determines that there is an operational abnormality and sends an NMI request signal to the CPU when the access from the CPU exceeds the abnormality monitoring time preset by the time setting means; This NMI
A WDT circuit comprising: a reset signal generating means for sending a reset signal to the CPU when there is no access within a predetermined time after generating the NMI request signal from the request signal generating means.