JP2613986B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly to a non-maskable interrupt.
(hereinafter referred to as NMI).

[0002]

2. Description of the Related Art Conventionally, in an information processing apparatus having an NMI, NMI request information due to a hardware error such as a memory parity error and NMI request information other than a hardware error such as an emergency processing request at the time of system shutdown are stored. Is a CPU (Central Processing Un
it). for that reason,
Only by the program executed after the CPU detects the NMI information, the operation of the device other than the CPU and the memory refresh can be stopped to perform the NMI processing.

FIG. 3 is a block diagram of a conventional information processing apparatus of this type. As shown in FIG. 3, an NMI request signal 5 caused by a hardware error and an NMI request signal 6 caused by a factor other than a hardware error are input to the gate circuit 3. Then, the NMI request signal 7 for the CPU output from the gate circuit 3 is input to the CPU 1. NMI
After the request is generated and the NMI request 7 is accepted by the CPU 1, the CPU 1 performs an NMI process. When an instruction for disabling bus access right arbitration of devices other than the CPU and the memory refresh is executed by the NMI processing program, the CPU 1 performs I / O on the address bus 8 and the device 9.
Instructs the register circuit 4 to prohibit arbitration of bus access rights of devices other than the CPU and memory refresh.

If the I / O register circuit 4 is set to prohibit arbitration of bus access rights of devices other than the CPU and memory refresh, the I / O register circuit 4
Actively determines the bus access right arbitration inhibition signal 10 by the program and sends it to the bus access right arbitration circuit 2. This makes it possible to stop the operation of the device other than the CPU and the memory refresh, and perform the NMI process of the CPU for the hardware abnormality.

FIG. 4 is a diagram showing an example of a state from a request of a bus request device and an NMI to a service in a conventional information processing apparatus. In the example of FIG. 4, it is assumed that an NMI due to a hardware error has occurred during a memory refresh and a bus request conflict between DMA1, DMA2, and the CPU.

Referring to FIG. 4, DMA1 is serviced, and then DMA2 is serviced. And D
A hardware error has occurred while MA2 is being serviced. However, DMA1 is serviced without the CPU being serviced because DMA1 is requesting a bus, and DMA2 is then serviced because DMA2 is requesting a bus. Thereafter, the CPU is serviced and error processing by the NMI is started, but the NMI processing is immediately suspended due to the occurrence of a memory refresh bus request, and the memory refresh is serviced. When memory refresh is serviced, DMA1 is serviced because DMA1 is requesting the bus again, and then the CPU is serviced again. Then, the NMI process is resumed, and the bus access right arbitration of devices other than the CPU and the memory refresh is prohibited by the program. Hereafter, C
The operation of the device other than the PU and the memory refresh is stopped, and the NMI processing of the CPU for the hardware abnormality is performed.

[0007]

In the above-mentioned conventional information processing apparatus, the operation of the CPU and devices other than the memory refresh is stopped by a program executed after the CPU detects the NMI, and the CPU performs the operation for the hardware abnormality. Since NMI processing is performed, if an NMI due to a hardware error occurs during processing of a device other than the CPU, C
There is a problem in that the NMI processing of the PU is executed, and the prohibition of arbitration of bus access rights of devices other than the CPU and the memory refresh is delayed.

[0008] This delay increases the damage caused by malfunction of the system due to hardware abnormality.

Accordingly, an object of the present invention is to provide an information processing apparatus capable of reducing damage caused by malfunction of a system due to hardware abnormality.

[0010]

An information processing apparatus according to the present invention inputs an NMI request signal caused by a hardware abnormality to a bus access right circuit and automatically generates an NMI request caused by a hardware abnormality. It is characterized in that arbitration of bus access rights of devices other than the CPU and the memory refresh is prohibited.

[0011]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

Referring to FIG. 1, an information processing apparatus according to the present embodiment includes a CPU 1 and an NM for causing a hardware abnormality.
A bus access right arbitration circuit 2 capable of inputting an I request signal 5 and prohibiting bus access right arbitration of devices other than the CPU and the memory refresh related device; an NMI request signal 5 caused by a hardware abnormality; A gate circuit 3 for receiving an NMI request signal 6 due to a cause other than a hardware abnormality and outputting an NMI request signal 7 to the CPU 1;

An NMI request signal 5 caused by a hardware error and an NMI request signal 6 caused by a factor other than a hardware error are input to the gate circuit 3. Then, the NMI request signal 7 to the CPU output from the gate circuit 3
Is input to the CPU 1. The NMI request signal 5 caused by a hardware abnormality is transmitted to the bus access right arbitration circuit 2.
NMI that is also input to the
The request is one of the factors for prohibiting arbitration of bus access rights of devices other than the CPU and the memory refresh.

When an NMI request is generated due to a hardware error, the bus access right arbitration circuit 2 automatically
Bus access right arbitration of devices other than the PU and memory refresh is prohibited. The bus access right arbitration circuit 2 does not automatically prohibit the bus access right arbitration of devices other than the CPU and the memory refresh when an NMI request is generated due to a factor other than a hardware abnormality.

After an NMI request is generated and the NMI request is accepted by the CPU 1, the CPU 1 performs an NMI process.
When an NMI request occurs due to a hardware error, C
With the operation of the device other than the PU and the memory refresh stopped when a hardware error occurs, the CPU can quickly perform the NMI process for the hardware error. By doing so, damage due to malfunction of the system due to hardware abnormality can be reduced.

FIG. 2 is a diagram showing an example of a state from the generation of a request for a bus request device and the NMI to the service in the information processing apparatus according to one embodiment of the present invention. In the example of FIG. 2, it is assumed that an NMI due to a hardware error has occurred during a memory refresh and a bus request conflict between DMA1, DMA2, and the CPU.

Referring to FIG. 2, DMA1 is serviced, and then DMA2 is serviced. And D
A hardware error has occurred while MA2 is being serviced. At this time, N
When the MI occurs, the bus access right arbitration is automatically prohibited. As a result, the CPU is serviced without servicing the bus requests of DMA1 and DMA2, and error processing by the NMI is started. Thereafter, the NMI process is interrupted due to the occurrence of a memory refresh bus request.
After the memory refresh is serviced, the CPU is serviced again. Then, the NMI process is restarted.

[0018]

As described above, according to the present invention, the arbitration of the bus access right of the device other than the CPU and the memory refresh is automatically inhibited by the generation of the NMI request due to the hardware abnormality, thereby the hardware abnormality is prevented. This has the effect of reducing the damage caused by system malfunctions caused by this.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of an information processing apparatus according to the present invention.

FIG. 2 is a diagram illustrating an example of a state from a request generation of an NMI request to a service in an information processing apparatus according to an embodiment of the present invention.

FIG. 3 is a block diagram of a conventional information processing apparatus.

FIG. 4 is a diagram showing an example of a state of a conventional information processing apparatus from a bus request device and an NMI request generation to a service.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 CPU 2 Bus access right arbitration circuit 3 Gate circuit 4 I / O register circuit 5 NMI request signal caused by hardware abnormality 6 NMI request signal caused by other than hardware abnormality 7 NMI request signal to CPU 8 Address bus 9 Data bus 10 Bus access right arbitration inhibit signal by program

Claims (3)

(57) [Claims] An information processing apparatus for inputting a non-maskable interrupt request signal caused by a hardware error and a non-maskable interrupt request signal caused by a factor other than a hardware error to make a non-maskable interrupt request to a CPU. A non-maskable interrupt request signal caused by the hardware error is also input to the bus access right arbitration circuit, and the non-maskable interrupt request caused by the hardware error is automatically generated to cause the CPU and the memory refresh relationship to be reset. An information processing apparatus for prohibiting arbitration of bus access rights of devices other than devices. 2. A non-maskable interrupt request signal due to a hardware abnormality and a non-maskable interrupt request signal due to a cause other than the hardware abnormality are input to a gate circuit, and a non-maskable interrupt to the CPU is performed. 2. The information processing apparatus according to claim 1, wherein the information processing apparatus outputs a request signal. 3. A bus capable of receiving a CPU and a non-maskable interrupt request signal caused by a hardware abnormality and prohibiting arbitration of bus access rights of devices other than the CPU and devices related to memory refresh. An access right arbitration circuit and a non-maskable interrupt request signal caused by the hardware error and a non-maskable interrupt request signal caused by a factor other than the hardware error are input to generate a non-maskable interrupt request signal to the CPU. An information processing apparatus comprising: a gate unit for outputting.