JPH0432315A - Gate array circuit device - Google Patents

Abstract

PURPOSE:To reduce the development cost per a circuit module by providing plural circuit modules whose sum of input terminals and output terminals exceeds the number of input/output pads of a gate array and a selection means selecting a signal sent from the circuit modules to the device. CONSTITUTION:Both circuit modules 1, 2 have the number of input/output terminals almost equal to the number of input/output pads provided to a gate array. Then an output selector 10 and an input output selector 13 are provided and the number of the circuit modules capable of forming in one gate array is formed and which of the circuit modules is to be operated is selected in response to a selection signal fed externally. Thus, the circuit modules whose number is a limited number capable forming in one gate array are formed and the sum of input/output terminals in the circuit modules is in excess of the number of input/output pads of the gate array. Thus, the operating rate of the gate array is improved and the development cost of the gate array is reduced.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a gate array circuit device.

[Prior art and its problems] When using a so-called gate array in which transistors etc. are arranged in an array on a wafer in advance in a digital circuit, conventionally, for one circuit module containing such a gate array, I was creating one gate array. For example, in a gate array with 100 output pads, the number of input/output terminals provided in the circuit module must be 100 or less.

Due to such constraints, the usage rate of internal gates configured in a gate array is often low. Even when the usage rate is low, due to the characteristics of gate arrays,
There was a problem in that the development cost, including the mask cost, was not necessarily cheap.

The present invention has been made to solve these problems, and aims to reduce the development cost per circuit module by improving the utilization rate of internal gates.

[Means for Solving the Problems] The present invention provides a plurality of circuit modules that are provided in the same gate array and have a total number of input/output terminals exceeding the number of input/output pads of the gate array, and a circuit module that supplies input signals. and a selection means for selecting a signal to be sent out by any one circuit module. Has multiple circuit modifiers.

- Select one circuit module from the circuit module, supply an input signal to the selected circuit module, select an output signal sent by the selected circuit module from output signals of a plurality of circuit modules, and send it to the outside. In this way, the selection means acts to improve the utilization of the gate array, and -
This is working to reduce development costs per chip.

[Example] A first example showing an example of the gate anoy circuit device of the present invention.
In the figure, circuit module 1 and circuit module 2 are both circuit modules in which the number of input/output terminals is equal to the number of input/output pads provided in one gate array. Further, in this embodiment, for the sake of explanation, the number of input terminals 3a of the circuit module 1 is 0, the number of output terminals 4 of the module 1 is 10, the number of input terminals 3b of the circuit module 2 is 15, and the number of output terminals of the module 2 is 10. Assume that the number of 6s is 5.

The respective input terminals 3 a and 3 b of such circuit modules 1 and 2 are provided on the IC chip 100,
It is connected to input terminals 101 equal to the number of input terminals in circuit module l or 2.

That is, each input terminal 101 is connected to the circuit module l.
and 2 are connected to both input terminals 3 a, 3 b,
Further, as shown in the figure, an input terminal connected to the input terminal 101, for example, indicated by A, is connected to an input terminal 3a indicated by A in the circuit module 1, and also connected to the input terminal 3a indicated by A in the circuit module 1.
It is also connected to the input terminals having the same terminal number of the circuit modules 1 and 2, so that it is connected to the input terminal 3b shown at A.

According to the example described above, the input terminal 3b of the circuit module 2
The number of is 5 than the number of input terminals 3a of circuit module l.
Since there are many terminals, the number of input terminals 101 provided is 10.
It's a book. The remaining five input terminals in the circuit module 2 are adjusted by the input/output selector 13, which will be described in detail later.

The plurality of output terminals 4 of the circuit module I are each connected to one input terminal of a plurality of AND gates 5, and a select signal input terminal 102 is connected to the other input side of each AND gate 5 via an inverter 8. be done.

A plurality of output terminals 6 of the circuit module 2 are each connected to one input terminal of a plurality of AND gates 7, and a select signal input terminal 102 is connected to the other input side of each AND gate 7.

The output sides of such AND gates 5 and 7 are respectively connected to the input sides of a plurality of OR gates 9, and the output side of each OR gate 9 is connected to the IC chip 1.
It is connected to a plurality of output terminals 103 of 00. One output selector 10 is formed by one AND gate 5, one AND gate 7, and one OR gate 9 as described above,
Although not shown, a plurality of such output selectors 10 are formed. In this embodiment, the number of output selectors 10 to be formed is 5 since the number of output terminals 4 of the circuit module 1 is 10 and the number of output terminals 6 of the circuit module 2 is 5. . In addition, the remaining 5 of circuit module 1
For the output terminal 4 of the book, please refer to the input/output selector 1 which will be described in detail later.
Adjusted in 3.

The output selector 10 is a circuit that selects an output signal of either the circuit module 1 or 2 according to a digital signal of 1 or 0 supplied to the select signal input terminal 102. For example, a signal of 1 is supplied to the select signal input terminal 102. is supplied, a signal of 1 is supplied to the AND gate 7, and a signal is sent out from the AND gate 7.

That is, the circuit module 2 connected to the AND gate 7 is selected. On the other hand, when a signal of 0 is supplied to the select signal input terminal 102, this signal is inverted by the inverter 8, so that the circuit module 1 is selected, contrary to the above case.

Further, the output terminal 4 of the circuit module 1 is connected to the input/output terminal 104 of the IC chip 100 via an easy-to-use buffer 11. The output side of the inverter 8 is connected to the enable terminal of the buffer 11, and when an O signal is supplied to the select signal input terminal +02, that is, when the output signal of the circuit module 1 is selected, the buffer 11 is turned on. Then, the output signal of the circuit module 1 is sent to the input/output terminal 104. In this embodiment, the number of output terminals 4 of the circuit module 1 is five more than the number of output terminals 6 of the circuit module 2, and five output terminals are unprocessed by the output selector lO. 1 through 5 buffers 11 each. and are connected to five input/output terminals (in this case, output terminals) 104.

In addition, the input/output terminal 104 is a high enable buffer 1.
2 to the input terminal 14 of the circuit module 2. Note that the select signal input terminal 102 is connected to the enable terminal of the buffer 12, and the select signal input terminal 1
When a signal of 1 is supplied to 02, that is, when the output signal of the circuit module 2 is selected, the buffer 12 is turned on.

In the case of this embodiment, the input terminal 3a of the circuit module 1
The number of input terminals 3b of circuit module 2 is 5 than the number of
Since there are many buffers, five buffers 12 are provided, and five input/output terminals (input terminals in this case) 104 are connected to the circuit module 2 via the buffers 12.

Further, the above component buffers 11 and 12 form an input/output selector 13. As is clear from the above description, the input/output selector 13 is a circuit that selects an input terminal or an output terminal in order to match the numbers of input terminals or output terminals when the circuit modules 1 and 2 have different numbers of input terminals or output terminals. Further, in FIG. 1, a plurality of sets of input/output selectors 13 are provided, as is clear from the above description, although only one set is shown. Further, in the above example, the number of buffers 11 and 12 is five each, and the output side of buffer 12 is connected to circuit module 2, but this is not limited to this, and similarly, FIG. 1 is also an example. This is what is shown.

The operation of the gate array circuit device configured in this manner will be described below.

For example, in order to operate circuit module 1 and obtain its output signal, a signal necessary for the operation of circuit module 1 is supplied from input terminal 101, and an output signal from circuit module 1 is supplied to one input terminal of AND gate 1-5. , while AND
The output signals that cannot be supplied to the gate 5 are supplied to the buffer 11. On the other hand, in order to operate the circuit module 2 and obtain its output signal, the signals necessary for the operation of the circuit module 2 are supplied from the input terminal 101 and the input/output terminal 104, and the output signal from the circuit module 2 is supplied to one input of the AND gate 7. Supplied to the terminal.

Therefore, when supplying a necessary signal to the circuit module l and obtaining a resultant signal, a signal of 0 is supplied to the select signal input terminal 102, and this signal of O is passed through the inverter 8 to other than the AND gate 5. input terminal and buffer 1
Since the signal 1 is supplied to the enable terminal 1,
AND gate 5 and buffer 11 are turned on, and the output signal of circuit module I is sent to output terminal 103 via OR gate 9, and also sent from buffer 11 to input/output terminal 104. On the other hand, when supplying the necessary signals to the circuit module 2 and obtaining the resulting signal, by supplying the signal 1 to the select signal input terminal 102, the AN
Since a signal of 1 is supplied to the other input terminal of the D gate 7, the AND gate 7 is turned on and the output signal of the circuit module 2 is sent to the output terminal 103 via the OR gate 9.

As explained above, since both circuit modules 1 and 2 have approximately the same number of input/output terminals as the number of input/output pads provided in the gate array, conventionally
Is it necessary to create two gate arrays, or is it necessary to provide an output selector IO and an input/output selector 13, form as many circuit modules as possible in one gate array, and operate one of these circuit modules? is selected according to a selection signal supplied from the outside, so that up to the maximum number of circuit modules that can be formed in one gate array can be formed in one gate array. Since the total number of input/output terminals can exceed the number of input/output pads of the gate array,
The utilization rate of the gate array can be improved. Therefore, the development cost of the gate array can be reduced, and since a plurality of gate arrays are used, the cost per chip can be reduced due to the advantage of mass production.

In the above example, there were two circuit modules installed in the IC chip, but if the number of circuit modules is more than that,
For example, FIG. 2 shows the configuration of the output selector and input/output selector in four cases. For the sake of explanation, in this example, the number of output terminals of the circuit modules 51 and 52 is greater than the number of output terminals of the circuit modules 53 and 54, and the number of input terminals of the circuit modules 51 and 52 is greater than the number of output terminals of the circuit modules 53 and 54.
As an example, the number of input terminals is smaller than 54.

The output side of the circuit module 51 is connected to one input terminal of the AND gate 21, and the output side of the circuit module 52 is connected to one input terminal of the AND gate 22.
The output side of the circuit module 53 is connected to one input terminal of the AND gate 24, and the output side of the circuit module 53 is connected to one input terminal of the AND gate 24.
The output side of 4 is connected. AND gate 21 like this
The output sides of 24 to 24 are connected via an OR gate 25 to an output terminal 26.

Further, as mentioned above, in this example, the circuit modules 51 and 52
Since the number of input/output terminals is different between the circuit modules 53 and 54, the output terminals of the circuit modules 51 and 52 are connected to a plurality of input/output terminals 37 that serve as output terminals via high-enable buffers 33 and 34, , a plurality of input/output terminals 37 serving as input terminals are connected to input terminals of circuit modules 53 and 54 via high-enable buffers 35 and 36. In addition, the buffer 3 mentioned above
3 to 36 form an input/output selector 63.

A selection signal input terminal 60 to which a selection signal for selecting one of the circuit modules 51 to 54 is supplied is connected to the AN
It is connected to one input terminal of D gates 29 and 30, and also connected to one input terminal of AND gates 27 and 28 via an inverter 31.

Similarly, a selection signal input terminal 61 is supplied with a selection signal for selecting one of the circuit modules 51 to 54.
is connected to one input terminal of AND gates 28 and 30, and also connected to one input terminal of AND gates 27 and 29 via an inverter 32.

The output side of such an AND gate 27 is the AND gate 2
1 and the enable terminal of the buffer 33, the output side of the AND gate 28 is connected to one input terminal of the AND gate 22 and the enable terminal of the buffer 34, and the output side of the AND gate 29 is connected to the enable terminal of the AND gate 23. connected to one input terminal and the enable terminal of the buffer 35;
An output side of ND gate 30 is connected to one input terminal of AND gate 24 and an enable terminal of buffer 36 .

Note that an output selector 62 is formed by the AND gates 21 to 24 and the OR gate 25 described above.

Although only one set of output selectors 62 is shown in FIG. 2, since each circuit module 51 to 54 has a plurality of output terminals, a plurality of output selectors 62 are provided. Similarly, a plurality of sets of input/output selectors 63 are provided.

A signal of 1 is sent from one of the AND gates 27 to 30 in response to the 1 and 0 select signals supplied to the select signal input terminals 60 and 61.

That is, when O signals are supplied to both select signal input terminals 60 and 61, a signal of 1 is sent from the AND gate 27, a signal of I is supplied to the select signal input terminal 60, and the select signal input terminal When a 0 signal is supplied to 61, a 1 signal is sent from the AND gate 28, a 0 signal is supplied to the select signal input terminal 60, and a l signal is supplied to the select signal input terminal 61. If the select signal input terminals 60 and 61 are both supplied with a signal of 1, the AND gate 30 outputs a signal of 1. Therefore, when a signal of 1 is sent out from the AND gate 27, a signal of 1 is sent out from the AND gate 21, which means that the output signal of the circuit module 51 is selected, and a signal of 1 is sent out from the AND gate 28. is sent out, a signal of 1 is sent out from the AND gate 22, which means that the output signal of the circuit module 52 is selected, and when a signal of 1 is sent out from the AND gate 29, the AND gate Since a signal of 1 is sent out from 23, it means that the output signal of the circuit module 53 is selected, and when a signal of 1 is sent out from the AND gate 30, a signal of 1 is sent out from the AND gate 24. This means that the output signal of the circuit module 54 has been selected.

Regarding the buffers 33 to 36 of the input/output selector 63, when a signal of 1 is sent from the AND gate 27, that is, when the circuit module 51 is selected, the output signal of the circuit module 51 is sent from the buffer 33 to the input/output terminal 3.
7, and when a signal of 1 is sent from the AND gate 28, that is, when the circuit module 52 is selected, the output signal of the circuit module 52 is sent from the buffer 34 to the input/output terminal 37, and the signal of 1 is sent from the AND gate 29. When a signal of 1 is sent out, that is, when the circuit module 53 is selected, an input signal is sent from the input/output terminal 37 to the circuit module 53 via the buffer 35, and a signal of 1 is sent out from the AND gate 30, that is. When the circuit module 54 is selected, an input signal is sent to the circuit module 54 from the input/output terminal 37 via the buffer 36.

Incidentally, as in the case described with reference to FIG. is not limited to what is shown in FIG. 2, but is determined by the difference in the number of input/output terminals in each circuit module provided within the IC chip.

Further, the number of select signal input terminals is determined by the number of circuit modules provided in the IC chip, and is expressed as an index of 2 relative to the number of circuit modules.

[Effect of the invention] For example, in a gate array with 100 input/output pads, there is a circuit module A with 50 input terminals and 50 output terminals, and a circuit module A with 70 input terminals and 30 output terminals. In the case of forming a circuit module B, conventionally, a gate array having the above specifications would be used for each of the circuit modules A and B, and two gate arrays would be required. However, each input terminal includes a selection signal input terminal.

However, according to the present invention, since the output signal of either circuit module can be selected by the selection means that operates according to the selection signal supplied from the outside, it is possible to provide the circuit modules A and B in the same gate array. can. or,
For circuit module A, 50 input terminals are connected to 50 input pads of the gate array and 30 output terminals are connected to 50 input pads of the gate array.
are connected to the output batts of the gate array, and the remaining 20
The individual terminals are connected to input/output terminals provided in the gate array. Further, regarding circuit module B, 20 input terminals exceeding the number of input pads of the gate array are connected to the above-mentioned input/output terminals, and 30 output terminals are connected to 30 output pads of the gate array. The input/output terminals provided in the gate array can be selected as either input terminals or output terminals by a selection means according to a selection signal supplied from the outside.

As described above, according to the present invention, circuit modules A and B can be provided in the same gate array, whereas conventionally two gate arrays are required, and furthermore, selection of input or output at the input/output terminal can be performed as a selection means. This can improve the utilization rate of the gate array.

Furthermore, if the number of gates in the gate array is sufficient, it is also possible to increase the number of circuit modules.

Therefore, development costs can be reduced by accommodating multiple circuit modules in the same gate array, and since one gate array can be used as multiple circuit modules, the unit price of IC chips can be reduced due to mass production advantages. I can do it.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of one embodiment of the gate array circuit device of the present invention, and FIG. 2 is a logic circuit diagram showing another embodiment of the output selector and input/output selector shown in FIG. 1. and 2... circuit module, -ru, 0... output selector, 13... input/output selector, O
l...Input terminal, 02...Select signal input terminal, 03...Output terminal, 104...Input/output terminal. Patent applicant Rico Co., Ltd. −

Claims (1)

[Claims] (1) Select multiple circuit modules that are included in the same gate array and whose total number of input/output terminals exceeds the number of input/output pads of the gate array, and a circuit module that supplies input signals, and select one of the circuit modules listed above. A gate array circuit device comprising: selection means for selecting a signal transmitted by the gate array circuit device.