JPH04321347A - Unit mount detection circuit - Google Patents

Abstract

PURPOSE:To quicken the speed of mount detection by devision the circuit such that the required number of signal lines is not increased even when the number of mount units is increased and no reply procedure is included. CONSTITUTION:The frame is provided with plural units 11, 21, 31 and a detection section 41 to detect the mount state of them to the frame. The detection section 41 is provided with an address generating circuit 43 generating a multiplexed address signal A corresponding to a unit number by using a clock signal 42 and a demultiplexer circuit 46 demultiplexing a mount signal B for each unit. The unit 11, 21, 31 is provided with an address comparator circuit 13, 23, 33 outputting a coincidence signal when a specific address and the address signal A are coincident and an output circuit 15, 25, 35 outputting the mount signal B through the reception of the coincidence signal. Each of the units 11, 21, 31 and the detection section 41 are interconnected by an address bus 44 and a mount signal bus 45.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a unit mounting detection circuit for detecting the mounting state of a unit mounted on a device such as a communication device.

0002

2. Description of the Related Art A conventional unit mounting detection circuit of this type will be explained with reference to the drawings.

FIG. 2 is a block diagram of a first conventional example. The device installed on the rack 200 is provided with a detection section 101, which is connected to a plurality of units that play various roles in the device, in this example, units 104, 105, 1.
This unit detects whether or not 06 is mounted on the rack 1. When each unit 104 , 105 , 106 is mounted on the rack 200 using a connector, it sends a ground air status signal 103 indicating that it has been mounted to a detection circuit 102 provided in the detection section 101 . The detection circuit 102 individually takes in the ground air status signal 103 from each unit 104 , 105 , 106 and detects the mounting status of the unit on the rack 200 .

FIG. 3 is a block diagram of a second conventional example. A detection unit 111 is installed on the rack 300, and the unit 11
4,115,116 are to be implemented. When each unit 114, 115, 116 is mounted on the rack 300, the communication circuit 112 of the detection unit 111 and the communication circuit 117 of each of the units 114, 115, 116,
118 and 119 are connected to each other by a serial bus 113. And each unit 114, 115, 116
The confirmation of the mounting on the rack 300 is carried out from the communication circuit 112 to each unit 114, 115, 1 via the serial bus 113.
The communication circuit 112 detects whether or not there is a response using serial data to the alarm sent to the 16 communication circuits 117, 118, and 119.

[0005]

[Problem to be Solved by the Invention] In the first conventional example of these conventional unit mounting detection circuits, the number of signal lines taken into the detection section increases in proportion to the increase in the number of units that perform mounting detection. However, there was a drawback that it was easy to become depressed due to lack of terminals in the connector of the unit including the detection section.

In addition, in the second conventional example, the number of signal lines does not increase even if the number of units detected to be mounted increases, but since the non-response of alarms is used to detect unit mounting, the number of target units increases. If there are too many, it takes time to perform the next check after one check, and there is a drawback that the unit mounting state cannot be detected quickly.

[0007]

[Means for Solving the Problems] A unit mounting detection circuit of the present invention includes a plurality of units mounted on a device and a detection section for detecting the mounting state of the plurality of units. The unit includes an address generation circuit and a separation circuit, each of the plurality of units includes an address comparison circuit and an output circuit, and when the plurality of units are mounted, the plurality of units and the detection unit are connected to the address comparison circuit. each of the output circuits and the address generation circuit are connected to each other by an address bus, each of the output circuits and the separation circuit are connected to each other by a signal bus,
The address generation circuit generates multiplexed address signals corresponding to the plurality of units in response to input of a clock signal, and outputs the generated address signals to the address bus and the separation circuit, and each of the address comparison circuits generates multiplexed address signals corresponding to the plurality of units. The address being inputted is compared with the address signal input from the address bus, and when the address and the address signal match, a match signal is output, and each of the output circuits outputs a match signal when the match signal is input. The separating circuit outputs a mounting signal indicating that the included unit is mounted to the signal bus, and the separation circuit inputs the mounting signal multiplexed from the signal bus, and outputs the mounting signal from the address generation circuit to the signal bus. The mounting signal is separated for each unit by the address signal.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. A detection section 41 included in a monitoring control unit (not shown) is always installed on the rack 100, and a plurality of units, in this example, units 11, 21,
31 is mounted so that it can be inserted and removed. Unit 11, 21, 3
1 is a unit whose mounting on the rack 100 is to be detected. An address bus 45 is installed at the mounting position of the address generation circuit 42 of the detection unit 41 and each unit 11, 21, 31.
is already wired. Therefore, units 11, 21,
31 is mounted on the rack 100, each unit is connected to the address generation circuit 42 and other mounted units by an address bus 44.

The address comparison circuits 13, 23, 33 include
Unique addresses are set by address setting signals 12, 22, and 32, respectively. The address generation circuit 42 is configured to control the units 11, 21, 31 by inputting the clock signal 42.
It generates a multiplexed address signal A corresponding to
Output to 3 and 33. Address comparison circuit 13, 23, 3
3 takes in the address signal A, respectively. When the address comparison circuits 13, 23, and 33 match each unique address with the address signal A, the address comparison circuits 13, 23, and 33 output matching signals 14, 24, and 33, respectively.
Output. Each address comparison circuit 13, 23, 33 is connected to an output circuit 15, 25, 35, respectively. The output circuits 15, 25, and 35 each output a coincidence signal 14.
, 24, and 34, and outputs a mounting signal B of low level "L" to the signal bus 45. That is, each output circuit 1
5, 25, and 35 are the unit 1 that each contains
Only when 1, 21, and 31 are mounted on rack 100,
Activated by address signal A, each unit 11, 2
A mounting signal B, which is a signal indicating that 1 and 31 are mounted, is output. The mounting signal B is multiplexed according to the number of units to be mounted (here 3).

The signal bus 45 connects the units 11, 21, 3
1 are connected to each other, and when any of these units is mounted on the rack 100, the detection unit 4
It is connected to the separation circuit 46 of No. 1. The separation circuit 46 uses the same signal as the address signal A output from the address generation circuit 43 to separate the mounting signal B input from the signal bus 45 and multiplexed by the address signal A into each unit 11, 21, and 31. Then, it is output as a status signal 47 indicating the mounting status of each unit.

0012

As explained above, the present invention multiplexes and outputs the mounting signal indicating the mounting state of the unit onto the signal bus, so that if an appropriate number of address buses are prepared, Even if the number of mounted units increases, the number of required signal lines does not increase. Additionally, since it does not include a response procedure, it has the advantage of fast implementation detection.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a block diagram of a first conventional example.

FIG. 3 is a block diagram of a second conventional example.

[Explanation of symbols]

11, 21, 31 Unit 12, 22, 32 Address setting signal 13, 23
, 33 Address comparison circuit 14, 24, 34
Coincidence signals 15, 25, 35 Output circuit 41 Detection section 42 Clock signal 43 Address generation circuit 44 Address bus 45 Signal bus 46 Separation circuit A Address signal B Mounting signal C Status signal 100, 200, 300 Frame 101, 111 Detection section 102 Detection Circuit 103 Status signals 104, 105, 106, 114, 115, 116
Units 112, 117, 118, 119 Communication circuit 11
3 Serial bus

Claims (1)

[Claims] [Claim 1] A plurality of units mounted on a device;
In the unit mounting detection circuit, the detection section includes an address generation circuit and a separation circuit, and each of the plurality of units includes an address comparison circuit and an output circuit. When the plurality of units are mounted, the plurality of units and the detection section are such that each of the address comparison circuits and the address generation circuit are connected to each other by an address bus, and each of the output circuits and the separation circuit are connected to each other by a signal bus. The address generation circuit generates multiplexed address signals corresponding to the plurality of units in response to input of a clock signal, and outputs the multiplexed address signals to the address bus and the separation circuit. Each of the output circuits compares a preset address with the address signal input from the address bus, and outputs a match signal when the address and the address signal match, and each of the output circuits outputs a match signal. When a matching signal is input, a mounting signal indicating that the included unit is mounted is outputted to the signal bus, and the separation circuit inputs the mounting signal multiplexed from the signal bus, A unit mounting detection circuit characterized in that the mounting signal is separated for each unit based on the address signal from the address generation circuit.