JPH04318998A - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JPH04318998A
JPH04318998A JP3085631A JP8563191A JPH04318998A JP H04318998 A JPH04318998 A JP H04318998A JP 3085631 A JP3085631 A JP 3085631A JP 8563191 A JP8563191 A JP 8563191A JP H04318998 A JPH04318998 A JP H04318998A
Authority
JP
Japan
Prior art keywords
circuit board
electrode
wiring
mounting
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3085631A
Other languages
Japanese (ja)
Other versions
JP2697345B2 (en
Inventor
Masaki Nishimura
西村　雅貴
Makoto Murase
真 村瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3085631A priority Critical patent/JP2697345B2/en
Publication of JPH04318998A publication Critical patent/JPH04318998A/en
Application granted granted Critical
Publication of JP2697345B2 publication Critical patent/JP2697345B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/281—Applying non-metallic protective coatings by means of a preformed insulating foil
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4635—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating flexible circuit boards using additional insulating adhesive materials between the boards

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To increase the degree of integration by increasing the number of wiring on a circuit board even though the size of the circuit board is restricted by placing a mounting supplemental film between a semiconductor equipment and the circuit board. CONSTITUTION:A flat package type semiconductor equipment 4 is connected to electrodes 10 and 11 placed on the top face and is mounted, and an electrode 12 for connecting to circuit board is placed on the bottom face. A mounting auxiliary film 5 connecting electrodes 10 and 11 to electrode 12 is placed on a circuit board 7, and a land 6 and an electrode 12 located and connected to wiring 9 placed on the circuit board 7 are connected together and mounted. Also, the auxiliary mounting film 5 is laminated between two insulation films 2 where the electrodes 10 to 12 connected by wiring 1 is sandwiched. By doing this, the circuit board 7 can be made as a multi-layer, and the size of the circuit board 7 can be increased.

Description

【発明の詳細な説明】[Detailed description of the invention]

【０００１】0001

【産業上の利用分野】本発明は、混成集積回路に関する
。FIELD OF THE INVENTION This invention relates to hybrid integrated circuits.

【０００２】0002

【従来の技術】従来の混成集積回路は、回路を形成した
回路基板上に、半田ペーストを、実装する半導体装置の
電極に合せて形成された半田ランド上に塗布し、半導体
装置の電極を半田ランドに合せて半田を溶かし回路基板
と半導体装置を接続していた。[Prior Art] In conventional hybrid integrated circuits, solder paste is applied onto solder lands formed to match the electrodes of a semiconductor device to be mounted on a circuit board on which a circuit is formed, and the electrodes of the semiconductor device are soldered. The circuit board and semiconductor device were connected by melting solder to match the lands.

【０００３】0003

【発明が解決しようとする課題】従来の混成集積回路は
、搭載する半導体装置の電極及びピッチに合せて半導体
装置を実装する回路基板上に接続用のランドを形成する
必要があり、回路基板のサイズに制約がある場合、回路
基板上の配線は、形成されたランドの間に配線する為、
回路基板上に配線を収容しきれなくなるという問題点が
あった。配線密度を上げる対策として回路基板の多層化
があるが、各層の接続電極の面積が必要になり、高密度
実装が進む中では、限界がある。[Problems to be Solved by the Invention] Conventional hybrid integrated circuits require connection lands to be formed on the circuit board on which the semiconductor device is mounted, in accordance with the electrodes and pitch of the semiconductor device to be mounted. If there is a size restriction, the wiring on the circuit board is routed between the formed lands, so
There was a problem that the wiring could not be accommodated on the circuit board. Multi-layering of circuit boards is a measure to increase wiring density, but this requires a larger area for connection electrodes in each layer, which has its limits as high-density packaging progresses.

【０００４】又、半導体ベアチップと表面実装用半導体
装置を同一回路基板上に実装する場合、半導体ベアチッ
プの電極が多いと、回路基板に設ける電極及び電極から
の配線導体も多くなり、半田ランドを形成するのに必要
なスペースを確保するには、回路基板を多層にするか、
回路基板のサイズを大きくしなければならないという問
題点があった。Furthermore, when mounting a semiconductor bare chip and a surface-mounted semiconductor device on the same circuit board, if the semiconductor bare chip has many electrodes, the number of electrodes provided on the circuit board and wiring conductors from the electrodes also increases, leading to the formation of solder lands. To obtain the space needed to
There was a problem in that the size of the circuit board had to be increased.

【０００５】[0005]

【課題を解決するための手段】本発明の混成集積回路は
、複数の絶縁フイルムの層間に配線を設けて積層し前記
配線に接続して上面に素子搭載用の電極及び下面に回路
基板接続用の電極を設けた実装用補助フイルムと、前記
回路基板接続用の電極と接続するランドを設けて前記実
装用補助フイルムを搭載する回路基板とを有する。[Means for Solving the Problems] The hybrid integrated circuit of the present invention includes a plurality of insulating films that are laminated with wiring provided between the layers, connected to the wiring, and electrodes for mounting an element on the upper surface and electrodes for connecting a circuit board on the lower surface. The circuit board has a mounting auxiliary film provided with an electrode, and a circuit board provided with a land connected to the circuit board connection electrode and on which the mounting auxiliary film is mounted.

【０００６】[0006]

【実施例】次に、本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

【０００７】図１（ａ）は本発明の一実施例を示す分解
斜視図、図１（ｂ）は図１（ａ）の実装用補助フイルム
の分解斜視図である。FIG. 1(a) is an exploded perspective view showing one embodiment of the present invention, and FIG. 1(b) is an exploded perspective view of the mounting auxiliary film of FIG. 1(a).

【０００８】図１（ａ）に示すように、上面に設けた電
極１０，１１に接続してフラットパッケージ型半導体装
置４を搭載し、下面に回路基板接続用の電極１２を設け
、電極１０，１１と電極１２間を接続した実装用補助フ
イルム５を回路基板５の上に載せ、回路基板５の上に設
けた配線９に接続して設けたランド６と電極１２とを接
続して実装する。As shown in FIG. 1A, a flat package type semiconductor device 4 is mounted by connecting to electrodes 10 and 11 provided on the upper surface, and an electrode 12 for connecting to a circuit board is provided on the lower surface. The mounting auxiliary film 5 with the connection between the electrode 11 and the electrode 12 is placed on the circuit board 5, and the electrode 12 is connected to the land 6, which is connected to the wiring 9 provided on the circuit board 5, for mounting. .

【０００９】図１（ｂ）に示すように、実装用補助フイ
ルム５は２枚の絶縁フイルム２の間に電極１０，１１，
１２及びこれらを接続する配線１を挟んで積層し、半導
体装置４を接続する電極１０の上面と、半導体装置４を
接続し且つランド６に接続する上面の夫々の絶縁フイル
ム２に開孔部を設けると共に電極１２の下面及び直接回
路基板７上に素子を搭載するための開孔部１３を設けて
いる。なお、位置合わせマーク３は実装用補助フイルム
５と回路基板７との位置合わせを行なうためのものであ
る。なお、実装用補助フイルム５は配線１を絶縁フイル
ム２を介して多層に形成しても良い。As shown in FIG. 1(b), the mounting auxiliary film 5 has electrodes 10, 11,
12 and the wiring 1 connecting these, and an opening is formed in each of the insulating films 2 on the upper surface of the electrode 10 that connects the semiconductor device 4 and the upper surface that connects the semiconductor device 4 and the land 6. In addition, an opening 13 is provided on the lower surface of the electrode 12 and directly on the circuit board 7 for mounting an element thereon. The alignment mark 3 is used to align the mounting auxiliary film 5 and the circuit board 7. Note that the mounting auxiliary film 5 may be formed by forming the wiring 1 in multiple layers with the insulating film 2 interposed therebetween.

【００１０】0010

【発明の効果】以上説明したように本発明は、実装用補
助フイルムを半導体装置と回路基板の間に介在させるこ
とにより回路基板のサイズに制約が有る場合でも回路基
板の配線数を増やす事が出来、集積度が高くなるという
効果を有する。[Effects of the Invention] As explained above, the present invention makes it possible to increase the number of wires on a circuit board even when the size of the circuit board is limited by interposing an auxiliary film for mounting between the semiconductor device and the circuit board. This has the effect of increasing the degree of integration.

【００１１】又、半導体ベアチップとフラットパッケー
ジ型半導体装置を同一基板上に実装する場合等の半導体
を同一基板上に実装する場合等の半導体装置の電極から
の引き出し本数が多い場合でも、回路配線上の制約が多
い回路基板上の配線の一部を実装用補助フイルム上に設
けることにより、配線の密集度を緩和できる。[0011] Furthermore, even when there are many leads from the electrodes of the semiconductor device, such as when mounting semiconductors on the same substrate, such as when mounting a semiconductor bare chip and a flat package type semiconductor device on the same substrate, the circuit wiring By providing part of the wiring on the circuit board, which has many restrictions, on the mounting auxiliary film, the density of the wiring can be alleviated.

【図面の簡単な説明】[Brief explanation of drawings]

【図１】本発明の一実施例を示す分解斜視図及び一実施
例に使用する実装用補助フイルムの分解斜視図である。FIG. 1 is an exploded perspective view showing an embodiment of the present invention and an exploded perspective view of a mounting auxiliary film used in the embodiment.

【符号の説明】[Explanation of symbols]

１，９　　　　配線 ２　　　　絶縁フイルム ３　　　　位置合わせマーク ４　　　　半導体装置 ５　　　　実装用補助フイルム ６　　　　ランド ７　　　　回路基板 １０，１１，１２　　　　電極 １３　　　　開孔部 1,9 Wiring 2 Insulating film 3 Alignment mark 4 Semiconductor device 5 Auxiliary film for mounting 6 Land 7 Circuit board 10, 11, 12 Electrode 13 Opening part

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】　　複数の絶縁フイルムの層間に配線を設
けて積層し前記配線に接続して上面に素子搭載用の電極
及び下面に回路基板接続用の電極を設けた実装用補助フ
イルムと、前記回路基板接続用の電極と接続するランド
を設けて前記実装用補助フイルムを搭載する回路基板と
を有することを特徴とする混成集積回路。1. A mounting auxiliary film comprising a plurality of insulating films laminated with wires provided between the layers, connected to the wires, and provided with an electrode for mounting an element on the upper surface and an electrode for connecting a circuit board on the lower surface; 1. A hybrid integrated circuit comprising: a circuit board on which the mounting auxiliary film is mounted, the circuit board having a land for connection with an electrode for connecting the circuit board.
JP3085631A 1991-04-18 1991-04-18 Hybrid integrated circuit Expired - Lifetime JP2697345B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3085631A JP2697345B2 (en) 1991-04-18 1991-04-18 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3085631A JP2697345B2 (en) 1991-04-18 1991-04-18 Hybrid integrated circuit

Publications (2)

Publication Number Publication Date
JPH04318998A true JPH04318998A (en) 1992-11-10
JP2697345B2 JP2697345B2 (en) 1998-01-14

Family

ID=13864186

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3085631A Expired - Lifetime JP2697345B2 (en) 1991-04-18 1991-04-18 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JP2697345B2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6371579U (en) * 1986-10-30 1988-05-13

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6371579U (en) * 1986-10-30 1988-05-13

Also Published As

Publication number Publication date
JP2697345B2 (en) 1998-01-14

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A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 19970819