JPH04317339A - Ldd type mos field effect transistor having inverted t-shaped gate and manufacture thereof - Google Patents

Abstract

PURPOSE: To provide an LDD-type MOS field transistor of inverted T-shape gate electrode of sub-micron size of less, by eliminating an unnecessary layer in a polycrystalline silicon gate, for stable adjustment in thickness of each layer. CONSTITUTION: On a semiconductor substrate 21, a first gate oxide layer 22, an n<+> -polycrystalline silicon layer 23, and a fire-proof metal layer 24 are formed. The n<+> -polycrystalline silicon layer 23 and the fire-proof metal layer 24 are etched to form a polycrystalline silicon gate. Here, etching is made so that the first gate oxide layer 22 is exposed, and n<-> -impurity ions are implanted to form an n<-> -LDD25. The second n<+> -polycrystalline a silicon layer 26 and a second oxide layer 27 are, vapor-deposited over the entire surface for patterning. A formed oxide layer 27 is left out as a spacer, so that the polycrystalline silicon gate is in an inverted T-shape. The n<+> -polycrystalline silicon layer 26 on the upper part of the polycrystalline silicon gate is removed by etching, and n<+> -ion is implanted for formation of a desired field effect transistor.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention has a gate electrode formed in an inverted T-shape, and a drain formed in an LDD (Lightly Do
The present invention relates to an LDD type MOS field effect transistor having an inverted T-shaped gate electrode formed in a ped drain) and a method for manufacturing the same.

0002

[Prior art] Sub-micron
A recent technological trend for MOS field effect transistors with class-sized devices, ie with dimensions below, for example, 0.5 to 1 μm, is the development of LDD type MOS field effect transistors with so-called LDDs. LDD type M
OS field effect transistors have shown very good characteristics in terms of performance and reliability. In particular, the LDD structure is
Commonly employed in narrow channel NMOS field effect transistors because they mitigate thermionic effects, LDD structures employ oxidized sidewall spacers to reduce the maximum lateral electric field within the channel.

However, while the adoption of the LDD structure reduces the maximum lateral electric field and the current flowing through the semiconductor substrate and improves the drain holding voltage, the MOS field effect transistor having the LDD structure has a reduced current driving ability. , there is a problem of decreased reliability.

[0004] Various papers have been published in order to improve these problems. One example is IDEM Tech.
nical Digest 1986, IEEE, p.
The paper “A NOVEL S” published in 742-745
UBMICRON LDD TRANSISTOR W
ITH INVERSE-T GATE STRUCT
URE". In this paper, as shown in FIG. 1(a), a gate oxide layer 2, a polycrystalline silicon layer 3, and an oxide layer 4 are sequentially stacked on a semiconductor substrate 1, and a polycrystalline silicon layer is formed by a photolithography process. A silicon gate 5 is formed.At this time,
When forming the polycrystalline silicon gate 5, all of the polycrystalline silicon layer 3 other than the polycrystalline silicon gate 5 is not etched;
A thin layer 3A remains on the gate oxide layer 2. This is for forming a polycrystalline silicon gate 5 having an inverted T shape. Element P, which is an n- impurity, is then implanted to form an n-LDD region 6.

As shown in FIG. 1(b), CVD (Ch
chemical vapor deposition)
After the oxide layer 7 is deposited and the oxide sidewall spacers 7A are formed by anisotropic etching, the remaining thin layer 3A of the polycrystalline silicon layer 3 except under the patterned oxide sidewall spacers 7A is exposed to plasma. Removed by polycrystalline silicon etching. Next, source-drain regions 8 are formed by implanting arsenic ions, which are n+ impurities.

As shown in FIG. 1C, both oxide layers 4 and 7 are removed, leaving only oxide sidewall spacers 7A on the sidewalls of polycrystalline silicon layer 3, resulting in an inverted T-shaped polycrystalline silicon gate. 5 is produced.

[0007] At this time, the important thing is that n+ source -
When forming the drain region 8, the n+ impurity is implanted while the polycrystalline silicon gate 5 is self-aligned, so that optimum Ln can be obtained.

However, in the above process, the inverted T
When manufacturing a polycrystalline silicon gate in the shape of a polycrystalline silicon gate, after stacking the polycrystalline silicon layer 3, in the process of etching the region of the polycrystalline silicon gate 5 using a mask, the etching time is adjusted to obtain a predetermined thickness. A thin layer 3A of the polycrystalline silicon layer 3 having a certain thickness is formed. Therefore, with this method, not only is it not possible to accurately form the thickness of the thin layer 3A formed in the area of the polycrystalline silicon gate 5, but it is also not easy. In addition, since the n- impurity is implanted through the thin layer 3A of the polycrystalline silicon gate 5, the film quality and reliability of the polycrystalline silicon gate 5 are affected, and the characteristics of a microscopic MOS field effect transistor are affected. This became one of the factors that reduced the reliability of the system.

[0009] Still another technique, which is slightly improved over such conventional techniques, is the IEDM Technical D
igest 1989, IEEE, p. 765-768
A paper published in “A Self-Aligned I
nverse-T Gate Fully Overl
applied LDD Device for Sub-
Half Micron CMOS”. This paper describes the use of oxidized or T
An iN buffer layer is interposed therebetween. The oxidized and TiN buffer layers used here exhibit good etch selectivity to the polycrystalline silicon layer.

Therefore, the thickness of the polycrystalline silicon layer can be adjusted and uniformly formed.

[0011]

[Problems to be Solved by the Invention] That is, as shown in FIG. 2, there is an oxidation or TiN buffer between the first polycrystalline silicon layer 11 and the second polycrystalline silicon layer 12 constituting the polycrystalline silicon gate. The above-mentioned problems are solved by using the buffer layer 13 as an etch stop when etching the first polycrystalline silicon layer 11. Since the buffer layer 13, which is not necessary in terms of structure and operating characteristics, remains between the polycrystalline silicon layers 11 and 12, the operating characteristics of the submicron-level MOS field effect transistor are adversely affected.

Therefore, the present invention has been made in consideration of the above-mentioned problems, and an object of the present invention is to eliminate unnecessary layers within a polycrystalline silicon gate and to stabilize the thickness of each layer. By making it possible to adjust the desired M
An object of the present invention is to provide an LDD type MOS field effect transistor having an inverted T-shaped gate electrode with a submicron size or less, and a method for manufacturing the same, for manufacturing an OS device.

Another object of the present invention is to provide an LDD type inverted T-shaped gate electrode to increase current drive capability and improve reliability due to oxidation trapping effect in the manufacturing process of CMOS devices of submicron size or smaller. An object of the present invention is to provide a MOS field effect transistor and a method for manufacturing the same.

[0014] Still another object of the present invention is to provide a refractory metal;
In forming n- and n+ LDDs in an inverted T-shaped polycrystalline silicon gate structure, selective etching is used to self-align them, thereby facilitating device manufacturing control. An object of the present invention is to provide an LDD type MOS field effect transistor with an inverted T-shaped gate electrode, which can improve the reliability and production yield in manufacturing the device, and a method for manufacturing the same.

[0015]

[Means for Solving the Problems] A method for manufacturing a MOS field effect transistor of the present invention for achieving the above object includes:
A process of sequentially forming a first gate oxide layer, a polycrystalline silicon layer, and a metal layer on a semiconductor substrate, and after patterning to form a polycrystalline silicon gate, ionization is performed to form lightly doped drain and source regions. a step of depositing and patterning a second polycrystalline silicon layer and a low-temperature oxide layer to form spacers on the sidewalls of the polycrystalline silicon gate; and a step of removing the remaining second polycrystalline silicon layer. It is characterized by a step of implanting ions at a high concentration.

Further, the L of the inverted T-shaped gate electrode of the present invention
A DD type MOS field effect transistor is formed on a semiconductor substrate, and includes an inverted T-shaped polycrystalline silicon gate with a spacer on the sidewall, and a drain and a low concentration ion drain formed inside the lower part of the polycrystalline silicon gate, respectively. The method is characterized by comprising a source region and a refractory metal layer silicidated on the surface of the polycrystalline silicon gate.

[0017]

[Example] Hereinafter, an example of the present invention will be described as shown in FIG. 3(a) attached.
This will be described in detail with reference to (d) to (d) and FIG.

First, as shown in FIG. 3A, a first gate oxide layer 22, an n+ polycrystalline silicon layer 23, and a refractory metal layer 24 are sequentially deposited on a semiconductor substrate 21. At this time, the first gate oxide layer 22 is made of, for example, SiO
2 to a thickness of about 200 angstroms, and Ti or W was used as the refractory metal.

Then, as shown in FIG. 3B, the n+ polycrystalline silicon layer 23 and the refractory metal layer 24 are etched by photolithography, leaving a width corresponding to the polycrystalline silicon gate. At this time, photolithography is performed so that the first gate oxide layer 22 is exposed, and n- impurity ions are implanted to form an n
- Form LDD25.

Here, in order to form a polycrystalline silicon gate, the above-mentioned series of steps of depositing and etching a refractory metal such as Ti or W at the initial stage of the process creates a self-containing layer on both sides of the polycrystalline silicon gate. This is for forming n- and n+ source-drain regions in an aligned manner, and allows the dose and length of the n- LDD 25 to be adjusted according to the device design. be. Furthermore, by positioning the n-LDD 25 under the polycrystalline silicon gate,
The current driving ability is not reduced by the specific resistance of the drain, and the n-dose can be reduced, so that the hot carrier effect is improved.

In particular, by forming the n-LDD 25 under the polycrystalline silicon gate, it is possible to reduce device degradation caused by oxidation trapping, thereby extending the average life time.

FIG. 3(b) shows that the gate, source, and drain, which are the basic components of a MOS field effect transistor, have been formed, and then FIG. 3(c)
), a second n+ polycrystalline silicon layer 26 and a second oxide layer 27 are deposited over the entire surface and patterned. At this time, the formed oxide layer 27 is LTO (
Low Temperature
n), and patterning is performed so that the polycrystalline silicon gate has an inverted T-shape as shown in FIG. 3(d), so that the oxide layer 27 remains as a spacer. Here, the material used for the spacer 27 is as follows:
Ta2 to increase the fringing field effect
It is preferable to use a substance with a high dielectric constant, such as O5.

According to the present invention, the width of the spacer is determined by RIE (Reactive Ion E) rather than being determined according to the thickness of the LTO described above due to the selective etching property of the refractory metal.
tching).

Next, as shown in FIG. 3(d), the second oxide layer 27 remaining in the area other than the area where the spacer is formed is removed.
Then, the n+ polycrystalline silicon layer 26 on the top of the polycrystalline silicon gate is etched and removed, and n+ ions are implanted to form an LDD type MO with a predetermined inverted T-shaped gate electrode.
An S field effect transistor is formed.

In FIG. 3D, the upper portion of the metal layer 24 exposed through the etching process is subsequently subjected to silicidation during fabrication of applied devices.

LD with inverted T-shaped gate electrode according to the present invention
D-type MOS field effect transistors can be used to fabricate NMOS field effect transistors in a CMOS process, as shown in FIG. That is, the LDD type MOS electric field of the inverted T-shaped gate electrode of the present invention as described above is generated in the region of the P-well 29, which is an active region formed between the field oxide films 28 for element isolation on the semiconductor substrate. An effect transistor is formed. This element can be connected with a PMOS field effect transistor formed adjacently to form a CMOS, and furthermore, depending on the application, a ROM (Read Only M
memory), RAM (Random Access
The present invention is applicable to applications such as memory devices (Memory) or semiconductor memory devices using MOS field effect transistors.

[0027]

As described above in detail, the present invention can form n- and n+ LDs by using a mask for patterning polycrystalline silicon gates only once in the initial process.
Since D is formed, process work is easy and it is suitable for process monitoring. Furthermore, compared to the conventional method in which the thickness of the spacer must be adjusted according to the thickness of the LTO,
Improved inverted T that is easier to tune the thickness using RIE, eliminates unwanted layers within the structure of the polysilicon gate, and minimizes the effects of maximum lateral electric field on the drain side. Thus, an LDD type MOS field effect transistor having a gate electrode shaped like a letter can be obtained.

[Brief explanation of drawings]

[Figure 1] Conventional LDD type MOS with inverted T-shaped gate electrode
FIG. 1 is a diagram sequentially showing an example of a manufacturing process of a field effect transistor.

[Figure 2] Conventional LDD type MOS with inverted T-shaped gate electrode
FIG. 3 is a cross-sectional view showing another example of a field effect transistor.

FIG. 3 is a cross-sectional view sequentially showing the manufacturing process of an LDD type MOS field effect transistor with an inverted T-shaped gate electrode according to the present invention.

FIG. 4 is a sectional view showing an application example of the present invention.

[Explanation of symbols]

21 Semiconductor substrate 22 First gate oxide layer 23 Polycrystalline silicon layer 24 Metal layer 26 Second polycrystalline silicon layer 27 Low temperature oxidation layer

Claims (8)

[Claims] 1. A first gate oxide layer on a semiconductor substrate;
sequentially forming a polycrystalline silicon layer and a metal layer, patterning to form a polycrystalline silicon gate, and then implanting ions to form lightly doped drain and source regions; a step of stacking and patterning a silicon layer and a low-temperature oxide layer to form spacers on the sidewalls of the polycrystalline silicon gate;
1. A method for manufacturing an LDD type MOS field effect transistor with an inverted T-shaped gate electrode, comprising the steps of removing a polycrystalline silicon layer and implanting high concentration ions. 2. The method of manufacturing an LDD type MOS field effect transistor with an inverted T-shaped gate according to claim 1, wherein the metal layer is formed of a refractory metal such as Ti or W. 3. The LDD type MOS field effect with an inverted T-shaped gate according to claim 1, wherein the drain and source regions are formed by implanting low concentration ions to the inside of the polycrystalline silicon gate. Method of manufacturing transistors. 4. The inverted T patterning according to claim 1, characterized in that the patterning operation for forming the polycrystalline silicon gate is performed until the first gate oxide layer is exposed.
A method for manufacturing an LDD type MOS field effect transistor with a shape gate. 5. The spacer is made of a high dielectric constant insulator or T
The method for manufacturing an LDD type MOS field effect transistor with an inverted T-shaped gate according to claim 1, wherein the inverted T-shaped gate is a2O5. 6. L of the inverted T-shaped gate according to claim 1, characterized in that each step is included in a step of an NMOS field effect transistor in a CMOS process.
A method for manufacturing a DD type MOS field effect transistor. 7. An inverted T-shaped polycrystalline silicon gate formed on a semiconductor substrate and having spacers on sidewalls, and a drain and source region for low concentration ions formed respectively inside the lower part of the polycrystalline silicon gate. , silicidation (silicidation) is applied to the surface of the polycrystalline silicon gate.
1. An LDD type MOS field effect transistor with an inverted T-shaped gate, characterized in that it is provided with a refractory metal layer subjected to oxidation. 8. The inverted T-shaped gate LDD type MOS according to claim 7, wherein the manufactured device is an NMOS field effect transistor constituting a CMOS.
Field effect transistor.