JPH11284152A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To show the desired characteristics of the two types of MIS transistor circuits which have a different gate insulating film thickness and a nonvolatile memory cell array, by integrating them through a simple process. SOLUTION: Wells 3 and 4 of a high breakdown voltage circuit section are formed and channel ions are implanted. A tunnel oxide film 6 of a stacked gate nonvolatile memory cell, a polysilicon film 7 and an ONO film 8, both of which are to serve as a floating gate, are formed. Then, while the tunnel oxide film 6, the polysilicon film 7, and the ONO film 8 are selectively made to remain in a memory cell array region, the surface of a silicon substrate 1 is exposed in a high breakdown voltage circuit section and a low breakdown voltage circuit section, and a first gate oxide film 9 is formed for the low breakdown voltage circuit section, formation of wells 10, 11 and channel control are conducted simultaneously by accelerated ion implantation using the first gate oxide film as a sacrificed oxide film. Subsequently, the first gate oxide film is removed from the low breakdown voltage circuit section and the second gate oxide film is formed in the low breakdown voltage circuit section.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device including two types of MIS transistor circuits having different gate insulating film thicknesses, and more particularly, to a nonvolatile semiconductor memory having a floating gate and a control gate laminated thereon. The present invention relates to a manufacturing method useful for a semiconductor device in which two types of MIS transistor circuits having different gate insulating film thicknesses are integrally formed together with a cell array.

[0002]

2. Description of the Related Art Conventionally, a semiconductor device in which a logic circuit is mounted together with a nonvolatile semiconductor memory cell array is known. In this type of semiconductor device, a MIS transistor circuit (hereinafter, referred to as a high withstand voltage circuit) which constitutes a driving circuit or the like that handles a high voltage required for driving a memory cell is operated as a peripheral circuit of a memory cell array at a low voltage. MIS transistor circuit (hereinafter, referred to as a logic circuit)
Two types of MIS transistor circuits are used. Since these two types of MIS transistor circuits have different gate insulating film thicknesses and also have different gate structures of the nonvolatile memory cells, the manufacturing process of the semiconductor device becomes complicated.

A brief description will be given of a conventional manufacturing process of this type of semiconductor device as follows. First, well formation and channel control ion implantation are performed on the high breakdown voltage circuit portion and the low breakdown voltage circuit portion of the semiconductor substrate, respectively. Next, a tunnel oxide film for a non-volatile memory cell is formed, a floating gate electrode material film is deposited thereon, and a slit process for separating in a row direction in the memory cell array is performed. An insulating film is deposited on the electrode. After removing these laminated films by etching while leaving them in the memory cell array region, a first gate oxide film for a high breakdown voltage circuit is formed. At this time, the first gate oxide film is formed slightly thinner than the film thickness required for the high breakdown voltage circuit. Then, the first gate oxide film of the low breakdown voltage circuit portion is removed by etching.
A thin second gate oxide film for a low breakdown voltage circuit is formed again. In the thermal oxidation step of the second gate oxide film, the accumulation of the first gate oxide film occurs, and the first gate oxide film has a required thickness.

Thereafter, a gate electrode material film is deposited, and a control gate in the nonvolatile memory cell array region, and a gate electrode in the high breakdown voltage circuit portion and the low breakdown voltage circuit portion are respectively patterned, and then the source and drain diffusion layers are formed. Form.

[0005]

However, such a conventional manufacturing process has the following problems. In other words, focusing on the low breakdown voltage circuit section, after performing well formation and channel ion implantation, two thermal oxidation steps of forming a gate oxide film in the high breakdown voltage circuit section and forming a gate oxide film in the low breakdown voltage circuit section, and Through a film removal process. These steps change the impurity profile of the bulk region of the MOS transistor. The effect is particularly large in a low withstand voltage circuit section that operates at a low voltage and requires high-speed performance. Therefore, precise impurity profile control of a channel region cannot be performed, and desired element characteristics cannot be obtained. Etc. occur.

In consideration of the memory cell array region, a high-temperature thermal oxidation process for forming a tunnel oxide film or an inter-insulation film between the floating gate and the control gate is performed in the memory cell array region. The influence of the high-temperature heat process on the high-withstand-voltage circuit portion and the low-withstand-voltage circuit portion in which well formation and channel ion implantation have been performed before is further increased.

Further, when a conductive layer serving as a floating gate and an insulating film serving as an inter-insulating film thereon are first formed in a memory cell array region, and then channel ions are implanted in a high breakdown voltage circuit and a low breakdown voltage circuit. The number of lithography steps on the inter-insulating film of the memory cell increases, which lowers the reliability and yield of the memory cell.

The present invention has been made in view of the above circumstances, and has made it possible to exhibit desired characteristics in two types of MIS transistor circuits having different gate insulating film thicknesses while reducing the number of steps. It is an object of the present invention to provide a method for manufacturing a semiconductor device.

The present invention also reduces the number of steps,
It is an object of the present invention to provide a method of manufacturing a semiconductor device in which desired characteristics can be exhibited by two types of MIS transistor circuits having different gate insulating film thicknesses together with a nonvolatile semiconductor memory cell array.

[0010]

According to the present invention, first, a first MIS transistor circuit and a second MIS transistor circuit having a thinner gate insulating film than the first MIS transistor circuit are integrally formed. In a method of manufacturing a semiconductor device, a sacrificial insulating film is formed on a semiconductor substrate, and a first M
A first ion implantation step of selectively implanting impurity ions into a formation region of an IS transistor circuit; a step of forming a first gate insulating film on the semiconductor substrate after removing the sacrificial insulating film; A second ion implantation step of selectively implanting impurity ions into the formation region of the second MIS transistor circuit of the semiconductor substrate through one gate insulation film, and a second MIS transistor of the first gate insulation film Forming a second gate insulating film thinner than the first gate insulating film in the second MIS transistor circuit forming region of the semiconductor substrate after selectively removing a portion in the circuit forming region; Forming a gate electrode in each of the formation regions of the first and second MIS transistor circuits, and forming source and drain diffusion layers.

The present invention secondly provides a memory cell array in which nonvolatile semiconductor memory cells having a floating gate are arranged, a first MIS transistor circuit, and a first M transistor circuit.
In a method of manufacturing a semiconductor device in which a second MIS transistor circuit having a smaller gate insulating film thickness than an IS transistor circuit is integratedly formed, impurity ions are selectively implanted into a formation region of a first MIS transistor circuit of a semiconductor substrate. 1) an ion implantation step, and after the first ion implantation step, a gate section forming step of laminating a conductive layer and an insulating film to be a floating gate in a memory cell array region of the semiconductor substrate; and After that, a second ion implantation step of selectively implanting impurity ions into a formation region of a second MIS transistor circuit of the semiconductor substrate, and the memory cell array, the first MIS transistor circuit, and the second MIS transistor circuit Forming a gate electrode, a source, and a drain diffusion layer in each of the formation regions. To.

More specifically, the first and second ion implantation steps are for ion implantation of impurities for forming wells and controlling channels of the first and second MIS transistor circuits, respectively.

[0013] Third, the present invention provides a memory cell array in which a nonvolatile semiconductor memory cell having a floating gate and a control gate laminated with an insulating film interposed therebetween is provided, a first MIS transistor circuit, and In a method of manufacturing a semiconductor device in which a second MIS transistor circuit having a smaller gate insulating film thickness than one MIS transistor circuit is formed, a sacrificial oxide film is formed on a semiconductor substrate,
A first ion implantation step for selectively forming an impurity ion for well formation and channel control in a formation region of an S transistor circuit, and removing the sacrificial oxide film in at least a formation region of a memory cell array; Forming a tunnel oxide film on the tunnel oxide film and stacking a floating gate electrode material film and an insulating film on the gate electrode on the tunnel oxide film; and storing the insulating film on the gate electrode, the floating gate electrode material film and the tunnel oxide film in a memory. After exposing the surface of the semiconductor substrate in the formation regions of the first and second MIS transistor circuits while selectively leaving them in the formation region of the cell array,
Forming a first gate oxide film on the semiconductor substrate; and selectively forming an impurity for well formation and channel control in a formation region of a second MIS transistor circuit of the semiconductor substrate through the first gate oxide film. A second ion implantation step of performing ion implantation, and a step of selectively removing a portion of the first gate oxide film in a formation region of a second MIS transistor circuit, and then removing a second MI of the semiconductor substrate.
Forming a second gate oxide film thinner than the first gate oxide film in the formation region of the S transistor circuit, depositing and patterning a gate electrode material film, and forming the memory cell array formation region and the first and second memory cells; The nonvolatile semiconductor memory cell and the MIS
Forming a transistor.

In the present invention, preferably, in the second ion implantation step, the well formation and the channel control ion implantation are performed without thermal diffusion by sequentially changing the accelerating voltage using a high acceleration ion implanter. It is assumed to be performed as a step.

Preferably, in the present invention, in the second ion implantation step, a resist pattern is sequentially formed on the NMOS transistor region and the PMOS transistor region in the formation region of the second MIS transistor circuit to form a well. And a step of ion-implanting impurities for channel control.

Further, in the present invention, preferably, after the second ion implantation step, at a temperature of 900 to 1050 ° C., a temperature of 1 to 1050 ° C. is used to suppress abnormal diffusion of the implanted impurities due to crystal defects.
Either perform lamp annealing for 0 to 30 seconds or improve the quality of the gate oxide film formed thereafter.
A furnace annealing process is performed at a temperature of 0 to 800 ° C. for 30 to 60 minutes.

According to the first aspect, after performing ion implantation and forming a gate insulating film on the side of the first MIS transistor circuit (high breakdown voltage circuit) handling relatively high voltage, the second MIS handling low voltage. Ion implantation and formation of a gate insulating film on the transistor circuit (low breakdown voltage circuit) side are performed. Therefore, compared with the conventional method, the number of oxidation and oxide film removal steps after ion implantation is reduced on the low breakdown voltage circuit side, and the characteristic deterioration due to the impurity profile fluctuation is prevented.

According to the second and third aspects of the present invention, when a high breakdown voltage circuit and a low breakdown voltage circuit are formed together with a nonvolatile semiconductor memory cell array, the ion implantation step of the low breakdown voltage circuit is performed by using a floating gate on the memory cell array side. This is performed after forming the conductive layer. Therefore, the impurity profile on the low withstand voltage circuit side is not affected by the high-temperature heating step in the step of forming the nonvolatile memory cell. As a result, compared to the conventional method in which the high voltage circuit and the low voltage circuit are ion-implanted before the formation of the floating gate structure on the memory cell array side, the impurity profile fluctuation on the low voltage circuit side is small, and a high-performance logic circuit or the like is used. A low withstand voltage circuit can be made.

In many cases, a driving circuit for a nonvolatile semiconductor memory requires a high voltage and a voltage of both positive and negative polarities. Therefore, it is often necessary to form a CMOS circuit in a deep double well. On the other hand, it is desired that a logic circuit operating at a low voltage mixed with a memory cell array be integrated and formed in a small area on a large scale. For this reason, a circuit is formed in a well as shallow as possible, the diffusion layer capacitance is controlled as small as possible by controlling the profile of the well, the junction breakdown voltage is increased as much as possible, and the channel impurity profile of the MIS transistor is precisely controlled. , So that the short channel effect and the like do not occur. The second invention can meet such a demand with a relatively simple process.

In the first to third aspects of the present invention, in the ion implantation step of the low breakdown voltage circuit, ion implantation for channel control and well formation is simultaneously performed in one resist pattern formation using a high-acceleration ion implantation apparatus. Thereby, while reducing the number of lithography steps, it is possible to further eliminate the conventional heat diffusion step for forming a well.
It is possible to prevent impurity re-diffusion and characteristic deterioration of an already formed element. In particular, in the second and third inventions, the deterioration of the characteristics of the already formed nonvolatile memory cell array portion, in particular, the decrease in the reliability of the insulating film can be suppressed.
It is possible to obtain a high performance logic embedded nonvolatile memory.

Further, in the first and third inventions, the ion implantation on the high breakdown voltage circuit side is performed through a sacrificial insulating film (oxide film). After removing the sacrificial insulating film, the first gate insulating film (oxide film) is formed. ) Is formed. The first gate insulating film is increased in thickness in a later step of forming a gate insulating film on the low withstand voltage circuit side to have a desired thickness, but is maintained without defects.
Also, the ion implantation on the low withstand voltage circuit side is the first for the high withstand voltage circuit.
An insulating film formed at the same time as the gate insulating film is used as a sacrificial insulating film. The sacrificial insulating film (first gate insulating film) is removed, and then a second gate insulating film (oxide film) is formed. ing. Therefore, while reducing the number of processes, the final gate insulating film on both the high-voltage circuit and the low-voltage circuit side is not exposed to ions, becomes a gate insulating film without damage, and has excellent element reliability. It can be.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 11 show a manufacturing process of an embodiment in which the present invention is applied to a logic-embedded nonvolatile semiconductor memory. (A), (b), and (c) of each drawing show a memory cell array section and a high-withstand-voltage circuit section (that is, a memory cell drive circuit including a MOS transistor using a thick gate oxide film) in the same step. M of 1
IS transistor circuit section) and low withstand voltage circuit section (ie,
FIG. 9 is a cross-sectional view of a second MIS transistor circuit portion as a logic circuit including a MOS transistor using a thin gate oxide film). In the case of this embodiment, both the high breakdown voltage circuit and the low breakdown voltage circuit are CMOS circuits.

As shown in FIG. 1, in a state in which a buffer sacrificial oxide film 2a of about 100 nm is formed on a p-type silicon substrate 1, n-type sacrificial oxide films 2a and n-type transistors are respectively formed in a PMOS transistor forming region and an NMOS transistor forming region of a high breakdown voltage circuit portion. Well 3 and p-type well 4 are sequentially formed. Specifically, for example, first, a resist pattern having an opening in an n-type well formation region is formed, and phosphorus is applied at an acceleration voltage of about 150 keV to 1.
After ion implantation in the order of E13 / cm ² , 120
Thermal diffusion is performed at a temperature of about 0 ° C. for about 6 hours to form the n-type well 3. Next, a resist pattern having an opening in a p-type well formation region is formed, and boron is accelerated to an acceleration voltage of 100.
After ion implantation at about keV in the order of 1E13 / cm ² , thermal diffusion is performed at about 1200 ° C. for about 3 hours to form a p-type well 4. As a result, the n-type well 3 has a depth of about 5 μm, and the p-type well 4 has a depth of 2.5 μm.
The depth is about μm.

Note that the p-type well 4 is not always arranged in the n-type well 2 as shown in the figure depending on the operation of the memory cell and the circuit design. For example, the p-type well 4 may be formed outside the n-type well 2 or the NMOS transistor may be formed on the p-type substrate 1 without forming the p-type well 4.

Thereafter, as shown in FIG. 2, an element isolation insulating film 5 for partitioning each element region is formed. In the figure, LOC
Although the element isolation insulating film 5 is shown by the OS process,
A buried insulating film such as I (Shallow Trench Isolation) may be used. Usually, a sacrificial oxide film 2
Although a is removed, a relatively thick oxide film (not shown) is formed on the substrate surface in the element isolation insulating film forming step. Therefore, after removing this oxide film by wet etching,
A sacrifice oxide film 2b is formed about 20 nm again.

Next, as shown in FIG. 3, channel-controlled ion implantation is performed in the high breakdown voltage circuit section. More specifically, the ion implantation step is described below. First, a resist pattern having an opening in an NMOS transistor formation region of the high breakdown voltage circuit portion is formed, and an appropriate amount of boron is implanted at an acceleration voltage of about 60 keV. Next, a resist pattern having an opening in the PMOS transistor formation region is formed, phosphorus ion implantation for suppressing a short channel effect is performed at an acceleration voltage of about 300 keV, and boron ion implantation for threshold value control is accelerated at about 20 keV. Perform with voltage.

Next, a resist pattern having an opening in the memory cell array region is formed, and the sacrificial oxide film 2b in the memory cell array region is removed by wet etching. Then, as shown in FIG.
A tunnel oxide film 6 is formed by thermal oxidation at about ° C. Further, a polysilicon film 7 serving as a floating gate electrode material film is formed on the entire surface.
Is deposited thereon, and a stacked structure film (ONO film) 8 of a silicon oxide film / silicon nitride film / silicon oxide film is formed thereon as an insulating film on the floating gate (inter-insulating film). In order to improve the characteristics of the tunnel oxide film 6, a nitriding treatment at a high temperature of about 1100 ° C. may be performed. When such a nitriding process is not performed on the tunnel oxide film 6, the sacrificial oxide film 2b is removed from the entire surface of the substrate without forming the above-described resist pattern having an opening in the memory cell array region. The oxide film 6, the polysilicon film 7, and the ONO film 8 may be sequentially formed. On the other hand, the polysilicon film 7 is usually doped with a heavy n-type impurity. Before the ONO film 8 is actually formed, the polysilicon film 7 is subjected to a separation step of separating each memory cell in the row direction of the memory cell array orthogonal to the plane of the drawing. The ONO film 8 is, for example, 1000
A silicon oxide film (6 nm) is formed by dilution oxidation at a temperature of about 10.degree.
By converting to a silicon oxide film of about nm, a laminated structure of silicon oxide film 6 nm / silicon nitride film 6 nm / silicon oxide film 6 nm is obtained.

Thereafter, a resist pattern covering the memory cell array region is formed, and as shown in FIG. 5, the ONO film 8 and the polysilicon film 7 of the high voltage circuit portion and the low voltage circuit portion are sequentially etched and removed, and further sacrificed. The oxide film 2b is also removed by wet etching to expose the substrate surfaces of the high breakdown voltage circuit portion and the low breakdown voltage circuit portion.

Next, as shown in FIG. 6, a first gate oxide film 9 of about 13 nm, which is a part of a gate oxide film for a high breakdown voltage circuit, is simultaneously formed on the high breakdown voltage circuit section and the low breakdown voltage circuit section. It is formed by oxidation. This oxidation step is applied to the ONO film 8 in the memory cell array region. However, since the oxidation rate of the nitride film is low, the change in the thickness of the ONO film can be suppressed to a negligible level. At this stage, the first gate oxide film 9 is slightly less than the specified thickness, and is added in a gate oxidation step on the low breakdown voltage circuit side described later.

Next, as shown in FIG. 7, the well formation and the channel control ion implantation are simultaneously performed selectively on the low breakdown voltage circuit portion by using a high-acceleration ion implantation apparatus.
A mold well 10 and an n-type well 11 are formed. This ion implantation step will be specifically described as follows. First, a resist pattern having an opening in an NMOS transistor formation region of a low withstand voltage circuit is formed.
eV, 150 keV, 80 keV, 20 keV, etc. are sequentially switched to change the boron from 1E12 to 1E13 / c.
Ion implantation is performed at a dose of m ² , and the threshold value is controlled simultaneously with the formation of the p-type well 10. Then, P of the low voltage circuit
A resist pattern having an opening in a MOS transistor formation region is formed, and the accelerating voltage is set to 800 keV and 500 keV.
V, 300k0eV, sequentially switches and so 150 keV, phosphorus ions are implanted at a dose of 1E12~1E13 / cm ^2, further boron ion implantation to at a low acceleration voltage of 20keV at 1E12 / cm ² order continuous Thereby, the formation of the n-type well 11 and the threshold value control are performed.

As described above, in this embodiment, the impurity is doped from the channel region to the depth required for the well by high-acceleration ion implantation in which the acceleration energy is switched stepwise. No long-term heat diffusion step is performed. The implanted impurities are activated in a short thermal process such as gate oxidation.

As shown in FIG. 7, the p-type well 10 and the n-type well 11 are formed as shown in FIG.
Is also formed shallowly below the element isolation insulating film 5 to have an impurity profile having a step. These impurity profiles are based on the junction breakdown voltage, junction capacitance,
Optimal control may be performed in consideration of several viewpoints such as suppression of the short channel effect. In the case of such ion implantation, the controllability is excellent because the heat process after ion implantation is short.

When the above-described high-acceleration ion implantation is performed, damage (crystal defects) of the substrate may occur. In order to prevent abnormal diffusion (increased diffusion) of the implanted impurity due to this damage, 900-105 after ion implantation.
It is preferable to perform a lamp annealing process at a temperature of 0 ° C. for 10 to 30 seconds, that is, an RTA (Rapid Thermal Annealing) process. Further, in order to improve the quality of the gate oxide film formed later, it is preferable to set the temperature at 700 to 800 ° C.
It is also preferable to perform furnace annealing for 60 minutes.

It is desirable that the resist pattern covering the other circuit region in the high-acceleration ion implantation step is not subjected to a heat treatment after development. Usually, a resist pattern is subjected to a baking process at about 125 ° C. called post-baking after exposure and development. When this post-baking step is performed, the edge of the resist pattern is deformed and thinned.
This is shown in FIG. FIG. 12A shows the resist 20 immediately after development, and FIG. 12B shows a state in which the shape of the opening end of the resist 20 has changed by post-baking. This deformation of the resist pattern does not cause much problem in the usual ion implantation or etching process at a low acceleration voltage. However, in the high acceleration ion implantation, there is a possibility that the ions may penetrate through the deformed and thinned portion. For this reason, it is preferable that the post-baking be omitted and the highly accelerated ion implantation be performed with the resist ends kept in a vertical shape as shown in FIG.

Thereafter, a resist pattern having an opening in the low breakdown voltage circuit portion is formed, and the first gate oxide film 9 in the low breakdown voltage circuit portion is removed by wet etching as shown in FIG. Then, high-temperature thermal oxidation is performed again to form an 8 nm-thick second gate oxide film 1 on the low breakdown voltage circuit portion as shown in FIG.
Form 2 In this high-temperature thermal oxidation step, the thickness of the first gate oxide film 9 already formed on the high breakdown voltage circuit side is increased, for example, to about 17 nm. This is a gate oxide film thickness necessary to secure a withstand voltage of about 10 V required for the memory cell drive circuit.

Thereafter, as shown in FIG. 10, a polysilicon film 13 as a gate electrode material film is deposited. Note that the gate electrode material film may have a laminated structure of polysilicon and a high melting point metal or a high melting point metal silicide. Hereinafter, as shown in FIG. 11, according to a normal process, in the memory cell array region, a control gate 13a in which a polysilicon film 13 is patterned, and a floating gate 7a in which a polysilicon film 7 is patterned in a self-aligned manner with the control gate 13a. The polysilicon film 13 is patterned in the high breakdown voltage circuit portion and the low breakdown voltage circuit portion to form gate electrodes 13b and 13c having desired gate lengths, respectively, and further, the n + type diffusion layer 14 serving as a source and a drain, and p + The mold diffusion layers 15 are sequentially formed. Hereinafter, although not shown in the figure, an interlayer insulating film is deposited, and metal wirings are provided in multiple layers if necessary, thereby completing a logic embedded nonvolatile memory.

According to this embodiment, after the floating gate of the memory cell array and the ONO film on the floating gate are formed through the high-temperature process, the well formation and the channel control ion of the low breakdown voltage circuit portion requiring a precise impurity profile are required. Since the implantation is performed, the impurity profile of the low breakdown voltage circuit is precisely controlled, and a high performance low breakdown voltage circuit can be obtained. In addition, in both the high-voltage circuit and the low-voltage circuit, the gate oxide film is formed as a defect-free oxide film that is not exposed to ion implantation, and a gate oxide film with good insulation can be obtained. Is obtained.

Further, after forming up to the ONO film in the memory cell array region and performing many lithography steps thereon, O
Although the insulation property of the NO film may be deteriorated, in this embodiment, the lithography process on the ONO film is a process of patterning the ONO film 8 and the polysilicon film 7 (FIG. 5), and a high-acceleration ion implantation apparatus. Of the low withstand voltage circuit section using
The process is only four times, including the step of implanting ions into the MOS transistor side and the PMOS transistor side (FIG. 7) and the step of etching the oxide film on the low breakdown voltage circuit side (FIG. 8). Therefore, it is possible to minimize the deterioration of the reliability of the memory cell array.

Further, by utilizing the highly accelerated ion implantation, a heat diffusion step for forming a well of a low breakdown voltage circuit section can be omitted. Thus, a high-temperature and long-time heat process after the formation of the memory cell can be avoided, and the characteristics of the already formed memory cell do not deteriorate. The total number of lithography steps can be reduced.

Another embodiment of the present invention will be described with reference to FIGS. FIG. 13 corresponds to the step of FIG. 6 of the previous embodiment. That is, in this embodiment, the same steps as those in the previous embodiment are performed in FIGS. In the previous embodiment, in the step of FIG. 6, a first gate oxide film 9 on the high withstand voltage circuit side, which is added later, is formed, and the first gate oxide film 9 is used as it is on the low withstand voltage circuit side. Used as a sacrificial oxide film for implantation.

On the other hand, in this embodiment, as shown in FIG. 13, first, an 8 nm sacrificial oxide film 21 is formed, and this is removed by wet etching on the high withstand voltage circuit side. Next, as shown in FIG. 14, a first gate oxide film 9 having a thickness of 10 nm is formed in the high breakdown voltage circuit portion. At this time, the sacrificial oxide film 21 of the low breakdown voltage circuit portion is accumulated,
It is about 17 nm. After that, similarly to the step of FIG. 7 in the previous embodiment, as shown in FIG. 15, well formation into the low breakdown voltage circuit portion and high-acceleration ion implantation for channel control are performed. Subsequent steps are the same as in the previous embodiment.

In this embodiment, although the number of steps is increased as compared with the previous embodiment, the thickness of the sacrificial oxide film 21 for performing high-acceleration ion implantation into the low breakdown voltage circuit section is large. Metal contamination at the time can be suppressed more effectively.

The present invention is not limited to the above embodiment. For example, in the embodiment, the well formation and the channel control are simultaneously performed by the high-acceleration ion implantation only in the low-withstand-voltage circuit portion, but the well formation and channel control using the high-acceleration ion implantation are similarly performed in the high-withstand-voltage circuit portion. You may.

Further, in the embodiments, the logic embedded nonvolatile memory has been described. However, in a nonvolatile semiconductor memory not embedded with logic, a low breakdown voltage MOS transistor and a high breakdown voltage MOS transistor having different gate oxide film thicknesses are provided in a memory cell drive circuit. The present invention can be similarly applied to the case of using.

[0045]

As described above, according to the present invention, after the ion implantation and the gate insulating film formation on the high breakdown voltage circuit side are performed, the ion implantation and the gate insulation film formation on the low breakdown voltage circuit side are performed. On the low breakdown voltage circuit side, the number of steps of oxidation and oxide film removal after ion implantation is reduced, and characteristic deterioration due to variation in impurity profile is prevented.

According to the present invention, when a high breakdown voltage circuit and a low breakdown voltage circuit are integrally formed together with the nonvolatile semiconductor memory cell array, the ion implantation step of the low breakdown voltage circuit is performed after forming the main part of the memory cell on the memory cell array side. By doing so, the impurity profile of the channel or well on the low withstand voltage circuit side is not affected by the high-temperature heating step in the formation process of the nonvolatile memory cell, and the high withstand voltage circuit and the low withstand voltage circuit are formed before the main part of the memory cell is formed. Compared with the method of performing ion implantation, a variation in impurity profile on the low breakdown voltage circuit side is small, and a high-performance logic-embedded nonvolatile semiconductor memory can be obtained.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of each part showing a well forming step of a high breakdown voltage circuit part according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of each part showing a sacrificial oxide film forming step according to the embodiment.

FIG. 3 is a sectional view of each part showing a channel ion implantation step of the high breakdown voltage circuit section according to the embodiment.

FIG. 4 is a cross-sectional view of each section showing a step of forming a floating gate film of the memory cell array according to the same embodiment.

FIG. 5 is a cross-sectional view of each part showing a step of etching and removing an unnecessary portion of the floating gate film according to the embodiment.

FIG. 6 is a cross-sectional view of each portion showing a first gate oxide film forming step according to the example.

FIG. 7 is a sectional view of each part showing a channel ion implantation step of the low breakdown voltage circuit part according to the embodiment.

FIG. 8 is a sectional view of each part showing an oxide film etching step of the low breakdown voltage circuit part according to the same embodiment.

FIG. 9 is a cross-sectional view of each portion showing a step of forming a second gate oxide film according to the same embodiment.

FIG. 10 is a cross-sectional view of each portion showing a step of depositing a gate electrode material film according to the same embodiment.

FIG. 11 is a cross-sectional view of each part showing a gate electrode patterning and a diffusion layer forming step according to the example.

FIG. 12 is a view showing a resist pattern during high-acceleration ion implantation according to the same embodiment.

FIG. 13 is a sectional view showing a step corresponding to FIG. 6 according to another embodiment of the present invention;

FIG. 14 is a cross-sectional view showing a step corresponding to FIG. 6 of the embodiment.

FIG. 15 is a cross-sectional view showing a step corresponding to FIG. 7 in the embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2a, 2b, 21 ... Sacrificial oxide film, 3
... n-type well, 4 ... p-type well, 5 ... element isolation insulating film,
7 ... polysilicon film, 8 ... ONO film, 9 ... first gate oxide film, 10 ... p-type well, 11 ... n-type well, 12 ...
Second gate oxide film, 13 ... polysilicon film, 13a ...
Control gates, 13b, 13c ... gate electrodes, 14 ... n +
Type diffusion layer, 15... P + type diffusion layer.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Norihisa Arai 25-1, Ekimae Honcho, Kawasaki-ku, Kawasaki-shi, Kanagawa Prefecture Inside Toshiba Microelectronics Co., Ltd. Company Toshiba Yokohama Office

Claims (8)

[Claims] In a method of manufacturing a semiconductor device in which a first MIS transistor circuit and a second MIS transistor circuit having a smaller gate insulating film thickness than the first MIS transistor circuit are integrated, a sacrificial insulation is provided on the semiconductor substrate. A first ion implantation step of forming a film and selectively implanting impurity ions into a formation region of a first MIS transistor circuit; and removing a sacrificial insulating film and then forming a first gate insulating film on the semiconductor substrate. Forming a second layer of the semiconductor substrate through the first gate insulating film.
A second ion implantation step of selectively implanting impurity ions into a region where a MIS transistor circuit is formed, and selectively removing a portion of the first gate insulating film in a region where a second MIS transistor circuit is formed. Forming a second gate insulating film, which is thinner than the first gate insulating film, in a region where the second MIS transistor circuit is formed on the semiconductor substrate; and forming a second gate insulating film in the region where the first and second MIS transistor circuits are formed. Forming a gate electrode and forming a source and drain diffusion layer, respectively. 2. A memory cell array in which nonvolatile semiconductor memory cells having a floating gate are arranged, a first MIS transistor circuit, and a second MIS transistor circuit having a thinner gate insulating film than the first MIS transistor circuit. A first ion implantation step of selectively implanting impurity ions into a region of a semiconductor substrate where a first MIS transistor circuit is formed; and A gate portion forming step of laminating a conductive layer and an insulating film serving as a floating gate in a region of the memory cell array of the semiconductor substrate; and, after the gate portion forming step, a second M of the semiconductor substrate.
A second ion implantation step of selectively implanting impurity ions into a formation region of the IS transistor circuit; and a gate electrode, a source, and a gate electrode in the formation regions of the memory cell array, the first MIS transistor circuit, and the second MIS transistor circuit, respectively. Forming a drain diffusion layer. 3. The method according to claim 1, wherein the first and second ion implantation steps are for ion implantation of impurities for forming wells and controlling channels of the first and second MIS transistor circuits, respectively. Item 3. The method for manufacturing a semiconductor device according to item 1 or 2. 4. A memory cell array in which a nonvolatile semiconductor memory cell having a floating gate and a control gate laminated with an insulating film interposed therebetween is arranged, a first MIS transistor circuit, and a first MIS transistor circuit. In a method of manufacturing a semiconductor device in which a second MIS transistor circuit having a thin gate insulating film is integratedly formed, a sacrificial oxide film is formed on a semiconductor substrate, and a well is selectively formed in a formation region of the first MIS transistor circuit. A first ion implantation step of implanting impurity ions for channel control, and after removing the sacrificial oxide film at least in the formation region of the memory cell array, forming a tunnel oxide film on the semiconductor substrate. Laminating a floating gate electrode material film and an insulating film on the gate electrode, and After exposing the surface of the semiconductor substrate in the first and second MIS transistor circuit formation regions while selectively leaving the gate electrode material film and the tunnel oxide film in the memory cell array formation region, Forming a first gate oxide film; and forming a second gate oxide film on the semiconductor substrate through the first gate oxide film.
A second ion implantation step of selectively implanting impurity ions for forming a well and controlling a channel in a formation region of the MIS transistor circuit, and a formation region of a second MIS transistor circuit in the first gate oxide film Forming a second gate oxide film thinner than the first gate oxide film in the formation region of the second MIS transistor circuit of the semiconductor substrate after selectively removing the portion at Manufacturing a semiconductor device, comprising the steps of: depositing and patterning to form a nonvolatile semiconductor memory cell and a MIS transistor in a formation region of a memory cell array and a formation region of first and second MIS transistor circuits, respectively. Method. 5. The method according to claim 1, wherein the second ion implantation step includes a step of sequentially changing an acceleration voltage by using a high-acceleration ion implantation apparatus to perform well formation and impurity ion implantation for channel control without performing thermal diffusion. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the method is performed as a step. 6. The method according to claim 1, wherein the second ion implantation step is performed by using a second M
10. The method according to claim 9, further comprising the steps of sequentially forming a resist pattern on the NMOS transistor region and the PMOS transistor region in the formation region of the IS transistor circuit, and ion-implanting impurities for forming a well and controlling a channel. 5. The method for manufacturing a semiconductor device according to any one of 1 to 4. 7. After the second ion implantation step, a step 90 is performed to suppress abnormal diffusion of implanted impurities due to crystal defects.
The method according to claim 1, wherein the lamp annealing is performed at a temperature of 0 to 1050 ° C. for 10 to 30 seconds. 8. After the second ion implantation step, a step of improving the quality of a gate oxide film to be formed is performed.
The method for manufacturing a semiconductor device according to claim 1, wherein furnace annealing is performed at a temperature of about 800 ° C. for about 30 to 60 minutes.