FR2673326A1 - MOS LDD field-effect transistor with gate structure in the shape of an inverted T, and method of fabricating it - Google Patents
MOS LDD field-effect transistor with gate structure in the shape of an inverted T, and method of fabricating it Download PDFInfo
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- FR2673326A1 FR2673326A1 FR9116243A FR9116243A FR2673326A1 FR 2673326 A1 FR2673326 A1 FR 2673326A1 FR 9116243 A FR9116243 A FR 9116243A FR 9116243 A FR9116243 A FR 9116243A FR 2673326 A1 FR2673326 A1 FR 2673326A1
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- 230000005669 field effect Effects 0.000 title claims description 34
- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 70
- 229920005591 polysilicon Polymers 0.000 claims abstract description 70
- 238000000034 method Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 229910052751 metal Inorganic materials 0.000 claims abstract description 5
- 239000002184 metal Substances 0.000 claims abstract description 5
- 125000006850 spacer group Chemical group 0.000 claims description 17
- 239000003870 refractory metal Substances 0.000 claims description 12
- 229910021332 silicide Inorganic materials 0.000 claims description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 claims description 2
- 239000012212 insulator Substances 0.000 claims 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 238000002513 implantation Methods 0.000 abstract description 5
- 230000007797 corrosion Effects 0.000 description 11
- 238000005260 corrosion Methods 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000004075 alteration Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910021341 titanium silicide Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910008814 WSi2 Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000003750 conditioning effect Effects 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005685 electric field effect Effects 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7836—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a significant overlap between the lightly doped extension and the gate electrode
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
La présente invention concerne un transistor LDD
MOS à effet de champ à structure de grille en forme de T renversé et plus particulièrement un transistor LDD MOS à effet de champ en forme de T renversé comportant un transistor LDD (c'est-à-dire possédant un drain faiblement dopé), comportant une structure de grille en forme de T renversé.The present invention relates to an LDD transistor
Field effect MOS with an inverted T-shaped gate structure and more particularly an LDD transistor Reverse field T-shaped MOS comprising an LDD transistor (that is to say having a weakly doped drain), comprising an inverted T-shaped grid structure.
Ces derniers temps, on s'est intéressé à un transistor MOS à effet de champ d'une taille inférieure au micron, par exemple sous la forme d'un dispositif ayant une taille comprise entre 0,5 et 1 pin, pour réaliser un transistor LDD MOS à effet de champ possédant ce qu'on appelle la structure LDD. Le transistor LDD MOS à effet de champ présente d'excellentes performances et une excellente stabilité. En particulier, la structure LDD est largement utilisée dans un transistor à effet de champ NMOS à canal étroit afin de réduire l'effet des électrons chauds. Dans la structure LDD, on utilise une entretoise de paroi latérale constituée d'un oxyde pour réduire le champ électrique latéral maximum dans la région du canal. Recently, we have been interested in a field effect MOS transistor of a size less than one micron, for example in the form of a device having a size between 0.5 and 1 pin, for producing a transistor. LDD MOS field effect with what is called the LDD structure. The field effect LDD MOS transistor has excellent performance and stability. In particular, the LDD structure is widely used in a narrow channel NMOS field effect transistor to reduce the effect of hot electrons. In the LDD structure, a side wall spacer made of an oxide is used to reduce the maximum lateral electric field in the channel region.
Cependant, une entretoise de paroi latérale constituée d'un oxyde introduit un décalage entre la source- drain de type n et le bord de la grille en polysilicium, ce qui peut présenter plusieurs inconvénients. However, a side wall spacer made of an oxide introduces a shift between the n-type source-drain and the edge of the polysilicon grid, which can have several drawbacks.
Bien que l'on sache qu'une faible dose de dopage LDD ( < 10s3 cm ) est avantageuse pour réduire E max et le courant de substrat 1sub et améliorer la tension de maintien de drain, il a été indiqué que des transistors LDD, dont le drain est dopé avec une faible dose, ont une capacité très réduite de commande du courant et que de tels transistors peuvent présenter en réalité une vitesse plus élevée d'altération que les dispositifs pour lesquels on a un 1sub supérieur.Les vitesses accrues d'altération sont imputables aux charges négatives ou aux états d'interface piégés à la partie supérieure d'une région LDD faiblement dopé de type n-, qui n'est pas située directement au-dessous de la grille en polysilicium. Étant donné que cette région n'est pas soumise à une modulation directe par la grille, elle peut être aisément appauvrie par les charges piégées, ce qui entraîne un accroissement important de la résistance série source-drain, conduisant à une altération plus rapide de la commande du courant.Although it is known that a low dose of LDD doping (<10s3 cm) is advantageous for reducing E max and the current of substrate 1sub and improving the drain holding voltage, it has been indicated that LDD transistors, including the drain is doped with a low dose, has a very reduced capacity for controlling the current and that such transistors may in reality have a higher rate of alteration than the devices for which there is a higher 1sub. alteration are due to negative charges or interface states trapped at the top of a lightly doped n- type LDD region, which is not located directly below the polysilicon grid. Since this region is not subjected to direct modulation by the gate, it can be easily depleted by the trapped charges, which leads to a significant increase in the source-drain series resistance, leading to more rapid deterioration of the current control.
Un grand nombre de propositions ont été publiées pour résoudre ce problème. Une telle proposition est décrite dans l'article articulé "A NOVEL SUBMICRON LDD TRAN
SISTOR WITH INVERSE-T GATE STRUCTURE", pages 742-745, IEDM
Technical Digest 1986, IEEE. Les figures lA, 1B et 1C, annexées à la présente demande, sont des schémas illustrant une telle proposition. Comme représenté sur la figure 1A, une couche d'oxyde de grille 2, une couche de polysilicium 3 et une couche d'oxyde 4 sont formées successivement sur un substrat 1 et un traitement photolithographique est mis en oeuvre pour former une grille en polysilicium 5.Au lieu d'éliminer totalement par corrosion la couche de polysilicium 3 lors de la formation de la grille en polysilicium 5, on arrête délibérément la corrosion du polysilicium afin de laisser subsister une mince couche de polysilicium 3A, ce qui conduit à la formation d'une grille en polysilicium ayant une structure 5 de grille en forme de T renversé.On implante une dose de phosphore de type n avec une énergie appropriée pour former les régions LDD 6 de type n
Comme représenté sur la figure 1B, on dépose ensuite selon le procédé CVD (dépôt chimique en phase vapeur) une couche d'oxyde 7 et on lui applique une corrosion anisotrope pour former une entretoise de paroi latérale 7A constituée d'un oxyde, puis on met en oeuvre une corrosion plasmatique du polysilicium pour éliminer la mince couche restante de polysilicium 3A, hormis au niveau de la partie inférieure de l'entretoise de paroi latérale 7A, constituée d'un oxyde et devant être formée par structuration. On exé cute alors une implantation peu profonde d'arsenic de type n+ de manière à former une région de source-drain 8.A large number of proposals have been published to solve this problem. Such a proposal is described in the articulated article "A NOVEL SUBMICRON LDD TRAN
SISTOR WITH INVERSE-T GATE STRUCTURE ", pages 742-745, MEI
Technical Digest 1986, IEEE. FIGS. 1A, 1B and 1C, annexed to the present application, are diagrams illustrating such a proposal. As shown in FIG. 1A, a gate oxide layer 2, a polysilicon layer 3 and an oxide layer 4 are successively formed on a substrate 1 and a photolithographic treatment is implemented to form a polysilicon grid 5 Instead of completely eliminating the polysilicon layer 3 by corrosion during the formation of the polysilicon grid 5, the corrosion of the polysilicon is deliberately stopped in order to leave a thin layer of polysilicon 3A, which leads to the formation of '' a polysilicon grid having a grid structure 5 in the shape of an inverted T.We implant a dose of phosphorus of type n with an appropriate energy to form the regions LDD 6 of type n
As shown in FIG. 1B, an oxide layer 7 is then deposited according to the CVD (chemical vapor deposition) process and anisotropic corrosion is applied to it to form a side wall spacer 7A made of an oxide, then uses plasma corrosion of the polysilicon to remove the thin remaining layer of polysilicon 3A, except at the level of the lower part of the side wall spacer 7A, consisting of an oxide and having to be formed by structuring. A shallow implantation of n + type arsenic is then carried out so as to form a source-drain region 8.
Comme représenté sur la figure 1C, on élimine les couches d'oxyde 4, 7 hormis au niveau de l'entretoise de paroi latérale 7A, constituée d'un oxyde, en butée contre le rebord de la couche de polysilicium 3, qui permet d'achever la réalisation de la grille en polysilicium 5 avec la structure en forme de T renversé. As shown in FIG. 1C, the oxide layers 4, 7 are eliminated except at the level of the side wall spacer 7A, consisting of an oxide, in abutment against the edge of the polysilicon layer 3, which makes it possible to '' complete the realization of the polysilicon grid 5 with the inverted T-shaped structure.
Il est important que, lors de la formation de la région de source-drain 8 de type n+, l'implantation de la source-drain de type nf soit autoalignée avec la grille en polysilicium 5, ce qui permet d'obtenir une valeur Ln optimale. It is important that, during the formation of the source-drain region 8 of type n +, the implantation of the source-drain of type nf is self-aligned with the polysilicon grid 5, which makes it possible to obtain a value Ln optimal.
Cependant, on forme la grille en polysilicium 5 possédant une structure en forme de T renversé de manière que, lorsque la région de grille en polysilicium 5 est corrodée moyennant l'utilisation du masque après le dépôt de la couche de polysilicium 3, on puisse obtenir, au moyen d'une modulation de temps, une couche mince de polysilicium 3A possédant une certaine épaisseur. C'est pourquoi, ce procédé de fabrication permet difficilement de réaliser la pellicule mince 3A avec une épaisseur précise. De même, l'impureté de type n implantée dans la mince couche de polysilicium 3A influe sur la qualité des couches et sur la fiabilité de la grille en polysilicium 5, ce qui réduit grandement la fiabilité des caractéristiques du transistor
MOS à effet de champ.However, the polysilicon grid 5 is formed having an inverted T-shaped structure so that, when the polysilicon grid region 5 is corroded by means of the use of the mask after the deposition of the polysilicon layer 3, it is possible to obtain , by means of time modulation, a thin layer of polysilicon 3A having a certain thickness. This is why, this manufacturing process makes it difficult to produce the thin film 3A with a precise thickness. Likewise, the n-type impurity implanted in the thin layer of polysilicon 3A influences the quality of the layers and the reliability of the polysilicon grid 5, which greatly reduces the reliability of the characteristics of the transistor.
Field effect MOS.
Une autre technique est décrite dans l'article "A
SELF-ALIGNED INVERSE-T GATE FULLY OVERLAPPED LDD DEVICE FOR
SUB-HALF MICRON CMOS", pp. 765-768, IEDM TECHNICAL DIGEST 1989, IEE. Dans cette technique, on utilise une couche tampon d'oxyde ou de TiN insérée dans une grille en polysilicium possédant une structure en forme de T renversé. A la fois l'oxyde et le TiN présentent de bonnes sélectivités de cqrrosion vis-à-vis d'une couche de polysilicium et c'est pourquoi il est possible de moduler et de rendre uniforme l'épaisseur de la couche de polysilicium.Another technique is described in the article "A
SELF-ALIGNED INVERSE-T GATE FULLY OVERLAPPED LDD DEVICE FOR
SUB-HALF MICRON CMOS ", pp. 765-768, IEDM TECHNICAL DIGEST 1989, IEE. In this technique, an oxide or TiN buffer layer is used inserted in a polysilicon grid having an inverted T-shaped structure. Both the oxide and the TiN have good corrosion selectivities with respect to a layer of polysilicon and this is why it is possible to modulate and make uniform the thickness of the layer of polysilicon.
C'est-à-dire que, comme représenté sur la figure 2, entre une première couche de polysilicium 11 et une seconde couche de polysilicium 12, il est prévu une grille en polysilicium formée par une couche tampon 13 d'oxyde ou de
TiN. On arrête la corrosion de la couche épaisse de polysilicium au niveau de cette couche d'oxyde 13 de manière à supprimer les problèmes mentionnés précédemment. Cependant, cette couche tampon 13 est inutile pour la structure et les performances du transistor MOS à effet de champ et reste située entre les couches de polysilicium Il, 12, ce qui a un effet nuisible sur les performances du transistor
MOS à effet de champ d'une taille inférieure au micron.That is to say that, as shown in FIG. 2, between a first layer of polysilicon 11 and a second layer of polysilicon 12, there is provided a polysilicon grid formed by a buffer layer 13 of oxide or of
TiN. Corrosion of the thick layer of polysilicon is stopped at the level of this oxide layer 13 so as to eliminate the problems mentioned above. However, this buffer layer 13 is useless for the structure and the performances of the MOS field effect transistor and remains situated between the polysilicon layers II, 12, which has a detrimental effect on the performances of the transistor.
Field effect MOS smaller than one micron.
Un premier but de la présente invention est de fournir un transistor LDD MOS à effet de champ à structure de grille en forme de T renversé, qui possède de hautes performances et une grande fiabilité, et un procédé pour fabriquer un tel transistor. A first object of the present invention is to provide an LDD MOS field effect transistor with an inverted T-shaped gate structure, which has high performance and high reliability, and a method for manufacturing such a transistor.
Un second but de la présente invention est de fournir un procédé pour fabriquer un transistor LDD MOS à effet de champ à structure de grille en forme de T renversé, dont les étapes de mise en oeuvre soient simples et aisées à contrôler. A second object of the present invention is to provide a method for manufacturing an LDD MOS field effect transistor with an inverted T-shaped gate structure, the implementation steps of which are simple and easy to control.
Selon un aspect de la présente invention, il est prévu un procédé consistant à former séquentiellement une première couche d'oxyde de grille, une couche de polysilicium et une couche métallique sur un substrat; structurer et former une grille en polysilicium; exécuter une implantation ionique pour former des régions de drain et de source à faible concentration; déposer et structurer une seconde couche de polysilicium et une couche d'oxyde formée à basse température de manière à former une entretoise sur la paroi latérale de ladite grille en polysilicium; et supprimer ladite seconde couche de polysilicium restante pour exécuter une implantation ionique à haute concentration. According to one aspect of the present invention, there is provided a method comprising sequentially forming a first gate oxide layer, a polysilicon layer and a metal layer on a substrate; structure and form a polysilicon grid; perform ion implantation to form low concentration drain and source regions; depositing and structuring a second layer of polysilicon and an oxide layer formed at low temperature so as to form a spacer on the side wall of said polysilicon grid; and removing said second remaining polysilicon layer to perform high concentration ion implantation.
Selon un autre aspect de la présente invention, il est prévu un transistor LDD MOS à effet de champ à structure de grille en forme de T renversé, comportant une grille en polysilicium possédant une structure à structure de grille en forme de T renversé formée sur un substrat et équipée d'une entretoise sur sa paroi latérale; des régions de drain et de source à faible concentration formées dans la partie intérieure de ladite grille en polysilicium; et une couche de métal réfractaire formée à l'état de siliciure sur la surface de ladite grille en polysilicium. According to another aspect of the present invention, there is provided an LDD MOS field effect transistor with an inverted T-shaped gate structure, comprising a polysilicon gate having a structure with an inverted T-shaped gate structure formed on a substrate and fitted with a spacer on its side wall; low concentration drain and source regions formed in the interior of said polysilicon grid; and a layer of refractory metal formed in the silicide state on the surface of said polysilicon grid.
Entre-temps, on transforme une couche de métal réfractaire située sur la couche de polysilicium de type n+ en siliciure au moyen d'une opération ultérieure de recuit, c'est-à-dire qu'on forme un composé du métal réfractaire et du silicium, comme par exemple du siliciure de tungstène (WSi2) ou du siliciure de titane (TiSi2). Meanwhile, a layer of refractory metal located on the layer of n + type polysilicon is transformed into silicide by means of a subsequent annealing operation, that is to say a compound of the refractory metal and of the silicon, such as, for example, tungsten silicide (WSi2) or titanium silicide (TiSi2).
D'autres caractéristiques et avantages de la présente invention ressortiront de la description donnée ciaprès prise en référence aux dessins annexés, sur lesquels
- les figures 1A à 1C, dont il a déjà été fait mention, sont des schémas illustrant le procédé de fabrication d'une forme de réalisation du transistor LDD MOS à effet de champ de l'art antérieur possédant une structure de grille en forme de T renversé;
- la figure 2 représente une vue en coupe montrant une autre forme de réalisation d'un transistor LDD
MOS à effet de champ de l'art antérieur comportant une structure de grille en forme de T renversé;
- les figures 3A à 3D sont des schémas illustrant le procédé de fabrication d'un transistor LDD MOS à effet de champ à structure de grille en forme de T renversé conforme à la présente invention; et
- la figure 3E est une vue en coupe d'une forme de réalisation préférée conforme à la présente invention.Other characteristics and advantages of the present invention will emerge from the description given below taken with reference to the appended drawings, in which
- Figures 1A to 1C, which have already been mentioned, are diagrams illustrating the method of manufacturing an embodiment of the prior art field effect LDD MOS transistor having a gate-like structure T overturned;
- Figure 2 shows a sectional view showing another embodiment of an LDD transistor
Prior art field effect MOS comprising an inverted T-shaped grid structure;
FIGS. 3A to 3D are diagrams illustrating the method of manufacturing an LDD MOS transistor with field effect with an inverted T-shaped gate structure according to the present invention; and
- Figure 3E is a sectional view of a preferred embodiment according to the present invention.
Comme cela est représenté sur la figure 3A, on forme successivement une première couche d'oxyde de grille 22, une couche de polysilicium 23 de type n+ et une couche d'un métal réfractaire 24, sur un substrat 21. On forme une couche de SiO2 possédant une épaisseur d'environ 20 nm en tant que couche d'oxyde de grille 22, et on utilise du Ti ou du W comme métal réfractaire. As shown in FIG. 3A, a first layer of gate oxide 22, a layer of n + type polysilicon 23 and a layer of refractory metal 24, are successively formed on a substrate 21. A layer of SiO2 having a thickness of about 20 nm as the gate oxide layer 22, and Ti or W is used as the refractory metal.
Comme représenté sur la figure 3B, on corrode par photolithographie la couche de polysilicium 23 de type n+ et le métal réfractaire 24 de manière à laisser subsister une partie de la grille en polysilicium et mettre à nu la première couche d'oxyde de grille 22, puis on applique une implantation d'ions d'une impureté de type n de manière à former un drain LDD 25 de type n
Ce procédé de fabrication consistant à déposer et éliminer par corrosion le métal réfractaire Ti ou W lors de la toute première étape de fabrication pour former une grille en polysilicium comprend la formation de régions de source et de drain de type n et n+ avec autoalignement de la région de la paroi latérale de la grille en polysilicium, ce qui permet de moduler la dose de dopage pour la formation du drain LDD 25 de type n et sa longueur conformément à la conception du dispositif.As shown in FIG. 3B, the layer of n + type polysilicon 23 and the refractory metal 24 are corroded by photolithography so as to leave a part of the polysilicon grid and expose the first layer of gate oxide 22, then an implantation of ions of type n impurity is applied so as to form an LDD 25 type n drain
This manufacturing process consisting in depositing and eliminating by corrosion the refractory metal Ti or W during the very first manufacturing step to form a polysilicon grid includes the formation of source and drain regions of type n and n + with self-alignment of the region of the side wall of the polysilicon grid, which makes it possible to modulate the doping dose for the formation of the LDD 25 type n drain and its length in accordance with the design of the device.
En outre, on forme le drain LDD 25 de type n audessous de la grille en polysilicium, ce qui ne réduit pas la capacité de commande du courant sous l'effet de la résistance propre du drain et améliore l'effet des porteurs chauds, sous l'effet de la réduction de la dose de type n
De façon spécifique, on forme le drain LDD 25 de type n au-dessous de la grille en polysilicium, et on peut réduire la dégradation du dispositif par le piégeage dans l'oxyde, ce qui permet d'accroître la durée de vie moyenne.In addition, the LDD 25 type n drain is formed below the polysilicon grid, which does not reduce the current control capacity under the effect of the drain's own resistance and improves the effect of hot carriers, under the effect of type n dose reduction
Specifically, the n-type LDD 25 drain is formed below the polysilicon grid, and the degradation of the device can be reduced by trapping in the oxide, which makes it possible to increase the average lifetime.
Comme cela est représenté sur la figure 3B, on forme une grille, une source et un drain constituant fondamentalement les éléments d'un transistor MOS à effet de champ. Comme représenté sur la figure 3C, on dépose une seconde couche de polysilicium 26 de type n+ et d'une seconde couche d'oxyde 27 sur l'ensemble de la surface, et on met en oeuvre une opération de structuration. On forme ensuite une couche d'oxyde 27 selon la technique LTO (oxydation à basse température) et on effectue la structuration de manière que la grille de polysilicium possède une structure en forme de T renversé, tout en laissant subsister la couche d'oxyde 27 en tant qu'entretoise. Comme entretoise 27A, on utilise de préférence du Ta2O5 possédant une constante diélectrique élevée afin d'accroître l'effet de champ marginal. As shown in FIG. 3B, a grid is formed, a source and a drain basically constituting the elements of a field effect MOS transistor. As shown in FIG. 3C, a second layer of n + type polysilicon 26 and a second layer of oxide 27 are deposited over the entire surface, and a structuring operation is carried out. An oxide layer 27 is then formed according to the LTO (low temperature oxidation) technique and the structuring is carried out so that the polysilicon grid has an inverted T-shaped structure, while leaving the oxide layer 27 as a spacer. As spacer 27A, Ta2O5 is preferably used having a high dielectric constant in order to increase the marginal field effect.
On peut avantageusement déterminer l'entretoise conforme à la présente invention au moyen des conditionnements de la corrosion RIE (corrosion ionique réactive) plutôt qu'au moyen de la modulation de l'épaisseur de l'oxydation LTO au moyen des sélectivités de corrosion du métal réfractaire. It is advantageously possible to determine the spacer in accordance with the present invention by means of the RIE (reactive ionic corrosion) corrosion conditionings rather than by means of the modulation of the thickness of the LTO oxidation by means of the corrosion selectivities of the metal. refractory.
Comme représenté sur la figure 3D, on élimine la seconde couche d'oxyde restante 27, hormis au niveau de la région de l'entretoise et de la couche de polysilicium 26 de type n+ formée sur la grille en polysilicium, et on applique une implantation ionique de type n+ pour former le transistor LDD MOS à effet de champ à une structure de grille en forme de T renversé. As shown in FIG. 3D, the second remaining oxide layer 27 is eliminated, except at the region of the spacer and of the n + type polysilicon layer 26 formed on the polysilicon grid, and an implantation is applied. n + type ion to form the field effect LDD MOS transistor in an inverted T-shaped gate structure.
On transforme en siliciure la couche métallique 24 mise à nu sous l'effet de l'opération de corrosion, illustrée sur la figure 3D, lors de la fabrication du dispositif considéré. Comme cela est représenté sur la figure 3E, on pourrait utiliser le transistor LDD MOS à effet de champ à structure de grille en forme de T renversé, conforme à la présente invention, pour fabriquer un transistor NMOS à effet de champ selon un procédé de fabrica tion CMOS. C'est-à-dire que l'on peut former le transistor
LDD à effet de champ à structure de grille en forme de T renversé conforme à la présente invention dans la région de puits de type P 29 en tant que région active formée à l'intérieur de la couche d'oxyde de champ 28 pour la séparation du dispositif.The metal layer 24 exposed under the effect of the corrosion operation, illustrated in FIG. 3D, is transformed into silicide during the manufacture of the device considered. As shown in FIG. 3E, the LDD MOS field effect transistor with inverted T-shaped gate structure, in accordance with the present invention, could be used to manufacture an NMOS field effect transistor according to a manufacturing process. CMOS. That is to say that we can form the transistor
Field effect LDD with inverted T-shaped grid structure according to the present invention in the P-type well region 29 as an active region formed within the field oxide layer 28 for separation of the device.
On raccorde le dispositif décrit précédemment à un transistor PMOS à effet de champ voisin de manière à former une structure CMOS et on l'applique à un dispositif de mémoire tel qu'une mémoire ROM (mémoire morte), une mémoire RAM (mémoire à accès direct) et analogue, et/ou à un dispositif à semiconducteurs utilisant un transistor MOS à effet de champ. The device described above is connected to a PMOS transistor with neighboring field effect so as to form a CMOS structure and it is applied to a memory device such as a ROM memory (read-only memory), a RAM memory (access memory direct) and the like, and / or a semiconductor device using a field effect MOS transistor.
Ce procédé de fabrication est aisé à mettre en oeuvre et on obtient un contrôle approprié de la fabrication étant donné que le masque servant à la structuration de la grille en polysilicium est utilisé une seule fois lors de la première étape opératoire, de manière à former le drain LDD de type n et de type n+. En outre, la modulation de l'épaisseur à l'aide de la technique RIE est beaucoup plus facile à mettre en oeuvre que la modulation classique d'épaisseur au moyen de la technique LTO. Aucune couche inutile n'est formée dans la structure de grille en polysilicium, comme c'était le cas dans l'art antérieur, et on obtient un transistor LDD MOS à effet de champ à structure en forme de T renversé perfectionné, qui permet de réduire l'effet de champ électrique latéral maximum. This manufacturing process is easy to implement and an appropriate manufacturing control is obtained since the mask used to structure the polysilicon grid is used only once during the first operating step, so as to form the n-type and n-type LDD drain. In addition, the modulation of the thickness using the RIE technique is much easier to implement than the conventional thickness modulation using the LTO technique. No unnecessary layer is formed in the polysilicon gate structure, as was the case in the prior art, and an LDD MOS transistor with field effect with an inverted T-shaped structure is improved, which allows reduce the maximum lateral electric field effect.
Claims (11)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR910003121 | 1991-02-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| FR2673326A1 true FR2673326A1 (en) | 1992-08-28 |
Family
ID=19311519
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR9116243A Pending FR2673326A1 (en) | 1991-02-26 | 1991-12-27 | MOS LDD field-effect transistor with gate structure in the shape of an inverted T, and method of fabricating it |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPH04317339A (en) |
| DE (1) | DE4143115A1 (en) |
| FR (1) | FR2673326A1 (en) |
| GB (1) | GB9127093D0 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0591599A1 (en) * | 1992-09-30 | 1994-04-13 | STMicroelectronics S.r.l. | Method of fabricating integrated devices, and integrated device produced thereby |
| US5568418A (en) * | 1992-09-30 | 1996-10-22 | Sgs-Thomson Microelectronics S.R.L. | Non-volatile memory in an integrated circuit |
| US5798279A (en) * | 1992-09-30 | 1998-08-25 | Sgs-Thomson Microelectronics S.R.L. | Method of fabricating non-volatile memories with overlapping layers |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7064027B2 (en) | 2003-11-13 | 2006-06-20 | International Business Machines Corporation | Method and structure to use an etch resistant liner on transistor gate structure to achieve high device performance |
| CN102074583B (en) * | 2010-11-25 | 2012-03-07 | 北京大学 | Low power consumption composite source structure MOS (Metal Oxide for and preparation method thereof |
| US9543427B2 (en) | 2014-09-04 | 2017-01-10 | Panasonic Intellectual Property Management Co., Ltd. | Semiconductor device and method for fabricating the same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6032354A (en) * | 1983-08-02 | 1985-02-19 | Matsushita Electronics Corp | Semiconductor integrated circuit |
| US4808544A (en) * | 1987-03-06 | 1989-02-28 | Oki Electric Industry Co., Ltd. | LDD structure containing conductive layer between gate oxide and sidewall spacer |
| EP0355691A2 (en) * | 1988-08-23 | 1990-02-28 | Seiko Epson Corporation | Semiconductor device and process for producing the same |
| US4951100A (en) * | 1989-07-03 | 1990-08-21 | Motorola, Inc. | Hot electron collector for a LDD transistor |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59205759A (en) * | 1983-04-01 | 1984-11-21 | Hitachi Ltd | Mis type field-effect transistor |
| JPH01149449A (en) * | 1987-12-04 | 1989-06-12 | Fujitsu Ltd | Cmos semiconductor device and manufacture thereof |
-
1991
- 1991-12-20 GB GB919127093A patent/GB9127093D0/en active Pending
- 1991-12-23 DE DE4143115A patent/DE4143115A1/en not_active Ceased
- 1991-12-27 FR FR9116243A patent/FR2673326A1/en active Pending
-
1992
- 1992-01-28 JP JP4013009A patent/JPH04317339A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6032354A (en) * | 1983-08-02 | 1985-02-19 | Matsushita Electronics Corp | Semiconductor integrated circuit |
| US4808544A (en) * | 1987-03-06 | 1989-02-28 | Oki Electric Industry Co., Ltd. | LDD structure containing conductive layer between gate oxide and sidewall spacer |
| EP0355691A2 (en) * | 1988-08-23 | 1990-02-28 | Seiko Epson Corporation | Semiconductor device and process for producing the same |
| US4951100A (en) * | 1989-07-03 | 1990-08-21 | Motorola, Inc. | Hot electron collector for a LDD transistor |
Non-Patent Citations (2)
| Title |
|---|
| IBM TECHNICAL DISCLOSURE BULLETIN. vol. 32, no. 3B, Août 1989, NEW YORK US pages 154 - 155; 'METHOD FOR MAKING SELF-ALIGNED, REVERSE-T GATE LDD MOSFET' * |
| PATENT ABSTRACTS OF JAPAN vol. 009, no. 150 (E-324)25 Juin 1985 & JP-A-60 032 354 ( MATSUSHITA DENSHI KOGYO KK ) 19 Février 1985 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0591599A1 (en) * | 1992-09-30 | 1994-04-13 | STMicroelectronics S.r.l. | Method of fabricating integrated devices, and integrated device produced thereby |
| US5464784A (en) * | 1992-09-30 | 1995-11-07 | Sgs-Thomson Microelectronics S.R.L. | Method of fabricating integrated devices |
| US5568418A (en) * | 1992-09-30 | 1996-10-22 | Sgs-Thomson Microelectronics S.R.L. | Non-volatile memory in an integrated circuit |
| US5798279A (en) * | 1992-09-30 | 1998-08-25 | Sgs-Thomson Microelectronics S.R.L. | Method of fabricating non-volatile memories with overlapping layers |
| US5977586A (en) * | 1992-09-30 | 1999-11-02 | Stmicroelectronics S.R.L. | Non-volatile integrated low-doped drain device with partially overlapping gate regions |
Also Published As
| Publication number | Publication date |
|---|---|
| DE4143115A1 (en) | 1992-09-03 |
| JPH04317339A (en) | 1992-11-09 |
| GB9127093D0 (en) | 1992-02-19 |
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