JPH04315466A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To solve the problem of a delay of clock signal in integrated circuit, which problem arises inevitably as the technique of the integrated circuit is developed in the future. CONSTITUTION:For the purpose of actuating a high-speed and large-scale integrated circuit chip by the same clock, the chip 101 is divided into several regions 102 being of a size where the delay of the clock can be disregarded and each of these divided regions is provided with clock junctions 104, 105, where the delay from a clock introduction terminal 103 is corrected or accurately known, so that a circuit in that region is actuated by a clock distributed from these junctions 104, 105. The large chip is divided into small regions and each of those small regions is provided with a junction, where the delay of time from an input terminal is evident, so that it is easy to time respective circuits constituting an integrated circuit to enable efficiently making a high-speed and large- scale integrated circuit.

Description

[Detailed description of the invention]

[Purpose of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a very large-scale semiconductor integrated circuit device that operates at high speed.

0002

[Prior Art] Recent advances in Si integrated circuits, mainly CMOS, have been remarkable;
MPUs that operate on the same technology have also been developed. That is, in addition to integrating a large number of transistors on one chip,
Its operating speed has also improved significantly, and since 2000
Even the appearance of a CMOS chip that integrates 5,000 transistors and operates at 500 MHz is being discussed as a possible realization in 2019. This is because in a MOS transistor, the performance of the transistor improves as the size becomes smaller due to the scaling law. In addition, the technology of bipolar ICs is rapidly advancing, catching up with MOS, and it is believed that the delay time per gate will approach 10 ps in the next ten years.

However, an increase in the degree of integration inevitably leads to an increase in the size of chips, and it is thought that chips in the year 2000 will have a side length of as much as 1 inch. This fact makes it difficult to increase the speed of integrated circuits. This is because, for example, even light can only move 3 mm in 10 ps, so in a large chip with a side length of 1 inch, it takes time to transmit signals, and the entire chip cannot be clocked using the same clock as before. It is impossible to move. Therefore, in order to further increase the speed of ICs in the future, it is thought that the conventional method of transmitting a clock signal on a chip from one terminal to control the entire chip will have to be changed.

0004

SUMMARY OF THE INVENTION The present invention is directed to solving the problem of clock signal delays in integrated circuits that will inevitably occur as integrated circuit technology progresses in the future. [Structure of the invention]

[0005]

[Means for Solving the Problems] The present invention provides a semiconductor integrated circuit device which is controlled in whole or in part by a clock signal, including a plurality of divided semiconductor circuit regions;
an input terminal provided on the divided semiconductor region,
A semiconductor integrated circuit device characterized in that a predetermined input terminal is an external clock signal input terminal for inputting an external clock signal, and other input terminals are branch points from the external clock signal input terminal. .

[0006]

[Operation] In order to operate a high-speed, large-scale integrated circuit chip with the same clock, the present invention divides the chip into several areas of such size that the clock delay can be ignored. In each area, a clock branch point is provided in which the delay from the clock introduction terminal is corrected or the delay is accurately known, and the circuits in that area are operated with the clock distributed from this branch point.

[0007] The present invention divides the inside of a chip into several small regions and controls each of the small regions with a clock signal from a clock branch point, and the clock signal at each clock branch point is input from an input terminal. Since the delay is corrected or known, the entire integrated circuit can be controlled with a single clock signal. Further, at this time, if a current signal, such as a signal that changes the current value, is used instead of the conventionally used voltage signal as the clock signal, the signal delay itself can be reduced because it is not affected by the load of the wiring.

[0008]

[Embodiments] Examples of the invention will be described below.

In this embodiment, an integrated circuit in which a bipolar transistor and a CMOS are mixedly mounted on a Si substrate is taken as an example. The process used to create the actual integrated circuit was the Bi-CMOS process commonly used today.

FIG. 1 is a schematic diagram of an embodiment of a high-speed integrated circuit made by applying the present invention. The actual dimensions of the chip excluding the glue allowance are 21 mm x 6 mm. This chip (101) has a size of 3 mm x 3 mm.
It is divided into four small areas (102). The external clock signal is introduced from approximately the center on the left side of the chip, and is connected to the standard external clock signal input terminal (103).
A branch point (
104) And a branch point 3mm further away (105)
And then there are the straight lines (
106) transmitted by. In this embodiment, a method is adopted in which the current value is changed as the clock signal, so the clock signal takes 10 ps to reach the next branch point.
delay. The circuits in each small area were operated based on the clock signal from the branch point of this clock signal. Since a voltage signal is easier to handle as a clock signal, it is conceivable to use a voltage signal as the signal within this small area, but in this embodiment, a current signal is used as the clock signal throughout the entire chip. A circuit to amplify the current signal is installed at each branch point to prevent the current signal from attenuating. In this way, in this embodiment, a clock reference point with a known delay from the input clock signal is installed in the divided small areas, so the timing between each circuit making up the integrated circuit can be easily adjusted. It has become possible to operate large-scale integrated circuits with long sides as long as 1 inch at speeds of 500 MHz.

[0011]

Effects of the Invention In the present invention, a large chip is divided into small areas, and a branch point with a clear time delay from the input terminal is installed in each of the small areas. This makes it easier to determine the timing of the process, making it possible to efficiently create large-scale integrated circuits at high speed.

[Brief explanation of drawings]

FIG. 1: Schematic diagram of one embodiment of the present invention

[Explanation of symbols]

101...Chip 102...Small area obtained by dividing the chip (divided semiconductor circuit area) 103...External clock signal input terminal 104...A branch point 3 mm away from the external clock signal input terminal 105...A branch point 6 mm away from the external clock signal input terminal

Claims (1)

[Claims] 1. A semiconductor integrated circuit device that is wholly or partially controlled by a clock signal, comprising: a divided semiconductor circuit area divided into a plurality of parts; and an input terminal provided on the divided semiconductor circuit area; 1. A semiconductor integrated circuit device, wherein a predetermined input terminal is an external clock signal input terminal for inputting an external clock signal, and other input terminals are branch points from the external clock signal input terminal.