JPS62213155A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce labor required for development, and to shorten the time for development by connecting a delay circuit and parting sections by using at least one mask or directly connecting the parting section in a connecting wire. CONSTITUTION:In an address buffer 4, parting sections in a buffer circuit 40 are connected through a delay circuit 41 and a connecting wire 43 or connected directly by the connecting wire 43. Consequently, the connecting wire 43 can be formed by using either of a pattern at a time when the parting sections between the delay circuit 41 and the buffer circuit 40 are connected and a pattern at a time when the parting sections are connected directly. Accordingly, the connecting wire can be shaped by at least one mask, thus reducing labor required for development while largely shortening the time for development.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to a semiconductor memory device.

[Conventional technology]

Recently, the operating speed of semiconductor memory devices, particularly MO5O5 rastic RAMs, has improved significantly due to improvements in process technology, and some devices have access times of 25 to 55 ns. MOS thruster static RAM having such an access time is used as a cache memory for computers, and has also begun to enter fields previously dominated by bipolar RAM.

In general, the faster an IC operates, the more susceptible it is to noise, and the two-layer printed circuit board has high impedance for M, source lines, and ground lines, and poor shielding of signal lines.
Easy to generate noise. Therefore, when the high-speed MO5O5 lastatic A) 4 is attached to a two-layer printed circuit board and used, an oscillation phenomenon may occur and malfunction may occur. For this reason, in microcomputer-applied products that use inexpensive double-layer printed circuit boards, the access time is still 1.
A slow MO5O5 rasteristic M of 00 to 200 ns is used.

High speed MO5O5 rastic M is according to the standard as low speed MO
Although it is intended to replace 5O5 rasteristic RAM, in reality, it cannot be replaced because it is susceptible to noise as described above, and both coexist.

[Problem that the invention seeks to solve]

However, in conventional semiconductor memory devices, low-speed and high-speed chips are designed separately, and dedicated masks are designed for each according to the design, which results in a large amount of development effort and time. there were.

(Means for Solving the Problems) The present invention aims to reduce the labor required for developing semiconductor memory devices and shorten the development time, and includes a memory array in which semiconductor memory devices are arranged in rows and columns;
A row decoder that specifies a row of the memory array, a column decoder that specifies a column of the memory array, an address buffer that supplies signals in phase and in phase with an external address signal to the row decoder and column decoder, and the memory cell an output buffer that amplifies the signal from and outputs it to the outside;
It is composed of a delay circuit and a connection line formed on a component in which a part of the circuit is separated among each component, and the connection line is connected to the 111th delay circuit and the separation point using at least one mask. or directly connect the separated points.

〔Example〕

FIG. 1 shows an embodiment of the invention. This shows an example in which a delay circuit and a connection line are formed only in the address buffer. In the figure, 1 is a memory array in which memory cells are arranged in rows and columns, 2 is a row decoder that specifies a row of this memory array 1, and 3 is a column decoder that specifies a column of the memory array 1.

4 is an address buffer, as shown in FIG. 2, it is composed of a buffer circuit 40, a delay circuit 41, and a connection line 43, and as shown in FIG. i&! 1I43, and FIG. 3 shows an example in which the cut points are directly connected by a connecting line 43. The buffer circuit 40 includes inverters 40a to 40.4 connected in series between terminals A and a. The inverter 40e and 40f are connected in series between the inverters 40e and 40d and between the terminal 3, and the inverter 40a and the inverter 40b are separated.

The delay circuit 41 includes an inverter 41a connected in series.
~41d. A signal with the same phase as the external signal is sent from terminal a, and a signal with the opposite phase from terminal i is sent to the row and column decoders 2.
, 3. 5 amplifies the signal from the memory cell specified by the row and column decoder 2.3, and sends the amplified signal to the terminal C.
This is an output buffer that outputs from.

In the semiconductor memory device of this embodiment, in the address buffer 4, the divided portion of the buffer circuit 40 is connected via the delay circuit 41 and the connection line 43, or directly connected to the connection line 43, so that the connection i! 1143 is
It can be formed using either a pattern for connecting the separated portions of the delay circuit 41 and the buffer circuit 40, or a pattern for directly connecting the separated portions.

When the divided parts of the buffer circuit 40 are directly connected by the connection line 43, the access time, that is, the time from when an input signal is applied to terminal A until the data of the desired memory cell appears at terminal C, is the address buffer. 41 lines,
Column decoder 2゜3, memory cell 1 and output buffer 5
is the total response time in . In this case, high-speed access is required.

Further, when the delay circuit 41 and the part where the buffer circuit 40 is separated are connected via the connection 1143, the access time is the sum of the above response time and the delay time of the delay circuit 41. In this case, use slow access.

In the above embodiment, the address buffer 4 is connected to the delay circuit 41, ! Although an example in which a43 is formed has been described, even if these are formed in at least one of the memory array 1, the row and column decoders 2 and 3, and the output buffer 5, there is no difference in operation and effect from the previous embodiment.

〔Effect of the invention〕

In the present invention, since the connection line is formed by at least one square, it is possible to reduce the development effort and to significantly shorten the development time.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIGS. 2 and 3 are diagrams showing specific examples of the address buffer 4 shown in FIG. 1, and FIG. 2 shows dividing points and delays. FIG. 3 shows an example in which the circuit 41 is connected to the circuit 41 by a connecting line 43, and FIG. In the figure, 1 is a memory array, 2 is a row decoder, 3 is a column decoder, 4 is an address buffer, 5 is an output buffer, 40 is a buffer circuit, and 4! is a delay circuit, and 43 is a connection line.

Claims (1)

[Claims] A memory array arranged in a matrix, a row decoder that specifies the row of this memory array, a column decoder that specifies the column of the memory array, and signals that are in phase and in phase with an external address signal are sent to these row decoders and column decoders. An address buffer to be supplied, an output buffer that amplifies the signal from the memory cell and outputs it to the outside, and a delay circuit and connection line formed on a component from which a part of the circuit is separated among these components. 2. A semiconductor memory device comprising: a semiconductor memory device, wherein the connection line connects the delay circuit and the divided portion using at least one mask, or directly connects the divided portion.