JPH04312964A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH04312964A
JPH04312964A JP6984291A JP6984291A JPH04312964A JP H04312964 A JPH04312964 A JP H04312964A JP 6984291 A JP6984291 A JP 6984291A JP 6984291 A JP6984291 A JP 6984291A JP H04312964 A JPH04312964 A JP H04312964A
Authority
JP
Japan
Prior art keywords
leads
semiconductor device
lead
width
extended
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6984291A
Other languages
Japanese (ja)
Inventor
Hajime Kato
肇 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP6984291A priority Critical patent/JPH04312964A/en
Publication of JPH04312964A publication Critical patent/JPH04312964A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce deterioration of a soldered part of a lead of a semiconductor device to a circuit board due to a thermal stress by increasing the width of a position at which the lead is extended, the wider the separated more separated the lead from the central position of a resin-molded package. CONSTITUTION:A semiconductor device 1 has a plurality of leads 30-33 extended from both ends of a resin-molded package 2, and the leads 30-33 are soldered to a circuit board 4. However, A3>A2>A1>A0 is satisfied, where A0 is the width of two leads 30 extended from both right and left end positions nearest the central position O of the package 2, A1 is the width of the four leads 31 extended from both right and left end positions near the position O, A2 is the width of the four leads extended from both the right and left end positions near the position O, and A3 is the width of the four leads 33 extended from both the right and left end positions near the position O.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、回路基板に表面実装さ
れる半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device surface-mounted on a circuit board.

【0002】0002

【従来の技術】図3は、従来の表面実装タイプの半導体
装置10であり、同図において、2は樹脂モールドパッ
ケージ、3はこのパッケージ2の両端から導出される複
数のリードである。この半導体装置10の各リード3は
、同一の幅Aとなっており、同一のピッチ間隔Bで形成
されている。
2. Description of the Related Art FIG. 3 shows a conventional surface-mount type semiconductor device 10. In the figure, 2 is a resin molded package, and 3 is a plurality of leads led out from both ends of this package 2. Each lead 3 of this semiconductor device 10 has the same width A and is formed with the same pitch interval B.

【0003】この半導体装置10は、複数のリード3の
斜線で示される部分(リード幅A×半田付長C)が、図
4に示されるように回路基板4に半田付されて実装され
る。なお、図4において5は半田付部分である。
This semiconductor device 10 is mounted by soldering the hatched portions (lead width A×soldering length C) of the plurality of leads 3 to a circuit board 4 as shown in FIG. In addition, in FIG. 4, 5 is a soldered part.

【0004】0004

【発明が解決しようとする課題】このようにして半導体
装置10を回路基板4に実装した後に、温度サイクル試
験を実施すると、樹脂モールドパッケージ2およびリー
ド3に比べて回路基板4の線膨張係数が小さいために、
リード3の半田付部分5には、熱応力が発生することに
なり、この熱応力は、樹脂モールドパッケージ2の中央
位置Oから離れた位置(図3において上側および下側)
のリード3ほど大きくなり、かかるリードの半田付部分
5が劣化しやすいという難点がある。
[Problems to be Solved by the Invention] When a temperature cycle test is performed after the semiconductor device 10 is mounted on the circuit board 4 in this manner, it is found that the coefficient of linear expansion of the circuit board 4 is lower than that of the resin mold package 2 and the leads 3. Because of its small size,
Thermal stress will occur in the soldered portion 5 of the lead 3, and this thermal stress will occur at positions away from the center position O of the resin molded package 2 (upper and lower sides in FIG. 3).
The problem is that the lead 3 becomes larger and the soldered portion 5 of the lead easily deteriorates.

【0005】本発明は、上述の点に鑑みて為されたもの
であって、半導体装置のリードと回路基板との半田付部
分の熱応力による劣化を低減することを目的とする。
The present invention has been made in view of the above-mentioned points, and an object of the present invention is to reduce deterioration due to thermal stress of the soldered portion between the lead of a semiconductor device and a circuit board.

【0006】[0006]

【課題を解決するための手段】本発明では、上述の目的
を達成するために、次のように構成している。
[Means for Solving the Problems] In order to achieve the above-mentioned object, the present invention is constructed as follows.

【0007】すなわち、本発明は、樹脂モールドパッケ
ージの両端から導出される複数のリードを有し、前記リ
ードが回路基板に半田付けされる表面実装タイプの半導
体装置において、リードの導出される位置が、樹脂モー
ルドパッケージの中央位置から離れたリードほどその幅
を広くしている。
That is, the present invention provides a surface mount type semiconductor device having a plurality of leads led out from both ends of a resin molded package, and in which the leads are soldered to a circuit board, in which the positions where the leads are led out are , the width of the leads is made wider as they are farther away from the center of the resin molded package.

【0008】[0008]

【作用】上記構成によれば、導出位置が、樹脂モールド
パッケージの中央位置から離れたリードほどその幅を広
くしているので、回路基板との半田付面積もその分だけ
大きくなり、これによって、温度サイクル試験において
、中央位置から離れた位置のリードの半田付部分の熱応
力が、従来例に比べて低減されることになる。
[Function] According to the above structure, the lead-out position is wider as the leads are farther away from the center position of the resin molded package, so the soldering area with the circuit board is also increased accordingly. In the temperature cycle test, the thermal stress of the soldered portion of the lead at a position away from the center position is reduced compared to the conventional example.

【0009】[0009]

【実施例】以下、図面によって本発明の実施例について
、詳細に説明する。
Embodiments Hereinafter, embodiments of the present invention will be explained in detail with reference to the drawings.

【0010】図1は、本発明の一実施例の半導体装置1
の平面図であり、図2はその正面図であり、上述の従来
例に対応する部分には、同一の参照符を付す。
FIG. 1 shows a semiconductor device 1 according to an embodiment of the present invention.
FIG. 2 is a front view thereof, and parts corresponding to the conventional example described above are given the same reference numerals.

【0011】この実施例の半導体装置1は、樹脂モール
ドパッケージ2の両端から導出される複数のリード30
〜33を有し、これらのリード30〜33が、図4の従
来例と同様にして回路基板4に半田付けされる表面実装
タイプである。
The semiconductor device 1 of this embodiment has a plurality of leads 30 led out from both ends of the resin mold package 2.
33, and these leads 30 to 33 are of a surface mount type in which these leads 30 to 33 are soldered to the circuit board 4 in the same manner as in the conventional example shown in FIG.

【0012】この実施例では、温度サイクル試験におけ
る熱応力によって半田付部分が劣化するのを低減するた
めに、リード30〜33の導出される位置が、樹脂モー
ルドパッケージ2の中央位置Oから離れるにつれて該リ
ード30〜33の幅A0〜A3を広くしている。
In this embodiment, in order to reduce the deterioration of the soldered parts due to thermal stress in the temperature cycle test, the positions from which the leads 30 to 33 are led out gradually change as the distance from the central position O of the resin mold package 2 increases. The widths A0 to A3 of the leads 30 to 33 are widened.

【0013】すなわち、樹脂モールドパッケージ2の中
央位置Oに最も近い左右の両端位置からそれぞれ導出さ
れている2本のリード30の幅をA0、次に中央位置O
に近い左右の両端位置からそれぞれ導出されている4本
のリード31の幅をA1、さらに次に中央位置Oに近い
左右の両端位置からそれぞれ導出されている4本のリー
ド32の幅をA2、次に中央位置Oに近い左右の両端位
置からそれぞれ導出されている4本のリード33の幅を
A3とすると、 A3>A2>A1>A0 としている。
That is, the width of the two leads 30 led out from the left and right end positions closest to the center position O of the resin molded package 2 is A0, and then the width is set to the center position O.
A1 is the width of the four leads 31 that are respectively led out from the left and right end positions near the center position O, and A2 is the width of the four leads 32 that are each led out from the left and right end positions that are near the center position O. Next, if the width of the four leads 33 respectively derived from the left and right end positions near the center position O is A3, then A3>A2>A1>A0.

【0014】なお、各リード30〜33のピッチ間隔B
および半田付長Cは、従来と同様である。
Note that the pitch interval B of each lead 30 to 33 is
And the soldering length C is the same as the conventional one.

【0015】この実施例では、樹脂モールドパッケージ
2の中央位置Oから離れたリード30〜33ほど、斜線
で示される半田付面積が大きくなり、これによって、温
度サイクル試験において、中央位置Oから離れた位置の
リードの半田付部分の熱応力が、従来例に比べて低減さ
れることになり、半田付部分の劣化が抑制されることに
なる。
In this embodiment, the further the leads 30 to 33 are from the center position O of the resin mold package 2, the larger the soldering area shown by diagonal lines. Thermal stress on the soldered portion of the lead at the position is reduced compared to the conventional example, and deterioration of the soldered portion is suppressed.

【0016】さらに、樹脂モールドパッケージ2の端に
位置するリード30〜33ほどその幅を広くしているの
で、リード30〜33の変形が発生しにくくなって回路
基板4への半田付けが安定して行えることになる。
Furthermore, since the leads 30 to 33 located at the ends of the resin molded package 2 have a wider width, deformation of the leads 30 to 33 is less likely to occur and the soldering to the circuit board 4 is stabilized. This means that you can do it.

【0017】上述の実施例では、ガルウィングタイプの
リードに適用して説明したけれども、Jベンドタイプの
リードにも同様に適用できるのは勿論である。
Although the above-described embodiments have been described with reference to gull-wing type leads, it is of course applicable to J-bend type leads as well.

【0018】上述の実施例では、樹脂モールドパッケー
ジ2が対称である半導体装置1に適用して説明したけれ
ども、非対称であっても中央位置からの距離に基づいて
同様に適用できるものである。
Although the above-described embodiment has been described with reference to the semiconductor device 1 in which the resin mold package 2 is symmetrical, the present invention can similarly be applied even if the resin mold package 2 is asymmetrical based on the distance from the center position.

【0019】[0019]

【発明の効果】以上のように本発明によれば、導出位置
が、樹脂モールドパッケージの中央位置から離れたリー
ドほどその幅を広くしているので、前記中央位置から離
れたリードほど回路基板との半田付面積が大きくなり、
これによって、中央位置から離れた位置のリードの半田
付部分の熱応力が、従来例に比べて低減されることにな
り、半田付部分の劣化を抑制することができる。
As described above, according to the present invention, the lead-out position is wider as the leads are farther away from the center position of the resin molded package, so that the leads farther from the center position are closer to the circuit board. The soldering area becomes larger,
As a result, the thermal stress on the soldered portions of the leads located away from the center position is reduced compared to the conventional example, and deterioration of the soldered portions can be suppressed.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明の一実施例の平面図である。FIG. 1 is a plan view of an embodiment of the present invention.

【図2】図1の実施例の正面図である。FIG. 2 is a front view of the embodiment of FIG. 1;

【図3】従来例の平面図である。FIG. 3 is a plan view of a conventional example.

【図4】半導体装置を回路基板に実装した状態を示す図
である。
FIG. 4 is a diagram showing a semiconductor device mounted on a circuit board.

【符号の説明】[Explanation of symbols]

1,10         半導体装置2      
        樹脂モールドパッケージ3,30〜3
3    リード
1,10 Semiconductor device 2
Resin mold package 3, 30-3
3 lead

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  樹脂モールドパッケージの両端から導
出される複数のリードを有し、前記リードが回路基板に
半田付けされる表面実装タイプの半導体装置において、
リードの導出される位置が、樹脂モールドパッケージの
中央位置から離れたリードほどその幅を広くしたことを
特徴とする半導体装置。
1. A surface mount type semiconductor device having a plurality of leads led out from both ends of a resin molded package, the leads being soldered to a circuit board, comprising:
A semiconductor device characterized in that a position from which a lead is led out is wider as the lead is farther away from the center of a resin molded package.
JP6984291A 1991-04-02 1991-04-02 Semiconductor device Pending JPH04312964A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6984291A JPH04312964A (en) 1991-04-02 1991-04-02 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6984291A JPH04312964A (en) 1991-04-02 1991-04-02 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH04312964A true JPH04312964A (en) 1992-11-04

Family

ID=13414464

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6984291A Pending JPH04312964A (en) 1991-04-02 1991-04-02 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH04312964A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6120059B2 (en) * 1978-05-18 1986-05-20 Torio Kk
JPH02143450A (en) * 1988-11-25 1990-06-01 Hitachi Ltd Lead frame

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6120059B2 (en) * 1978-05-18 1986-05-20 Torio Kk
JPH02143450A (en) * 1988-11-25 1990-06-01 Hitachi Ltd Lead frame

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