JPH04312154A - Terminal equipment - Google Patents

Abstract

PURPOSE:To quickly deal with the data transfer request given from a line even though a processor included in a terminal equipment is processing the data stored in a memory. CONSTITUTION:A processor 5 gives a request to a memory control part 6 for use of a dual port memory 7 and then outputs a memory control signal 14 received from the part 6 to the memory 7. If a data transfer request is given to a data converter 9 from a line while the processor 5 is using the memory 7, the circuit data request information is transmitted to a line control part 8 and the memory 7 can transfer the line data to the converter 9. The serial data received from a host system are converted into the parallel data by the converter 9 and written into the memory 7. When the data are sent to the host system, the parallel data read by the memory 7 are converted into the serial data by the converter 9 and outputted to the line.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a terminal device.

0002

2. Description of the Related Art In conventional terminal devices, when a data transfer request is generated from a line while a processor is using a file memory, the data transfer request waits until the processor finishes using the file memory. .

0003

[Problems to be Solved by the Invention] In this conventional terminal device, if a data transfer request is received from the line while the processor is using the file memory, the processor will not respond to the data transfer request from the line unless the processor finishes using the file memory. Therefore, there was a problem in that it took a long time to complete the data transfer request from the line.

0004

[Means for Solving the Problems] A terminal device of the present invention includes a display section that displays information, a display control section that controls this display section, an operation section that inputs information, and an operation that controls this operation section. a control unit, a file memory that stores information, a memory control unit that controls this file memory, and converts information from a line or internal between serial and parallel formats and sends it to the internal or line. In a terminal device that includes a data conversion circuit, a line control unit that controls the data conversion circuit, and a processor that processes the information, the file memory has two buses, one on the processor side and one on the data conversion circuit side. It is characterized by being a dual port memory that allows memory access from and to the computer independently.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a terminal device of the present invention.

The terminal device of this embodiment includes a display section 1 for displaying information, a display control section 2 for controlling the display section 1, an operation section 3 for inputting information, and an operation control section for controlling the operation section 3. 4
, a dual port memory 7 for information storage that has two buses and allows memory access from two directions simultaneously and independently, a processor 5 that processes information, and a dual port memory 7 that has two buses and allows memory access from two directions simultaneously and independently. a memory control unit 6 that controls memory access requested by the processor 5; a data conversion circuit 9 that converts information from the line or internal between serial and parallel formats and sends it to the internal or line; The circuit controller 8 includes a line controller 8 that controls access to data related to the data conversion circuit 9 from the dual port memory 7. Display control signal 1
1 is output from the display control section 2 and controls the display on the display section 1. The operation control signal 12 is instruction data input manually through the operation unit 3. Processor 5 is system bus 1
I/O access and memory access are realized via 0.

Next, the operation of the terminal device of this embodiment will be explained. The processor 5 requests the memory control unit 6 to use the dual port memory 7 via the system bus 10, and the memory control unit 6 outputs a memory control signal 14 to the dual port memory 7 to communicate with the processor 5. This allows access to and from the dual port memory 7. Address and data bus 13 is used for memory address and data signals for processor 5. When a data transfer request is made from the line to the data conversion circuit 9 while the processor 5 is using the dual port memory 7, the line data request information is transmitted to the line control unit 8 by the line control signal 16, and the line control unit 8 transfers the data from the line to the data conversion circuit 9. - Transmit a line data transfer request to the port memory 7 using the line file control signal 15; By receiving a line data transfer request, dual port memory 7 enables line data transfer with data conversion circuit 9 via address data bus 17. Serial data sent from the host system via the line is converted into parallel data by the data conversion circuit 9 and written into the dual port memory 7. Conversely, when data is to be sent to the host system, the dual port memory 7 reads the parallel data, converts it into serial data in the data conversion circuit 9, and outputs it to the line.

[0008]

[Effects of the Invention] As explained above, the present invention uses a dual port memory for the file memory of the terminal device, so even when the processor in the terminal device is processing data in the memory, it is possible to This has the effect of quickly responding to data transfer requests.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a terminal device of the present invention.

[Explanation of symbols]

1 Display section 2 Display control section 3 Operation section 4 Operation control section 5 Processor 6 Memory control section 7 Dual port memory 8 Line control section 9 Data conversion circuit 10 System bus 11 Display control signal 12 Operation control signal 13, 17 Address・Data bus 14
Memory control signal 15 Line memory control signal 16 Line control signal

Claims (1)

[Claims] [Claim 1] A display section that displays information, a display control section that controls this display section, an operation section that inputs information, an operation control section that controls this operation section, and a file that stores information.・Memory, a memory control unit that controls this file memory, a data conversion circuit that converts information from a line or internal between serial and parallel formats and sends it to the internal or line, and controls this data conversion circuit. In the terminal device, the file memory has two buses to enable independent memory access from the processor side and the data conversion circuit side. A terminal device characterized by having dual port memory.