JPH04308954A - Dmac compatible processor - Google Patents

Abstract

PURPOSE:To provide a DMAC(direct memory access controller) processor having the same size, the number of pins, and the pin arrangement as those of the conventional DMAC, and having both a DMAC function and a data processing function (for example, fuzzy infrence arithmetic function). CONSTITUTION:This device is equipped with a fuzzy input and output register 32, and fuzzy inference part 31 in addition to a DMAC control part 21. The DMAC control part 21 inputs and outputs input data necessary for the fuzzy inference part 31, and output data indicating the inference result of the fuzzy inference part 31, by a DMA transfer, in addition to the normal DMA transfer.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMAC compatible processor, a DMA transfer device, a processor with a DMA function, a computer system, a DMAC compatible fuzzy processor, a method of operating a DMAC compatible processor, and a DMA transfer method.

[0002] Here, DMA is a direct memory access (
Direct Memory Access), and DMAC stands for Direct Memory Access Controller (Direct Memory Access).
Direct Memory Access Cont.
roller).

0003

2. Description of the Related Art In systems incorporating one or more processors, the processors are connected to an address bus, a data bus, and a control bus on the system. The processor then obtains input data from the circuit devices connected to these buses, executes predetermined processing, and controls and drives other devices, thereby realizing the execution of the predetermined processing of the system. There is.

0004

In a conventional system incorporating such a processor, when expanding or changing the system functions, it is necessary to change the design of the circuit, such as adding a new processor. There was also the problem of finding space on the board to mount a new processor.

On the other hand, DMAC is widely used in many computer systems, and there are many computer systems incorporating DMAC.

An object of the present invention is to make it possible to easily add a new processor using a widely used DMAC without redesigning the circuit of an existing system.

[0007]

[Means for Solving the Problems] The present invention
The present invention provides a processor that is compatible with C, and this processor has both the DMAC function and the original function of a processor to perform predetermined data processing. DMAC compatible means that it has the same pin arrangement as an existing DMAC, and this DMAC compatible processor can be connected in place of the existing DMAC.

The DMAC compatible processor according to the present invention, in response to a DMA transfer request from an external device, performs either inter-external DMA transfer or internal DMA transfer according to a predetermined operation mode for the external device. means for determining whether the DMA transfer is between storage means, and a first means for controlling data transfer between two required external devices including the external device that has made the above-mentioned DMA transfer request when it is determined that the DMA transfer is between external devices; When it is determined that DMA transfer is to be performed between the DMA transfer control means and the internal storage means of the external device, the above DM
a second DMA transfer control means for controlling data transfer between the external device that made the A transfer request and the internal storage means;
and processing means for performing predetermined processing on the input data stored in the internal storage means through DMA transfer by the second DMA transfer control means to create output data, and storing this output data in the internal storage means. We are prepared.

DMA between the external device and internal storage means
The second DMA transfer control means for controlling the transfer preferably includes a third control means for controlling the DMA transfer of input data from the external device to the internal storage means, and a third control means for controlling the DMA transfer of input data from the internal storage means to the external device. D of output data
and fourth control means for controlling MA transfer.

[0010] Preferably, the DMAC compatible processor causes the processing means to process the input data after the third control means completes the DMA transfer of the input data from the external device to the internal storage means. The apparatus further includes processing start control means for starting the process.

[0011] When the processing means requests the fourth control means to DMA transfer the output data to the external device after completing the processing of the input data, the data generated by the processing can be automatically transferred. becomes.

[0012] Alternatively, the DMAC compatible processor determines whether to permit the fourth control means to request DMA transfer of output data to the external device after the processing means has finished processing the input data. Further comprising means for determining.

[0013] In one embodiment of the present invention, the DMAC compatible processor further includes data temporary storage means, and the first DMA transfer control means controls the transfer source external device in DMA transfer between external devices. The data read from the data storage means is first temporarily stored in the data temporary storage means, and then the data stored in the data temporary storage means is controlled to be read and written to the transfer destination external device.

Preferably, the first DMA transfer control means controls the data read from the transfer source external device to be stored in the data temporary storage means and at the same time stored in the internal storage means.

[0015] In one embodiment of the present invention, the DMAC compatible processor is a DMAC compatible processor that performs fuzzy inference processing.
It is a MAC compatible fuzzy processor.

[0016] In this case, the processing means
The fuzzy inference means performs a predetermined fuzzy inference operation using the input data stored in the internal storage means through DMA transfer by the MA transfer control means, and stores the result in the internal storage means as output data.

The invention also provides a DMA transfer device. This DMA transfer device first stores data read from a temporary data storage means, an internal data storage means, and a transfer source device in the temporary data storage means, and then reads and transfers the data stored in the temporary data storage means. A first DMA transfer control means controls writing to the destination device, and data read from the transfer source device is first stored in the data temporary storage means and also stored in the internal data storage means, and then the data is stored in the internal data storage means. A second DMA transfer control means is provided for controlling the data stored in the temporary storage means to be read and written to the transfer destination device.

The DMA transfer device further includes processing means for performing predetermined processing on the data stored in the internal data storage means.

The DMA transfer device according to the present invention stores data read from a temporary data storage means, an input data storage means, and a transfer source device first in the temporary data storage means, and then stores it in the temporary data storage means. A first DMA transfer control means for controlling the reading of data and writing it to the transfer destination device, and a second DMA transfer control for controlling the data read from the transfer source device to be stored in the input data storage means. have the means.

The DMA transfer device further includes processing means for performing predetermined processing on the data stored in the input data storage means.

[0021] The DMA transfer device according to the present invention stores the data read from the temporary data storage means, the output data storage means, and the transfer source device first in the temporary data storage means, and then stores it in the temporary data storage means. A first DMA transfer control means for controlling the reading of data and writing to the transfer destination device, and a second DMA transfer control means for controlling the reading of data from the output data storage means and writing to the transfer destination device. It is equipped with

The DMA transfer device further includes processing means for writing data obtained through predetermined processing into the output data storage means.

The present invention further provides a processor with DMA functionality. This processor with a DMA function includes an input data storage means, a processing means for performing predetermined processing on the input data stored in the input data storage means,
A control terminal for input/output of control signals for DMA transfer, a data terminal connected to a data bus, an address terminal connected to an address bus, and a terminal connected to the control terminal, data terminal, and address terminal, and connected to the control terminal Taking in data via the data bus from the transfer source device designated by the address signal output to the address bus in response to the control signal input to the terminal, and writing this data into the input data storage means. The input data DMA transfer control means is provided to control the input data DMA transfer.

In one embodiment of the present invention, the processor with a DMA function further includes a temporary data storage means, and a device connected to the control terminal, the data terminal, and the address terminal, and specified by an address signal outputted to the address bus. The data is fetched from the transfer source device via the data bus, this data is stored in the temporary data storage means and the input data storage means, and then the data stored in the temporary data storage means is transferred to the above address.・
The device includes inter-device/input data DMA transfer control means for controlling transfer and writing via the data bus to a transfer destination device designated by an address signal output to the bus.

A processor with a DMA function according to the present invention includes an output data storage means, a processing means for storing output data obtained by predetermined processing in the output data storage means,
A control terminal for input/output of control signals for DMA transfer, a data terminal connected to a data bus, an address terminal connected to an address bus, and a terminal connected to the control terminal, data terminal, and address terminal, and connected to the control terminal In response to a control signal input to the terminal, the output data stored in the output data storage means is transferred via the data bus to a destination device designated by an address signal output to the address bus. It is provided with output data DMA transfer control means for controlling transfer and writing.

The processor with a DMA function is further connected to the control terminal, the data terminal, and the address terminal, and is specified by an address signal output to the address bus in response to a control signal input to the control terminal. The device includes inter-device DMA transfer control means for controlling data transfer from a transfer source device to a transfer destination device.

The processor with a DMA function according to the present invention includes a data temporary storage means, an input data storage means, a processing means for performing predetermined processing on the input data stored in the input data storage means, and a DMA transfer means. Control terminals for input/output of control signals, data terminals connected to the data bus, and address terminals connected to the address bus.
Also, data is connected to the control terminal, data terminal, and address terminal, and data is fetched from the transfer source device specified by the address signal output to the address bus via the data bus, and this data is temporarily stored in the data temporary storage. and the input data storage means, and then the data stored in the data temporary storage means,
An inter-device/input data DMA transfer control means is provided for controlling transfer and writing via the data bus to a transfer destination device designated by an address signal output to the address bus.

The present invention provides a computer system. This computer system has an address
It consists of a CPU, input/output devices including memory, and a DMAC processor interconnected by a bus, a data bus, and a control bus.

The DMAC processor has an internal storage means, in response to a DMA transfer request from the input/output device, and with bus occupancy permission from the CPU, stores two required input/output devices including the input/output device that made the DMA transfer request. A first DM that controls data transfer between input and output devices
A transfer control means, in response to a DMA transfer request from the input/output device, transfers data between the input/output device that made the DMA transfer request and the internal storage means with bus occupancy permission from the CPU. A second DMA transfer control means to control and input data stored in the internal storage means through DMA transfer by the second DMA transfer control means are subjected to predetermined processing to create output data, and this output data is A processing means for storing data in the internal storage means is provided.

The DMAC compatible processor according to the present invention includes a processing means that performs predetermined processing on input data to generate output data, takes in the input data from an external device by DMA transfer, and processes the output data. The device includes a first DMA transfer means for outputting data to an external device by DMA transfer, and a second DMA transfer means for performing DMA transfer of data between two external devices.

In one embodiment of the present invention, the processing means is a fuzzy inference processing means, and includes a first storage means for storing data representing rules and membership functions, and a second storage means for storing the input and output data. storage means, and calculation means for performing fuzzy inference calculation processing using the input data stored in the second storage means according to the rules and membership functions stored in the first storage means. There is.

The processing means and the first and second DMA transfer means are preferably formed on one chip.

The DMAC compatible processor has a pin arrangement compatible with existing DMACs.

[0034] This invention further provides a DMAC compatible
Provides instructions on how the processor operates.

[0035] In this operating method, in response to a DMA transfer request from an input/output device, the DMA transfer is performed between the input/output devices or within the input/output device, depending on the predetermined operation mode for the input/output device. Decide whether to perform DMA transfer between storage means, and perform DM between input and output devices.
When A transfer is determined, data is transferred by DMA between two required input/output devices including the input/output device that made the above DMA transfer request, and when it is determined to be DMA transfer between internal storage means of input/output devices, the above DMA transfer is performed. It performs DMA transfer of data between the input/output device that has requested the transfer and the internal storage means.

Preferably, the DMA transfer between the internal storage means of the input/output device includes DMA transfer of input data from the input/output device to the internal storage means and output data from the internal storage means to the input/output device. D
This includes MA transfer.

In one embodiment of the present invention, DMA of input data from the input/output device to the internal storage means is provided.
After the transfer is completed, the processing means is caused to start processing this input data.

In another embodiment, when the processing means finishes processing the input data, it requests DMA transfer of the output data to the input/output device.

[0039] In yet another embodiment, when the processing means finishes processing the input data, it is allowed to request DMA transfer of output data to the input/output device according to a predetermined operating mode. Decide whether or not.

In still another embodiment of the present invention, in DMA transfer between input/output devices, data read from the source input/output device is first temporarily stored in the data temporary storage means, and then the data is temporarily stored in the data temporary storage means. control to read the data stored in the transfer destination input/output device and write it to the transfer destination input/output device.

By controlling the data read from the transfer source input/output device to be stored in the data temporary storage means and simultaneously stored in the internal storage means, the input of input data to the DMAC compatible processor is performed as inter-device DMA transfer. Can be done at the same time.

[0042] When there is a DMA transfer request from the input/output device, the DM between the input/output device internal storage means is
When the A transfer is determined, it is preferable that the processing means determines whether or not the processing operation is being executed, and if the processing operation is in progress, it is preferable to wait for the completion of the processing operation before performing the DMA transfer.

[0043] The processing means is, for example, a fuzzy inference processing means.

The present invention further provides a DMA transfer method. This DMA transfer method includes data temporary storage means,
In an apparatus comprising an internal data storage means and a processing means for performing predetermined processing on the data stored in the internal data storage means, the data read from the transfer source device is first stored in the data temporary storage means, and the data is stored in the data storage means. The data is stored in the internal data storage means, and then the data stored in the temporary data storage means is read and written to the transfer destination device.

[0045]

[Operation] In addition to normal DMA transfer between input/output devices, this invention also allows input data to be taken into the processor and output data to be sent from the processor.
This is done by MA transfer. Further, the processor performs predetermined processing on the input data that has been taken in to generate output data.

Furthermore, input data is taken into the processor at the same time as the DMA transfer between input and output devices.

[0047] The processor according to the present invention uses the existing D
It can have exactly the same pin arrangement as the MAC. In other words, it can be configured to be pin compatible with DMAC.

[0048]

[Effects of the Invention] The processor according to the present invention
It can have exactly the same size, number of pins, and pin arrangement as AC. Therefore, it is possible to install the processor according to the present invention into a DMAC socket on the circuit board of an existing system. This makes it possible to expand and add functionality to the system by simply replacing devices and, if necessary, adding or changing some software for the CPU, without changing the design of existing circuits. C
The PU can handle the processor according to the present invention in the same way as an existing DMAC.

Furthermore, since the input data is taken into the processor at the same time as the DMA transfer between input/output devices, high-speed data transfer can be realized.

[0050]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an overview of the overall configuration of a computer system.

[0051] A computer system has a CPU (host CPU or MPU: MPU = microprocessor).
10. Multiple input/output devices (hereinafter simply referred to as I/O)
11, 12, one or more memories 13, and DM
It consists of an AC compatible fuzzy processor (hereinafter simply referred to as DMAC fuzzy processor) 20. Two I/Os, I/O1 and I/O2, are shown. Only one memory 13 is shown.

The DMAC fuzzy processor is a well-known DMAC fuzzy processor.
It has exactly the same size, number of pins, and pin arrangement as a MAC. Therefore, the DMAC fuzzy processor is a DMAC that is built into existing computer systems.
It can be replaced with That is, it is possible to use the DMAC in an existing computer system by removing it from its socket and inserting this DMAC fuzzy processor into the socket. The DMAC fuzzy processor is connected to the CPU, I/O, and memory just like existing DMACs.

As detailed later, the DMAC fuzzy
The processor 20 has exactly the same functions as an existing DMAC, a function to perform fuzzy inference calculation processing, and DMA transfer of input data for fuzzy inference and output data obtained by fuzzy inference to/from I/O or memory. It has a function.

DMAC fuzzy processor 20 can be made pin compatible with any DMAC. HD68450 as an example of existing DMAC
The pin arrangement of is shown in FIG.

This DMAC has many control signal terminals, address signal terminals, and data signal terminals. Since these signal terminals are known, no special explanation is required, but the basic terminals required for DMA transfer processing will be briefly described.

[0056] This DMAC has four channels. That is, DMA transfer is possible between four pairs of I/O and memory.

Generally, the inversion of a signal is indicated by adding a bar above the symbol indicating the signal, but in this specification, the inversion of the signal is indicated by adding an * in front of the symbol.

Terminals *REQ0 to *REQ3 are input terminals for DMA transfer requests from I/O for each channel.

Terminals *ACK0 to *ACK3 are output terminals for a signal indicating that the DMA transfer request has been accepted for the I/O that made the transfer request.

Terminal *BR is an output terminal for a signal indicating that this DMAC requests bus occupancy from the CPU.

[0061] The terminal *BG is used by the CPU to take possession of the bus.
This is an input terminal for a signal indicating that it is to be applied to the MAC.

The terminal *DTC is an output terminal for a signal that notifies the I/O that the DMA transfer has completed normally.

The terminal *DTACK is mainly an output terminal for a signal that notifies the CPU that the DMA transfer has ended normally.

In addition, R/*W is an output terminal for a read/write signal, and *CS is an input terminal for a chip select signal of this DMAC. Power supply terminal VCC, ground terminal VSS
are also arranged mixed with control signal terminals and address or data signal terminals.

This DMAC has a single addressing mode and a dual addressing mode, the details of which will be described later. Terminals A8/D0 to A23/D15, which are commonly used for address signals and data signals, are used as address terminals in the single addressing mode, and as address terminals or data terminals in a time-divisionally switched manner in the dual addressing mode.

FIG. 3 shows the DMAC fuzzy processor 20
This shows an overview of the configuration.

The DMAC fuzzy processor basically consists of a DMAC control section 21 and a fuzzy inference section 31. In addition, necessary registers, counters, etc. are specifically extracted and shown in FIG. 3 for the convenience of explanation.

The DMAC control section 21 is accompanied by a data temporary storage buffer 22, a transfer word counter 23, and a register group 24 provided for each channel. The register group 24 of each channel includes a transfer source address register,
Contains the transfer destination address register, transfer word count register, operation mode register, etc.

The fuzzy inference section 31 is accompanied by an input data register (input register) and an output data register (output register) (collectively referred to as fuzzy input/output registers) 32. The fuzzy inference unit 31 includes a memory for storing data representing rules and membership functions for fuzzy inference, and a fuzzy inference function and fuzzy input/output register 3 according to the rules.
It is comprised of an arithmetic section that executes fuzzy inference operations using the input data of the input register No. 2, and a control section that controls read/write of data from the memory, operations of the arithmetic section, etc. Output data representing the fuzzy inference operation result is stored in the output register of the fuzzy input/output register 32. Data representing rules and membership functions may be written in advance in PROM etc.
The data may be written into the memory of the fuzzy inference unit 31 by DMA transfer.

From the DMAC control unit 21 to the fuzzy inference unit 3
1 is given a fuzzy inference start signal. A signal indicating that fuzzy inference is in progress (busy signal) and an automatic output request signal requesting output data representing the fuzzy inference result by DMA transfer are given from the fuzzy inference unit 31 to the DMAC control unit 21. .

As mentioned above, this DMAC fuzzy processor 20 has an address bus, a control bus,
and data bus for I/O11, 12, memory 1
3. Connected to the CPU 10, etc. In FIG. 3, the DMA transfer request signal is particularly extracted and shown as *REQ. Needless to say, these buses are connected to corresponding terminals as shown in FIG.

The internal parts of the DMAC fuzzy processor 20 are also interconnected by data buses and various control signals, as shown in FIG. In particular, the data temporary storage buffer 22 and the fuzzy input/output register 32 are connected to the outside through a data bus.

FIGS. 4A and 4B show examples of the transfer word count register and operation mode register. These registers are included in the register group 24 for each channel, as described above.

In FIG. 4A, the number of words (number of bytes) to be transferred by DMA transfer is stored in advance in the transfer word number register.

In FIG. 4B, the lower three bits B0 to B2 of the operation mode register represent the operation mode.

B1B0=00 is a normal DMA transfer, ie from I/O to memory or vice versa,
Represents the operation mode of DMA transfer of data from /O to I/O (DMA transfer mode).

B1B0=01 is an operation mode in which normal DMA transfer of data from I/O to memory, etc. is performed, and the transferred data is simultaneously DMA transferred to the input register of the fuzzy input/output register 32 as input data. (DMA transfer + fuzzy input mode).

B1B0=10 represents an operation mode in which input data is DMA transferred from I/O or memory to the input register of the fuzzy input/output register 32 (fuzzy input mode).

B1B0=11 represents an operation mode in which output data representing the inference result from the output register of the fuzzy input/output register 32 is transferred by DMA to I/O or memory (fuzzy output mode).

Immediately after the fuzzy inference operation is completed, B2 sends the output data obtained by the fuzzy inference operation to D.
This indicates whether or not to proceed to the operation of outputting by MA transfer (this is called automatic output activation). B2=0 indicates that automatic output is not activated, and B2=1 indicates that automatic output is activated.

Such an operating mode is determined by the user of this computer system, and data B0-B2 representing the operating mode is written in advance to the operating mode register for each channel.

[0082] In Figure 1, as *REQ1 and *REQ2,
As shown by specifically extracting only the DMA transfer request signal line, each I/O is assigned a channel in advance. The operating mode is determined for each channel.

FIG. 5 shows the DMAC fuzzy processor 20
The overall processing procedure of the DMAC control unit 21 in FIG. This processing can of course be realized by a processor or CPU operating according to a logic circuit, microcode, like a normal DMAC.

[0084] While waiting (step 101)
, DMA transfer request signal *REQi from any I/O
is input (step 102), the operation mode register in the register group 24 of channel i assigned to that I/O is selected, and the operation mode data of the operation mode data stored in the operation mode register is selected. The lower 2 bits B1B0 are taken in, and this data B1B0 becomes the 4 mentioned above.
It is determined which of the types of operation modes is specified (step 103).

If the DMA transfer mode is specified (B1B0=00), a normal DMA transfer operation is performed according to the procedure shown in FIG. 6, which will be described later.
).

When the DMA transfer + fuzzy input mode is specified (B1B0=01), it is checked whether the fuzzy inference unit 31 is executing fuzzy inference (
Step 105). As will be understood from what will be described later, the fuzzy inference section 31 outputs a fuzzy inference in progress signal while fuzzy inference is being executed. This fuzzy inference signal is DM
Since the fuzzy inference signal is given to the AC control unit 21, the DMAC control unit 21 can determine whether the fuzzy inference unit 31 is executing fuzzy inference based on this fuzzy inference in progress signal. If the fuzzy inference section 31 is executing fuzzy inference, the DMAC control section 21 will wait until the fuzzy inference is completed.

[0087] If the fuzzy inference unit 31 is not in the process of fuzzy inference, or if the fuzzy inference processing is completed, the DMA transfer shown in FIG. 7, which will be described later, is performed (step 106).
). Since the input data is stored in the input register in the fuzzy input/output register 32 by this DMA transfer, a fuzzy inference start signal is sent from the DMAC control unit 21 in order to cause the fuzzy inference unit 31 to start fuzzy inference processing shown in FIG. 10, which will be described later. is outputted and given to the fuzzy inference section 31 (step 107).

When the fuzzy input mode is specified (B1B0=10), the fuzzy inference unit 3
1 is currently executing fuzzy inference (step 108). Then, if the fuzzy inference unit 31 is not executing fuzzy inference or if fuzzy inference is completed, D
Data is transferred from the I/O that issued the MA transfer request to an input register in the fuzzy input/output register 32 and stored (step 109). Thereafter, fuzzy inference is started in the fuzzy inference section 31 using this input data (step 110).

When the fuzzy output mode is specified (B1B0=11), the fuzzy inference unit 3
1 is currently executing fuzzy inference (step 111). If the fuzzy inference unit 31 is not executing fuzzy inference or if the fuzzy inference is completed, the output data obtained by this fuzzy inference and stored in the output register in the fuzzy input/output register 32 is shown in FIG. 9, which will be described later. By DMA transfer, the data is transferred to the I/O that issued the DMA transfer request.

[0090] In the DMAC control section 21, the above-described operation is repeatedly performed.

FIG. 6 shows the procedure of the DMA transfer process shown in step 104 in FIG. 5 by the DMAC control unit 21.

In response to the DMA transfer request *REQi, processing for occupying the bus is performed (step 121). As is well known, first a bus occupancy request signal *BR is output to the CPU 10, and in response, when a bus occupancy permission signal *BG is given from the CPU 10, the I/O that made the DMA transfer request This is done by outputting a DMA transfer request permission signal *ACKi to the DMA transfer request.

Next, the transfer word count register in the register group 24 of channel i assigned to the I/O that made the DMA transfer request is selected, and the data representing the transfer word count set in advance in that register is read out. , is set in the transfer word counter 23 (step 122).

[0094] DMA transfer is performed by the transfer source I/O for each channel.
A pair of an I/O or memory (these are referred to as a transfer source device) and a transfer destination I/O or memory (these are referred to as a transfer destination device) is determined in advance. Further, the addresses to which the data of the transfer source device and the transfer destination device are to be transferred are determined in advance and set in the register group 24 of the channel i.

First, one word (one byte) of data is transferred from the transfer source device to the data temporary storage buffer 22 (step 123). Specifically, this is D
The MAC control unit 21 outputs an address signal indicating the address of the transfer source device. A chip select signal designating the transfer source device is generated from this address signal by a decoder (not shown) provided in the computer system, and is applied to the transfer source device. Further, a read signal R is output from the DMAC control section 21. This reads one word of data from the addressed storage location of the source device and outputs it onto the data bus. Since the write signal *W is applied to the data temporary storage buffer 22, the data output on the data bus is written to the buffer 22 and temporarily stored.

Next, one word of data temporarily stored in the data temporary storage buffer is transferred to the destination device (step 124). Specifically, this is done as follows. The DMAC control unit 21 outputs an address signal indicating the address of the transfer destination device. A chip select signal is generated by decoding this address signal and is applied to the transfer destination device. A write signal *W is applied from the DMAC control unit 21 to the transfer destination device, and a read signal R is applied to the data temporary storage buffer 22. This causes the data in buffer 22 to be read and written to the addressed memory location of the destination device via the data bus.

When the above operations are completed, the contents of the transfer word counter 23 are decremented.

The above operations are performed one word at a time while updating the addresses of the transfer source device and transfer destination device.

When the DMA transfer of the data of the preset number of words is completed, a count end signal is output from the transfer word number counter 23 and given to the DMAC control unit 21 (step 125).

Thereafter, the CMAC control unit 21 performs a bus release procedure (step 126). This is executed by outputting a normal end signal *DTC to the device and a normal end signal *DTACK to the CPU 10.

The above-described DMA transfer operation is an operation in the dual addressing mode, which is performed when the address range assigned to the transfer source device and the address range assigned to the transfer destination device are different. If the address ranges of the transfer source and destination devices match, a single addressing mode operation is performed in which data is directly sent from the transfer source device to the transfer destination device without going through a data temporary storage buffer.

FIG. 7 shows the DMA transfer processing procedure of the DMA transfer+fuzzy input mode shown in step 106 of FIG. 5 by the DMAC control section 21.

[0103] Bus occupancy procedure by DMAC control unit 21,
The process of setting the number of transfer words in the transfer word number register is the same as steps 121 and 122 in FIG. 6 (steps 131 and 132).

One word of data is read from the transfer source device and written to the data temporary storage buffer 22 and the input register in the fuzzy input/output register 32 (step 133). A write signal *W is applied from the DMAC control unit 21 to the data temporary storage buffer 22 and the input register. The address of the input register is specified by the DMAC control unit 21.

There are several ways to address input registers. One of them is to use the input register as an F1F0 (first-in, first-out) register. In this case, addressing can be done by incrementing the address one by one. The other is to predetermine the address range of the input register (set in a register in the register group 24), and according to this address range, the DMAC control unit 21 performs the same addressing for the transfer destination and source device. address.

In any case, since both the data temporary storage buffer 22 and the fuzzy input/output register 32 are connected to the data bus, the data read from the transfer source device is stored in these buffers 22 and input registers. Ru.

Subsequently, the data temporarily held in the data temporary storage buffer 22 is transferred to the destination device and written (step 134). This is Figure 6 Step 1
This is the same process as No. 24.

The above operation is repeated for each word of data transfer, and when a count end signal is output from the transferred word counter 23 (step 135), the bus occupation release procedure is performed and the DMA transfer is completed (step 135). 136).

[0109] This DMA transfer + fuzzy input mode is
When transferring data from I/O to memory, this same data is used as input data for fuzzy inference in DM.
It is very convenient because it is input to the AC fuzzy processor 20. The data written to the memory is used by the CPU 10 for processing other than fuzzy inference, for example.

FIG. 8 shows the DMA transfer processing procedure in the fuzzy input mode shown in step 109 of FIG. 5 by the DMAC control section 21.

Compared with the process shown in FIG. 7, data is transferred only from the transfer source device to the input register in the fuzzy input/output buffer 32, and data is not transferred to the temporary storage buffer 22 (step 143). )
. This can be realized by applying the write signal *W only to the input register and not applying the write signal *W to the temporary storage buffer 22. Furthermore, there is no processing equivalent to step 134 in FIG. Other processing steps 141, 142, 145, 146
are steps 131, 132, 135, 13 in FIG.
Same as 6.

In this mode, input data used for fuzzy inference is given to the input register in the DMAC fuzzy processor 20 by direct DMA transfer from the transfer destination device. Moreover, the flow in Figure 6 or Figure 7
As can be seen by comparing with the chart, data is transferred directly from the transfer source device to the input register without going through the data temporary storage buffer 22, so the data transfer speed is fast (in contrast to the dual addressing mode described above). It has the advantage of being twice as fast as the standard computer.

FIG. 9 shows the DMAC transfer processing procedure in the fuzzy output mode shown in step 112 of FIG. 5 by the DMAC control section 21.

The difference from the process in step 143 shown in FIG. 8 is that in step 153 in FIG. data) is transferred word by word to the destination device. The read signal R is output to the output register.
A write signal *W is given to the transfer destination device. The addressing of the output register is F1F0 as described above.
Alternatively, the DMAC control unit 21 may provide the address signal to the output register. In this case, the DMA transfer request will generally be made by the transfer destination device. A channel related to a pair of a transfer destination device and an output register is determined in advance, and data necessary for DMA transfer (address data, number of transferred words, operation mode, etc.) is set in advance in the register group 24 of that channel. Other processing steps 151 , 152 , 155 , 156
are steps 141, 142, 145, 146 in FIG.
is the same as

FIG. 10 mainly shows the processing procedure of the control section in the fuzzy inference section 31. This control section is also realized by a processor or CPU that operates according to a combination of logic circuits and microcode.

When the fuzzy inference start signal is given from the DMAC control unit 21 (steps 107 and 11 in FIG. 5),
0), the fuzzy inference flag is set (step 161). As a result, a fuzzy inference signal is output.

[0117] Next, the rules stored in advance in the memory in the fuzzy inference section 31 are read out one by one, and
Membership functions related to this rule are read from the same memory, and input data is read from an input register in the fuzzy input/output register 32, respectively, and processed according to the rule. The fuzzy inference operation is the well-known MIN
- Follows MAX operation and other methods. The fuzzy inference calculation results are defuzzified by the center of gravity method, maximum height method, etc. as necessary, and stored in the output register in the fuzzy input/output register 32 as output data (step 162
).

The third bit B2 in the operation mode register of the channel related to the device that made the DMA transfer request in step 102 of FIG. 5 is referenced (step 163). If B2=0, the fuzzy inference flag is reset (step 166). This stops the fuzzy inference signal. If B2=1, an automatic output request signal is output and given to the DMAC control unit 21 (step 165). Also, the fuzzy inference flag is reset (step 166). In response to this automatic output request signal, the DMAC control unit 21 transfers the data representing the fuzzy inference result stored in the output register to the above device by DMA transfer according to the flow chart shown in FIG.

If necessary, a channel is also allocated to the fuzzy inference unit 31, and D of the fuzzy inference result is
MA transfer may also be performed.

In the above embodiment, a DMAC fuzzy processor is shown as a processor compatible with DMAC, but the type of processor is not limited to fuzzy processors, and DMAC can be used with processors that perform specific arithmetic processing other than fuzzy processing. The combined DMAC processor may be compatible with DMAC.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the entire computer system.

FIG. 2 is a plan view showing an example of a pin arrangement of a DMAC.

FIG. 3 is a block diagram showing the configuration of a DMAC fuzzy processor.

FIG. 4 (A) shows the transfer word count register, and (B) shows the operation mode register.

[Fig. 5] Flowchart showing the overall operation of the DMAC control unit.
It is a chart.

FIG. 6 is a flow chart showing a normal DMA transfer operation in a DMAC control unit.

FIG. 7 is a flow chart showing the operation of the DMA transfer+fuzzy input mode in the DMAC control unit.

FIG. 8 is a flow chart showing the operation of the fuzzy input mode in the DMAC control unit.

FIG. 9 is a flow chart showing the operation of the fuzzy output mode in the DMAC control unit.

[Fig. 10] Flowchart showing the operation in the fuzzy inference section.
It is a chart.

[Explanation of symbols]

10 CPU 11, 12 Input/output device (I/O) 13 Memory 20 DMAC compatible fuzzy processor (DMAC fuzzy processor) 21 DMAC control section 22 Data temporary storage buffer 23 Transfer word counter 24 Register group 31 Fuzzy inference section 32 Fuzzy input/output register

Claims (40)

[Claims] [Claim 1] In response to a DMA transfer request from an external device, a DMA transfer between external devices is performed according to a predetermined operation mode for the external device.
means for determining whether to transfer or DMA transfer between internal storage means of an external device, and when it is determined to be DMA transfer between external devices, transfer data between two required external devices including the external device that made the above DMA transfer request; a first DMA transfer control means for controlling the DMA transfer, and a second DMA transfer control means for controlling the data transfer between the external device that made the DMA transfer request and the internal storage means when it is determined that the DMA transfer is to be performed between the external device and the internal storage means. DMA transfer control means by the DMA transfer control means and the second DMA transfer control means
A processing means for performing predetermined processing on the input data stored in the internal storage means by transfer to create output data, and storing this output data in the internal storage means.
MAC compatible processor. Claim 2: D between the external device and internal storage means.
A second DMA transfer control means for controlling MA transfer, a third control means for controlling DMA transfer of input data from the external device to the internal storage means, and an output from the internal storage means to the external device. Claim 1 comprising: fourth control means for controlling DMA transfer of data.
DMAC compatible processor described in. 3. DMA of input data from the external device to the internal storage means by the third control means;
3. The DMAC compatible processor according to claim 2, further comprising processing start control means for causing said processing means to start processing said input data after the transfer is completed. 4. The DMAC compatible processor according to claim 2, wherein said processing means requests said fourth control means to perform DMA transfer of output data to said external device after completing processing of input data. 5. Further comprising means for determining whether to allow the fourth control means to request DMA transfer of output data to the external device after the processing means finishes processing the input data. 3. The DMAC compatible processor according to claim 2. 6. Further comprising data temporary storage means, wherein the first DMA transfer control means is configured to transfer data between external devices.
In MA transfer, data read from the transfer source external device is first temporarily stored in the data temporary storage means,
2. The DMAC compatible processor according to claim 1, further controlling the data stored in said data temporary storage means to be read and written to a transfer destination external device. 7. The DMAC according to claim 6, wherein the first DMA transfer control means controls the data read from the transfer source external device to be stored in the data temporary storage means and at the same time stored in the internal storage means. Compatible processor. 8. Data read from the data temporary storage means, internal data storage means, and transfer source device is first stored in the data temporary storage means, and then the data stored in the data temporary storage means is read and transferred to the transfer destination. A first DMA transfer control means for controlling writing to the device, and data read from the transfer source device are first stored in the data temporary storage means and also in the internal data storage means, and then the data is temporarily stored in the internal data storage means. A DMA transfer device comprising: second DMA transfer control means for controlling reading data stored in a storage means and writing it to a transfer destination device. 9. The DMA transfer device according to claim 8, further comprising processing means for performing predetermined processing on the data stored in the internal data storage means. 10. Data read from the data temporary storage means, input data storage means, and transfer source device is first stored in the data temporary storage means, and then the data stored in the data temporary storage means is read and transferred to the transfer destination. A first DMA transfer control means that controls writing to the device, and a second DMA transfer control means that controls the data read from the transfer source device to be stored in the input data storage means.
A DMA transfer device equipped with a transfer control means. 11. The DMA transfer device according to claim 10, further comprising processing means for performing predetermined processing on the data stored in the input data storage means. 12. Data read from the data temporary storage means, output data storage means, and transfer source device is first stored in the data temporary storage means, and then the data stored in the data temporary storage means is read and transferred to the transfer destination. DMA transfer comprising a first DMA transfer control means for controlling writing to a device, and a second DMA transfer control means for controlling reading data from the output data storage means and writing to a transfer destination device. Device. 13. The DMA transfer device according to claim 12, further comprising processing means for writing data obtained through predetermined processing into said output data storage means. 14. Input data storage means, processing means for performing predetermined processing on the input data stored in the input data storage means, a control terminal for inputting and outputting control signals for DMA transfer, and a data bus. and an address terminal connected to the data terminal and the address bus, as well as the control terminal, the data terminal and the address terminal, and output to the address bus in response to a control signal input to the control terminal. DMA function equipped with an input data DMA transfer control means for controlling to take in data from the transfer source device specified by the address signal via the data bus and write this data to the input data storage means. processor. Claim 15: Further comprising data temporary storage means,
The data temporary storage means takes in data via the data bus from the transfer source device connected to the control terminal, data terminal, and address terminal and specified by the address signal output to the address bus, and stores this data in the data temporary storage means. and stored in the input data storage means, and then transfers the data stored in the data temporary storage means to the destination device specified by the address signal output to the address bus via the data bus. 15. The processor with DMA function according to claim 14, further comprising device-to-device and input data DMA transfer control means for controlling writing. 16. Output data storage means, processing means for storing output data obtained by predetermined processing in the output data storage means, a control terminal for input/output of control signals for DMA transfer, and a control terminal connected to a data bus. and an address terminal connected to a data terminal and an address bus, and the control terminal, the data terminal and the address terminal, and the output data is stored in the output data storage means in response to a control signal input to the control terminal. output data DMA transfer control means for controlling the output data to be transferred and written to the transfer destination device specified by the address signal output to the address bus via the data bus; With processor. 17. Transfer from a transfer source device specified by an address signal connected to the control terminal, data terminal, and address terminal and output to the address bus in response to a control signal input to the control terminal. 17. The processor with DMA function according to claim 14, further comprising inter-device DMA transfer control means for controlling data transfer to a destination device. 18. Data temporary storage means, input data storage means, processing means for performing predetermined processing on the input data stored in the input data storage means, input/output control of control signals for DMA transfer. terminals, data terminals connected to the data bus, address terminals connected to the address bus, and specified by address signals connected to the control terminals, data terminals, and address terminals and output to the address bus. Data is fetched from the transfer source device via the data bus, this data is stored in the temporary data storage means and the input data storage means, and then the data stored in the temporary data storage means is transferred to the address and the input data storage means. A processor with a DMA function, comprising inter-device and input data DMA transfer control means for controlling transfer and writing to a transfer destination device specified by an address signal output to the bus via the data bus. 19. CPUs interconnected by an address bus, a data bus, and a control bus;
It is composed of an input/output device including a memory, and a DMAC processor, and the DMAC processor transfers the DMA to an internal storage means, in response to a DMA transfer request from the input/output device, and with bus occupancy permission from the CPU.
A first controller that controls data transfer between two required input/output devices including the input/output device that requested the transfer.
DMA transfer control means, D from the above input/output device
a second D that controls data transfer between the input/output device that made the DMA transfer request and the internal storage means under bus occupancy permission of the CPU in response to the MA transfer request;
Performing predetermined processing on the input data stored in the internal storage means through DMA transfer by the MA transfer control means and the second DMA transfer control means to create output data, and store this output data in the internal storage means. A computer system that has processing means for storing information. 20. Processing means that performs predetermined processing on given input data to generate output data, takes in the input data from an external device by DMA transfer, and outputs the output data to the external device by DMA transfer. A DMAC compatible processor comprising: a first DMA transfer means for performing DMA transfer of data between two external devices; and a second DMA transfer means for performing DMA transfer of data between two external devices. 21. The processing means is a fuzzy inference processing means, and includes a first storage means for storing data representing rules and membership functions, and a second storage means for storing the input and output data. 20. Calculating means for performing fuzzy inference calculation processing using the input data stored in the second storing means according to the rules and membership functions stored in the first storing means. DMAC compatible processor described in. 22. The processing means, first and second D
Claim 20, wherein the MA transfer means is formed on one chip.
DMAC compatible processor described in. 23. The DMAC compatible processor according to claim 20, having a pin arrangement compatible with DMAC. 24. In response to a DMA transfer request from an external device, DM between external devices is performed according to a predetermined operation mode for the external device.
Means for determining whether to transfer A or DMA transfer between external device internal storage means, and when it is determined to be DMA transfer between external devices, data transfer between two required external devices including the external device that made the above DMA transfer request. a first DMA transfer control means for controlling the transfer; and a first DMA transfer control means for controlling the data transfer between the external device that requested the DMA transfer and the internal storage means when it is determined that the DMA transfer is to be performed between the external device and the internal storage means. 2 DMA transfer control means and DM by the second DMA transfer control means
A DMAC compatible fuzzy processor, comprising fuzzy inference means for performing a predetermined fuzzy inference operation using the input data stored in the internal storage means by A transfer, and storing the result in the internal storage means as output data. . 25. A second DMA transfer control means for controlling DMA transfer between the external device and internal storage means is a third control means for controlling DMA transfer of input data from the external device to the internal storage means. , DMA of output data from the internal storage means to the external device.
25. The DMAC compatible fuzzy processor according to claim 24, further comprising fourth control means for controlling transfer. 26. DM of input data from the external device to the internal storage means by the third control means;
26. The DMA according to claim 25, further comprising processing start control means for causing the fuzzy inference means to start fuzzy inference calculation processing of the input data after the A transfer is completed.
C compatible fuzzy processor. 27. The DMAC compatible fuzzy inference method according to claim 25, wherein the fuzzy inference means requests the fourth control means to DMA transfer the output data to the external device after completing the processing of the input data. processor. 28. Means for determining whether or not to permit the fourth control means to request DMA transfer of output data to the external device after the fuzzy inference means finishes fuzzy inference calculation processing of input data. 26. The DMAC compatible computer according to claim 25, further comprising:
Fuzzy processor. Claim 29: Further comprising data temporary storage means,
In DMA transfer between external devices, the first DMA transfer control means first temporarily stores data read from the transfer source external device in the data temporary storage means, and then stores the data stored in the data temporary storage means. 25. The DMAC-compatible fuzzy processor according to claim 24, wherein the DMAC-compatible fuzzy processor controls reading of and writing to a destination external device. 30. The first DMA transfer control means comprises:
30. The DMAC compatible fuzzy processor according to claim 29, wherein the DMAC compatible fuzzy processor controls the data read from the transfer source external device to be stored in the internal storage means at the same time as the data is stored in the data temporary storage means. 31. In response to a DMA transfer request from an input/output device, the DMA transfer is performed between input/output devices or between internal storage means of the input/output device, depending on the operation mode predetermined for the input/output device. DM
A transfer is determined, and when it is determined to be a DMA transfer between input/output devices, a DMA transfer of data is performed between two required input/output devices including the input/output device that made the above DMA transfer request, and the data is transferred to the internal memory of the input/output device. An operating method of a DMAC compatible processor, which performs a DMA transfer of data between an input/output device that has requested the DMA transfer and an internal storage means when it is determined that inter-means DMA transfer is to be performed. 32. The DMA transfer between the internal storage means of the input/output device includes DMA transfer of input data from the input/output device to the internal storage means, and DMA transfer of output data from the internal storage means to the input/output device. 32. The method of operating a DMAC compatible processor according to claim 31, comprising: transferring. 33. After the DMA transfer of input data from the input/output device to the internal storage means is completed,
Claim 3: The processing means starts processing the input data.
2. A method of operating the DMAC compatible processor according to item 2. 34. When the processing means finishes processing the input data, DM the output data to the input/output device.
33. The method of operating a DMAC compatible processor according to claim 32, requesting an A transfer. [Claim 35] A claim for determining whether to allow a request for DMA transfer of output data to the input/output device according to a predetermined operation mode when the processing means finishes processing the input data. 33. A method of operating a DMAC compatible processor according to item 32. 36. In DMA transfer between input/output devices, the data read from the transfer source input/output device is first temporarily stored in a data temporary storage means, and then the data stored in the data temporary storage means is read and transferred. 32. The method of operating a DMAC compatible processor of claim 31, controlling to write to a first input/output device. 37. The method of operating a DMAC compatible processor according to claim 36, wherein the data read from the transfer source input/output device is controlled to be stored in the internal storage means at the same time as the data is stored in the data temporary storage means. 38. When there is a DMA transfer request from the input/output device and it is determined that the DMA transfer is to be performed between the internal storage means of the input/output device, the processing means determines whether or not the processing operation is being executed; If so, the DMA transfer is performed after waiting for the completion of the DMA transfer according to claim 31.
How a MAC compatible processor operates. 39. The method of operating a DMAC compatible processor according to claim 38, wherein said processing means is a fuzzy inference processing means. 40. In an apparatus comprising temporary data storage means, internal data storage means, and processing means for performing predetermined processing on the data stored in the internal data storage means, the data read from the transfer source device is first read out from the transfer source device. storing the data in the temporary data storage means and storing it in the internal data storage means, and then reading out the data stored in the temporary data storage means and writing it to the transfer destination device;
DMA transfer method.