JPH04306085A - Picture information processor - Google Patents

Abstract

PURPOSE:To reduce the processing time by devising the processor such that the arithmetic processing is implemented in parallel for each picture element in the picture information processing implementing edge detection. CONSTITUTION:Sets of pnpn optical switches 1 are arranged in 2-dimension and two independent connection terminals are provided, from which a drive voltage is applied to the pnpn optical switch group and one of the terminals connects to a 1st power supply via a resistor 2 to each optical switch. The other terminal connects to a tunnel diode 3 connecting in parallel with two adjacent optical switches and the tunnel diode is connected to a 2nd power supply.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image information processing apparatus for detecting edges of image information.

0002

2. Description of the Related Art FIG. 11 is a configuration diagram showing a conventional image processing device for detecting edges of image information, as shown in "Digital Image Processing", authored by Masao Saito, published by Tokai University Press, page 65. , 6 is an input image, 30 is a CCD image sensor, 31 is a computer, 32 is an output device, and 7 is an output image.

Next, the operation will be explained. The input image information (input light) 6 is received by the CCD image sensor 30 . The information possessed by each pixel output from the CCD image sensor 30 is f(i, j) (where M and N are the numbers of pixels in both the vertical and horizontal directions of the input image information, 1≦i≦M, 1≦i
≦N. ). f(i,j) is input to the computer 31 as one-dimensional time series information, and the following calculation is performed on all of this pixel information f(i,j). ∇f=(f(i+1,j)−f(i,j),f(i,j
+1)-f(i,j)) |∇f|≧T then g(
i, j)=1 |∇f|<T then g(i, j)=
0 Here, T is a threshold value, and g(i,j) is image information after performing edge detection. This image information g(i,
j) is outputted to an output device 7 such as a monitor as image information (output light) 7 consisting of edges of the input image.

0004

[Problems to be Solved by the Invention] Since the conventional image information processing device is configured as described above, calculations for each pixel are sequentially processed in time series, and as the number of pixels of an input image increases, the computer Since the processing time also increases in proportion to the number of pixels of the input image, the processing speed decreases. For example, even if the processing time per pixel is 10 ns, if the image information consists of 512 pixels in both the vertical and horizontal directions, it will take 2.6 m to process one image information.
sec. Furthermore, since a computer is used for arithmetic processing, there is a problem in that the apparatus becomes large-scale.

The present invention was made to solve the above-mentioned problems, and it reduces the processing time by making it possible to perform arithmetic processing on each pixel of image information in parallel.
The present invention aims to provide an image information processing device that is smaller and lighter in weight.

[0006]

[Means for Solving the Problems] An image information processing device according to the present invention arranges pnpn optical switches (hereinafter simply referred to as optical switches) in a two-dimensional direction, and applies a driving voltage to the group of optical switches. Two independent connection terminals are provided, one of which is connected to the first power supply via a resistor for each optical switch, and the other is a voltage-controlled negative terminal that connects two adjacent optical switches in parallel. It is connected to a resistance element (hereinafter simply abbreviated as a negative resistance element), and this negative resistance element is connected to a second power source.

[0007]

[Operation] The optical switch array (hereinafter simply referred to as an optical switch array) in which optical switches are arranged in a two-dimensional direction according to the present invention can input and output two-dimensional image information in parallel, and can input and output input information in parallel. Can be processed in parallel. Furthermore, the light emission intensity of the optical switch corresponding to the edge portion of the input image information can be increased.

[0008]

[Example] Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an optical switch array (optical switch array) in which optical switches are arranged in a straight line to explain the present invention.
This is an internal connection diagram of the optical switch array (hereinafter abbreviated as one-dimensional optical switch array), and the internal connection of the optical switch array of the present invention is also
It is basically the same as this figure except that the array of optical switches is spread out in two dimensions. In the figure, 1 is an optical switch, and A, B, C, D, E... represent individual optical switches, which will be abbreviated as element A, element B, etc. hereinafter. 2 is a resistor connected to each optical switch, 3 is a negative resistance element commonly connected to two adjacent optical switches 1, 4 is a first power terminal to which a plurality of resistors 2 are connected, and 5 is a plurality of resistors 1. The second negative resistance element 3 connected to
6 is an optical input terminal, and 7 is an optical output terminal.

FIG. 2 is a structural diagram when the one-dimensional optical switch array shown in FIG. 1 is made into an integrated circuit. As described in the explanation of FIG. 1, the structure of the optical switch array of the present invention is basically the same as that shown in this figure, except that the array of each optical switch is spread out in two dimensions. There is. This figure shows an example in which a tunnel diode (Esaki diode) is used as the negative resistance element 3. In the figure, 10 is G
aAs substrate, 11 is n-type AlGaAs layer, 12 is p-type GaAs layer, 13 is n-type GaAs layer, 14 is p-type AlG
aAs layer, 15 is a GaAs layer corresponding to resistor 3, 16
17 is an n+ GaAs layer, 17 is a p+ GaAs layer, 18 is a lower electrode, 19 is an electrode for parallel connection, 20 is an electrode for applying a driving voltage, and 21 is an insulating region.

Next, the operation will be explained. FIG. 3 is a timing diagram for operating the one-dimensional optical switch array according to the present invention, which consists of two steps. As described in the description of FIGS. 1 and 2, the timing diagram of the optical switch array of the present invention is also similar to this figure. In the first step, power terminal 5
A voltage of positive polarity 1 is applied to the input terminal, and light carrying input information is input. Here, it is assumed that light of equal intensity is input only to elements B, C, and D in FIG. Then, elements B, C, and D become conductive and the same current flows through each of them through the resistor 3.

In the second step, a positive voltage 2 is applied to the power supply terminal 6. When voltage 2 is applied, element B
, D increases than the current flowing through element C, and the optical output of the optical switch is proportional to the current, so elements B and D emit strong light, but since there is no optical input to elements A and E, the current decreases. It is not flowing and therefore does not emit light. Also, the emission intensity of element C is
Since the light emission intensity is smaller than the light emission intensity of the light, the light output of the edge portion of the information input as light is emphasized, so the edge can be detected.

The reason for this will be explained in more detail. FIG. 4 is a partial connection diagram in which only two adjacent optical switches 1 are extracted from the one-dimensional optical switch array according to the present invention. Two optical switches 1 are connected in parallel, and a negative resistance element 4 is connected in series. FIG. 4(a) shows the elements A and B described above, as well as FIG. 4(b).
) is shown for elements B and C. FIG. 5(a) is a characteristic diagram showing the relationship between the voltage V3 applied across the negative resistance element 3 and the current I3 flowing through the negative resistance element 3 for the circuit shown in FIG.
) is a characteristic diagram showing the relationship between the voltage V1 applied across the optical switch 1 in each of the circuits shown in FIGS. 4(a) and 4(b) and the current I3 flowing through the negative resistance element 3 in each circuit. , curve I3a represents the current flowing through the negative resistance element 3 in FIG. 4(a), and curve I3b represents the current flowing through the negative resistance element 3 in FIG. 4(b). In the circuit shown in Figure 4(a), element B
In contrast, in the circuit shown in FIG. 4(b), current flows in both elements B and C, so even if the voltage applied to both ends of optical switch 1 is the same, I3a<
The relationship is I3b.

FIG. 5(c) is an explanatory diagram showing the operating state of each circuit shown in FIGS. 4(a) and 4(b), and the point V2 taken on the horizontal axis indicates It shows the commonly applied power supply voltage, V2=V1+V
There is a relationship of 3. Curve aa corresponds to curve I4a in FIG. 5(b) starting from point V2, and curve bb also corresponds to curve I4a in FIG.
is a curve corresponding to curve I3b in FIG. 5(b), and is a curve corresponding to curve I3b in FIG.
) The intersections of the curve cc corresponding to the curve cc and the curve aa and the curve bb become the operating points of the respective circuits.

By appropriately selecting the power supply voltage V2 in this way, a larger current can flow in the circuit shown in FIG. 4(a) than in the circuit shown in FIG. 4(b). Consider the currents flowing through elements B and C, with these currents being I(AB) and I(BC), respectively. Element B has I(AB)+I(BC)/2, element C has I(
BC) current flows, but I(AB)>I(B
C), so the current flowing through element B is larger than the current flowing through element C. For example, I(AB):I(
BC)=5:1, the current flowing through element B will be 5.5 times the current flowing through element C. Since the current flowing through the optical switch and the emitted light intensity are approximately proportional, elements B and D emit light more strongly than element C, and as a result of the light input information, the emitted light intensity at the edge portion is emphasized. parts can be detected.

[0015] In the above explanation, a one-dimensional optical switch array has been described, but the same operating principle can be applied even when optical switches are arranged in a two-dimensional direction. FIG. 6 is a configuration diagram of an optical switch array (hereinafter simply referred to as an optical switch array) in which optical switches 1 each consisting of 25 elements, 5 in the vertical direction and 5 in the horizontal direction, are arranged in a two-dimensional direction according to the present invention. Only the optical switch 1 and the negative resistance element 3 are shown in order to Optical switches 1 are arranged on each grid point on a plane, and negative resistance elements 3 are connected in series to two adjacent optical switches 1, as in the case of a one-dimensional optical switch array. Similar to a one-dimensional optical switch array, a larger current flows through the optical switch 1 at the edge of the optical input compared to the optical switches at other parts, and as a result, the light emission intensity at the edge of the optical input is emphasized. Edges can be detected. This detection of edge portions also includes corner portions of the optical input.

FIG. 7 is an explanatory diagram of the operation of the optical switch array shown in FIG. 6, in which light of equal intensity is applied only to a square area consisting of three elements in both the vertical and horizontal directions at the center of the optical switch array, for a total of nine elements. indicates that it has been input. Note that α, β, γ, δ, . . . represent individual optical switches, which are hereinafter abbreviated as element α, element β, . FIG. 7A shows the state of optical input, where the surrounding hatched areas indicate areas where no optical input is present, and the white area at the center indicates areas where optical input is present. FIG. 7(b) shows the state of the optical output, and indicates that the smaller the density of the diagonal lines, the higher the optical output. There is no light output from the surrounding areas where there is no light input, and the white areas without diagonal lines indicate the areas with the greatest light output.

The elements α, β, γ, and δ are considered in the same way as the one-dimensional optical switch array described above. There is no light output from element α. Element β has 2 around it.
There are elements with optical inputs. element γ
There are three elements with optical inputs around it. Around the element δ there are four elements with optical inputs. Therefore, by the same operation as in the one-dimensional optical switch array, element β has the strongest optical output, and the optical output decreases in the order of element γ and element δ. It can be seen that by processing these light outputs using an appropriate threshold value, only the edge portions including the corner portions of the light input can be detected.

Example. 2 In the above embodiment, two adjacent optical switches 1 are connected in parallel, and the negative resistance element 3 connected in series with the negative resistance element 3 is connected to the power supply, but each optical switch 1 is connected to a resistor 8. By connecting these two sets of optical switches and the resistor 8 in parallel to the negative resistance element 3, the operation of the optical switch array can be stabilized.

FIG. 8 is a partial connection diagram showing the configuration of the optical switch 1 and the negative resistance element 3 in the second embodiment of the invention, and corresponds to FIG. 4 described above. FIG. 9 is an operation explanatory diagram showing the operating state in this embodiment, and is an explanatory diagram showing the operation state in this embodiment, and is shown in FIG.
). Comparing FIG. 8 with FIG. 4, in FIG. 8 the resistor 8 is connected in series with the optical switch 1. Therefore, due to the voltage drop in the resistor 8, the slope of the curve aa' curve bb' corresponding to the curve a curve b in FIG.
The range of the power supply voltage V2 serving as I3b is expanded, and the operation of the optical switch array becomes stable.

Example. In the above embodiment, a tunnel diode was used as the negative resistance element, but similar effects can be obtained even if a resonant tunnel diode is used as the negative resistance element. FIG. 10 is a structural diagram of a resonant tunnel diode, where 22 is an n-type GaAs layer, 23 is an intrinsic Al
xGa1-xAs layer, 24 is intrinsic GaA
s layer, 25 is intrinsic AlxGa1-xAs
Layer 26 is an n-type GaAs layer. Note that the negative resistance element is not limited to the above two types, and it goes without saying that any element having voltage-controlled negative resistance can be applied in the same manner as in the above embodiment.

Example. In the above embodiment, the operation was explained assuming that the optical switch is a pnpn optical switch that acts as a light emitting diode. By imparting non-linearity to the intensity characteristics, it is possible to emphasize the emission intensity of the edge portion of the input information more than other portions.

[0022]

As described above, according to the present invention, a plurality of optical switches arranged in a two-dimensional direction and a first
and a second power source connected via a voltage-controlled negative resistance element common to two adjacent optical switches among the plurality of optical switches, two-dimensional image information can be transmitted. Since input can be performed in parallel and processing in each element is performed in parallel, image processing can be executed at high speed, and an image information processing apparatus can be realized in a small size and at low cost.

[Brief explanation of the drawing]

FIG. 1 is an internal connection diagram of an optical switch array according to the present invention.

FIG. 2 is a structural diagram of an optical switch array according to the present invention.

FIG. 3 is an operational timing diagram of a one-dimensional optical switch array according to the present invention.

FIG. 4 is a partial connection diagram of two adjacent optical switches in the optical switch array according to the present invention.

FIG. 5 is a characteristic diagram of a negative resistance element and an optical switch according to the present invention, and an explanatory diagram of the operation of the optical switch array according to the present invention.

FIG. 6 is a configuration diagram of an optical switch array according to the present invention.

FIG. 7 is an explanatory diagram of the operation of the optical switch array according to the present invention.

FIG. 8 is a partial connection diagram in a second embodiment of the invention.

FIG. 9 is an explanatory diagram of the operation of the second embodiment of the present invention.

FIG. 10 is a structural diagram of a resonant tunnel diode used in a second embodiment of the invention.

FIG. 11 is a configuration diagram of a conventional image processing device.

[Explanation of symbols]

1 Optical switch 2 Resistor 3 connected to each optical switch Negative resistance element 4 First power terminal 5 Second power terminal 6 Optical input 7 Optical output 8 Resistor 10 GaAs substrate 11 N-type AlGaAs layer 12 P-type GaAs layer 13 n-type GaAs layer 14 p-type AlGaAs layer 15 GaAs layer corresponding to resistor 3 16 n+ GaAs layer 17 p+ GaAs layer 18 lower electrode 19 parallel connection electrode 20 drive voltage application electrode 21 insulating region 22 n-type GaAs layer 23 Trinsic AlxGa1-xAs layer 2
4 Intrinsic GaAs layer 25 Intrinsic AlxGa1-xAs layer 2
6 n-type GaAs layer 30 CCD image sensor 31 computer 32 output device

Claims (1)

[Claims] 1. A plurality of optical switches arranged in a two-dimensional direction, a first power source connected to each of the plurality of optical switches via a corresponding resistor, and two adjacent optical switches among the plurality of optical switches. 1. A parallel information processing device for image processing, comprising: a second power source connected via a voltage-controlled negative resistance element common to the two optical switches.