JPH04302286A - Image pickup device - Google Patents

Abstract

PURPOSE:To directly convert image pickup signals outputted from an image pickup means to digital data with high accuracy for the unit of one picture element. CONSTITUTION:A correlative double sampling circuit 12 executes correlative double sampling to the output signal of a solid-state imaging device 11 and afterwards, the horizontal driving clock of the solid-state imaging device 11 is integrated for one cycle period by supplying the clock to first and second integration circuits 14 and 15 to execute reset alternately with mutually reverse phases for the next one cycle period. The signal integrated by the first and second integration circuits 14 and 15 is alternately sampled by a sampling circuit 17, and the signal sampled by this sampling circuit 17 is converted to a digital signal by an analog/digital converter 18.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an imaging device suitable for a video camera that processes an imaging signal as digital data.

0002

[Background Art] Conventionally, in an imaging device such as a video camera, when converting an imaging signal outputted from a solid-state imaging device such as a CCD imager into digital data, a clock component (readout clock) is removed from the output of the imaging device using a filter. This is done to extract only video data, sample this video data at a predetermined frequency, and convert it into digital data.

However, when the clock component is removed using a filter, the resolution of the video data decreases and the point script function (PS) in the time domain decreases.
F) spread occurs, which is undesirable.

For this reason, a method shown in FIG. 4 has been proposed as a method for directly converting the output of a solid-state image sensor into digital data (see Japanese Patent Laid-Open No. 49561/1983). This circuit supplies the output of the image sensor 1 to an integrator 2, and integrates the image signal every time the integrator 2 outputs an image signal for one pixel. Then, the integral value data of the integrator 2 is supplied to the analog/digital converter 3, where it is converted into digital data according to the integral value, thereby obtaining digital data of the image pickup signal. By doing so, digital conversion is performed with one sampling period for one pixel of the image sensor 1, and a digital image signal with relatively high resolution is obtained.

[0005]

[Problems to be Solved by the Invention] However, when obtaining a digital image signal in this way, it is impossible to completely convert the image signal for one pixel into digital data, and the phase fluctuation of the signal There was an inconvenience that noise was generated due to (sampling clock jitter, etc.).

That is, for example, as the output of the image sensor, the image shown in FIG.
Suppose that the signal shown in is obtained. In the imaging signal shown in FIG. 5A, the level periodically rises and falls due to the influence of the clock component, and the period from when the imaging signal level rises until it falls again corresponds to the imaging signal for one pixel. Therefore, if the value from the lowest level to the highest level (peak-to-peak value) of the image signal for one pixel can be detected, the image signal can be detected for each pixel, but in reality, the image signal contains noise. Since many components are included, the lowest level between each pixel is not constant, making it difficult to accurately detect the level. Therefore, as in the circuit shown in FIG. 4, the influence of noise components can be removed by integrating this image signal in one pixel period and converting the integrated value into digital. However, integrator 2 After performing the integration, it was necessary to reset the integral value once to the "0" level before performing the next integration.

For example, when integrating the image signal shown in FIG. 5A, as shown in FIG. 5B, an interval with a relatively high level is selected within one pixel period and integration S is performed, and the integral value at this time is calculated. Reset R is performed while reading the peak. This integration S and reset R are repeated every time the signal of each pixel is output, but since there is a period of reset R,
It was not possible to integrate all the imaging signals for one pixel period. Therefore, the integral value for each pixel is not completely proportional to the imaging signal level, which causes an inconvenience that an error occurs.

Furthermore, although FIG. 5 shows the case where the period of reset R is most appropriately selected, in reality, there is a phase variation of the reset pulse with respect to the image signal output, so the reset is always performed at the lowest level of the image signal. However, the integral value fluctuates greatly depending on the reset timing, making it difficult to completely convert the image signal for one pixel into digital data without error.

SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide an imaging device that can directly convert an imaging signal outputted from an imaging means into digital data with high precision on a pixel-by-pixel basis.

0010

[Means for Solving the Problems] The present invention has a plurality of pixels arranged in a matrix, as shown in FIG. a solid-state image sensor 11 configured to transfer vertically and then horizontally based on a horizontal drive clock; a correlated double sampling circuit 12 that performs correlated double sampling of the output signal of the solid-state image sensor 11;
For the output signal of this correlated double sampling circuit 12,
The first and second integration circuits 14 and 15 are configured to integrate one period of the horizontal driving clock and reset it in the next one period in an alternate manner with opposite phases to each other. 1. A sampling circuit 17 that alternately samples the signal integrated by the second integration circuits 14 and 15, and an analog/digital converter 1 that converts the signal sampled by the sampling circuit 17 into a digital signal.
8.

[0011]

[Operation] By doing this, the first and second integrating circuits can alternately perform complete integration for one cycle period of the horizontal drive clock, and sampling can be performed based on the data completely integrated for one cycle period. Therefore, it becomes possible to accurately convert the image signal for one pixel into digital data.

0012

Embodiment An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

In FIG. 1, 11 is C as an image sensor.
A CD imager is shown, and the CC from the clock generation circuit 21 is shown.
This CCD imager 11 is synchronized with the vertical drive clock and horizontal drive clock supplied to the D imager 11.
Signal charges accumulated in each pixel formed in a matrix are read out as an imaging signal. That is, the signal charge accumulated in each pixel is transferred vertically based on the vertical drive clock, and then transferred horizontally based on the horizontal drive clock, and the signal charge accumulated in each pixel is synchronized with the horizontal drive clock. is read out as an imaging signal.

[0014] Then, this image pickup signal is supplied to a correlated double sampling circuit (hereinafter referred to as CDS circuit) 12,
Perform correlated double sampling. This correlated double sampling in the CDS circuit 12 is also performed in synchronization with the clock supplied from the clock generation circuit 21. And CDS
The imaging signal outputted by the circuit 12 is supplied to the changeover switch 13, and by switching the changeover switch 13, the imaging signal is changed to the first
is selectively supplied to the second integrating circuit 14 and the second integrating circuit 15. That is, when the movable contact of the changeover switch 13 is switched to the first integrating circuit 14 side, the imaging signal is supplied to the first integrating circuit 14, and the movable contact is switched to the second integrating circuit 15 side. When the imaging signal is input to the second integrating circuit 15
supply to. In this case, the switching of the movable contact of the changeover switch 13 is performed by the clock generation circuit 21 as described later.
This is done in synchronization with the horizontal drive clock output by

First integrating circuit 14 and second integrating circuit 15
This integrates the supplied imaging signal, and as will be described later, a reset pulse is supplied in synchronization with the horizontal drive clock output from the clock generation circuit 21. Then, the integrated data of the first integrating circuit 14 and the integrated data of the second integrating circuit 15 are transferred to each other using a changeover switch 16.
and both integral data are selected by this changeover switch 16. In this case, switching of the movable contact of the changeover switch 16 is performed in conjunction with the changeover switch 13 in synchronization with the horizontal drive clock output from the clock generation circuit 21, as will be described later. However, the integration circuits selected by both selector switches 13 and 16 are set in the opposite manner. That is, when the selector switch 13 is switched to the first integrating circuit 14 side, the selector switch 16 is switched to the second integrating circuit 15 side, and the selector switch 13 is switched to the second integrating circuit 15 side.
is switched to the second integrating circuit 15 side, the changeover switch 16 is switched to the first integrating circuit 14 side.

Then, the integral data selected by the changeover switch 16 is supplied to the sample/hold circuit 17 and sampled at a predetermined timing. In this example, the sample/hold circuit 17 performs sampling immediately after the changeover switches 13 and 16 are switched. Then, the signal sampled by the sample/hold circuit 17 is supplied to an analog/digital converter 18, and the analog/digital converter 18 converts each sampled data into digital data. The digital data output from the analog/digital converter 18 is then supplied to a subsequent digital imaging signal processing circuit (not shown).

The clock generation circuit 21 also supplies a vertical drive clock to the CCD imager 11 and the CDS circuit 12.
In addition to supplying various clocks such as a horizontal driving clock, a sampling clock synchronized with the vertical driving clock and the horizontal driving clock is supplied to the first and second integrating circuits 14.
, 15 and changeover switches 13, 16. That is, the clock generation circuit 21 outputs a clock having the same frequency as the horizontal drive clock, and this output clock is passed through the 1/2 frequency divider 2.
Supply to 2. Then, with this 1/2 frequency divider 22, 1/2
A clock having a frequency of 1 is supplied to the changeover switches 13 and 16 as a changeover control signal, and both changeover switches 13 and 16 are switched in conjunction with the change in this clock. Also, a clock with the same frequency as the horizontal drive clock outputted by the clock generation circuit 21 and an inverted signal of the clock with a frequency of 1/2 outputted by the 1/2 frequency divider 22 are ANDed.
The AND gate 23 supplies the logical product output of the AND gate 23 to the first integrating circuit 14 as a reset pulse. Furthermore, a clock having the same frequency as the horizontal drive clock outputted by the clock generation circuit 21 and a 1/2 frequency divider 22
AND the clock whose frequency is 1/2 that is output by
The AND gate 24 supplies the logical product output of the AND gate 24 to the second integration circuit 15 as a reset pulse.

Next, the operation of the imaging device of this example will be explained with reference to the timing diagram of FIG. 2. For example, the CDS circuit 12
Assume that the imaging signal shown in FIG. 2A is output from. This imaging signal is read out from the CCD imager 11 based on a horizontal drive clock having the same frequency as the clock shown in FIG. 2G, and the imaging signal for one pixel is read out in one cycle of the clock shown in FIG. 2G. Output. Here, since the changeover switches 13 and 16 are switched in synchronization with the clock shown in FIG. It will be performed alternately each time it is supplied. For example, at the timing when the image pickup signal of a certain pixel is output, the changeover switch 13
is switched to the first integrating circuit 14 side, Fig. 2B
As shown in FIG.
It is integrated by 4. Then, at the timing when the image signal of the next pixel is output, the changeover switch 13 is switched to the second integrating circuit 15 side, and as shown in FIG. 2C, the image signal of this pixel is outputted to the second integrating circuit 15. It is integrated. Therefore,
Every time an image signal for one pixel is supplied, both integration circuits 14 and 15 perform integration alternately.

Then, when each integrating circuit 14 and 15 integrates one pixel, the changeover switch 13 is switched to the other side at the timing when the image signal of the next pixel is supplied, so the signal is not integrated until the reset pulse is supplied. This integrated value for one pixel is held. Here, the reset pulse (FIG. 2C) supplied to the first integration circuit 14 is an inverted signal of the clock (FIG. 2G) synchronized with the horizontal drive clock, and this FIG.
A clock obtained by dividing the clock shown in G into 1/2 (Fig. 2F
). Therefore, at approximately the midpoint of the period during which the selector switch 13 is switched to the other side, the reset pulse supplied to the first integrating circuit 14 rises, and at this rising timing, the integrated value of the first integrating circuit 14 is reset. be done. And sample/hold circuit 17
Since sampling is performed immediately after the changeover switches 13 and 16 are switched, sampling is performed while the first integrating circuit 14 is holding the integral value for one pixel, and this The sampled values are converted into digital data.

Similarly, the reset pulse (FIG. 2E) supplied to the second integration circuit 15 is a clock synchronized with the horizontal drive clock (FIG. 2G) and a clock shown in FIG. 2G divided by half. This is the AND with the clock (FIG. 2F). Therefore, at approximately the midpoint of the period during which the selector switch 13 is switched to the other side, the reset pulse supplied to the second integrating circuit 15 rises, and at this rising timing, the integrated value of the second integrating circuit 15 is reset. be done. Then, while the second integration circuit 15 is holding the integrated value for one pixel, sampling is performed in the sample/hold circuit 17, and this sampling value is converted into digital data.

In this manner, the image signal from the CCD imager 11 is converted into digital data as an integral value for each pixel as shown in FIG. 2H. Note that FIG. 2H shows digital data in levels.

[0022] By converting into digital data in this way, each sampled data to be digitalized becomes an integral value of one pixel period of the image pickup signal, and the image pickup signal level for each pixel is accurately converted into digital data. . In other words, since the integration circuits 14 and 15 alternately integrate one pixel at a time, the integral value sampled by the sample/hold circuit 17 is exactly the value integrated for one pixel, and in order to provide a reset period. Compared to conventional circuits that cannot integrate the period during which an image signal for one pixel is obtained, a highly accurate digital image signal for each pixel can be obtained with fewer errors and no influence of noise. In this case, if the integration period is a period in which an image signal for one pixel is output, even if the phase of the integration operation clock and sampling clock for the image signal changes, there is almost no change in the integral value itself, and the clock The jitter component does not adversely affect the digital data, and stable digital data can always be obtained, and from this point of view, highly accurate digital data can also be obtained.

[0023] In the above embodiment, the changeover switch 13,
16, the two sets of integrating circuits 14 and 15 are switched in one pixel period, but since the period during which one pixel's image signal is obtained is very short, the changeover switches 13 and 16 require high-speed operation. It is also possible to adopt a configuration that does not use a changeover switch that performs this high-speed operation.

That is, FIG. 3 shows a circuit configuration that does not use a changeover switch, and the imaging signal output from the CDS circuit 12 is supplied to the amplifiers 31 and 41. The outputs of the respective amplifiers 31 and 41 are supplied to one end of the resistors 32 and 42 forming the integrating circuit, and the other ends of the respective resistors 32 and 42 are connected to the capacitors 33 and 42 forming the integrating circuit. 43 to ground. Furthermore, resistor 32,
42 and the capacitors 33, 43 are grounded via connection switches 34, 44, respectively. and,
A level signal obtained at the midpoint between the resistors 32 and 42 and the capacitors 33 and 43 is supplied to the adder 51.
The addition output of 1 is supplied to the sample/hold circuit 17.

Further, the clock synchronized with the horizontal drive clock outputted from the clock generation circuit 21 is passed through the 1/2 frequency divider 5.
Supply to 2. Then, the inverted signal of the output of this 1/2 frequency divider 52 and the inverted signal of the clock outputted by the clock generation circuit 21 are supplied to an AND gate 53, and the logical product output of the AND gate 53 is connected to the connection switch 34. Supplied as a control signal. Further, the output of the 1/2 frequency divider 52 and the inverted clock signal outputted by the clock generation circuit 21 are
The signal is supplied to an AND gate 54, and the AND output of the AND gate 54 is supplied to the connection switch 44 as a connection control signal.

A clock synchronized with the horizontal drive clock outputted by the clock generation circuit 21 is also supplied to the sample/hold circuit 17, so that the output of the adder 51 is sampled at the timing when this clock rises.

The other parts are constructed in the same manner as the imaging apparatus shown in FIG.

With this configuration, the resistor 32 and the capacitor 33 constitute a first integrating circuit, the resistor 42 and the capacitor 43 constitute a second integrating circuit,
Integrating operations of both integrating circuits are controlled by connection switches 34 and 44. That is, the connection switches 34 and 44 repeat the connected state and the disconnected state every time one pixel's worth of imaging signals are output, and the first integration circuit made up of the resistor 32 and the capacitor 33 is connected when the connection switch 34 is disconnected. When the capacitor 33 is in the connected state, the capacitor 33 accumulates the imaging signal, and when the connected state is reached, the capacitor 33 is reset. In addition, a resistor 42 and a capacitor 43
In the second integrating circuit, the capacitor 43 accumulates the imaging signal when the connection switch 44 is in the disconnected state, and is reset when the connection switch 44 is in the connected state. The integration operation in both integration circuits is similar to the imaging device shown in FIG.
This is done alternately every time the imaging signal for a pixel is output, so the integral value of one pixel period of the imaging signal is sampled by the sample/hold circuit 17, and digital imaging for each pixel with little error and no influence of noise is achieved. I get a signal.

However, in the case of the configuration shown in FIG.
The two integration circuits are not switched by a switch, and the integration of the image signal is performed in the integration circuit unless it is reset, and the integration operation does not stop when one pixel is integrated as shown in FIGS. 2B and 2D. Therefore, it is necessary to ensure that data integrated over a period equivalent to one pixel is not sampled, and when sampling the integrated value of one integrating circuit, the integrated value of the other integrating circuit must be set to 0. It is necessary to keep it. Therefore, when sampling is performed when the clock output by the clock generation circuit 21 rises (that is, when one pixel is integrated), only the integral value for one pixel integrated by one of the integrating circuits is sampled. It is set as.

Note that in the case of the configuration shown in FIG.
Although a simple integrating circuit using a resistor and a capacitor is used, a more accurate integrating circuit using a constant current source may be used.

Furthermore, it goes without saying that the present invention is not limited to the above-mentioned embodiments, but can take various other configurations.

[0032]

According to the present invention, the first and second integrating circuits can alternately perform complete integration over one period of the horizontal drive clock, and sampling can be performed based on data completely integrated over one period. Therefore, the imaging signal can be accurately converted into digital data pixel by pixel, and the imaging signal output from the imaging means can be converted into digital data with the highest precision. In this case, regardless of the phase relationship between the processing clock for converting into digital data and the imaging signal, it will not have a negative effect on the digital data to be converted, so stable and good digital data without noise can always be obtained. It will be done.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a timing diagram illustrating sampling conditions according to one embodiment.

FIG. 3 is a configuration diagram showing another embodiment of the present invention.

FIG. 4 is a configuration diagram showing an example of a conventional imaging device.

FIG. 5 is a timing diagram showing a conventional sampling state.

[Explanation of symbols]

11 CCD imager 12 Correlated double sampling circuit (CDS circuit) 14
First integration circuit 15 Second integration circuit 17 Sample/hold circuit 18 Analog/digital converter 21 Clock generation circuit 22 1/2 frequency divider 23, 24, 53, 54 AND gates 31, 41
Amplifier

Claims (1)

[Claims] 1. A plurality of pixels are arranged in a matrix, and electrical signals obtained by photoelectric conversion by the plurality of pixels are transferred vertically based on a vertical drive clock, and then transferred horizontally based on a horizontal drive clock. a solid-state image sensor configured to transfer signals to the solid-state image sensor; a correlated double sampling circuit that performs correlated double sampling of the output signal of the solid-state image sensor;
First and second integrals are configured to perform integration for one period of the horizontal drive clock on the output signal of the correlated double sampling circuit, and reset for the next one period, in opposite phases to each other, alternately. Based on the circuit and the horizontal clock above,
The invention is characterized by comprising a sampling circuit that alternately samples the signals integrated by the first and second integrating circuits, and an analog/digital converter that converts the signals sampled by the sampling circuits into digital signals. imaging device.