JPH04302014A - Logic circuit driving device - Google Patents

Abstract

PURPOSE:To suppress an excessive noise due to system clock and power consumption as much as possible by supplying the system clock to a logical element as necessary. CONSTITUTION:When operational information signals 14a-14c are inputted to functional blocks 11-13, or when processing signals 19a-19c are outputted based on the operational information signals 14a-14c, an operation starting signal or an operation end signal is outputted to a status signal included in status information signals 16a-16c. A sequence controller 15 executes or stops the supply of a system clock 20 through signals 17a-17c for operation to the pertinent functional block by this status signal.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit driving device for synchronously operating a plurality of logic circuits constituted by various logic elements using a system clock signal.

0002

2. Description of the Related Art Conventionally, for example, as shown in FIG. 5, a plurality of functional blocks 1, 2, and 3, which are logic circuits, are provided, and each of these functional blocks 1 to 3 receives operation information signals 4a, 4a, and 4b, respectively.
4b and 4c are input, and the system clock 5 is also input for operation, and as a result of the operation, processed signals 7a, 7b, and 7c are output from each of the functional blocks 1 to 3. Note that when the operational information signal 4a is input to the functional block 1, the operational information signal 4b is input from the functional block 1 to the next functional block 2, and when the operational information signal 4b is further input to the functional block 2, Operation information signal 4 from function block 2 to the next function block 3
c is now input. Further, each of the functional blocks 1 to 3 is reset by a system reset 6.

The functional block 1, as shown in FIG.
It is composed of various logic elements, such as flip-flops 1a and 1e, gate circuits 1b and 1f, counters 1c and 1d, and inverters 1g and 1h. Although not shown, other functional blocks 2 and 3 also have similar circuit configurations.

In this conventional example, first, when the operation information signal 4a is input to the functional block 1, the flip-flop 1a operates, thereby causing the system clock 6 to be counted by the counters 1c and 1d, and from the counter 1d to the next one. The operation information signal 4b is output to the functional block 2 of the stage, and the processed signal 7a is output from the counter 1c. That is, the operation information signal 4b is outputted regardless of the output timing of the processed signal 7a.

Functional block 2 performs a similar operation based on operational information signal 4b from functional block 1, and outputs operational information signal 4c and processed signal 7b.

Function block 3 performs a similar operation based on the operation information signal 4c from function block 2, and outputs a processed signal 7c. Note that since the functional block 3 is the final stage, no operation information signal is output.

Furthermore, when the system reset 5 is input to each of the functional blocks 1 to 3, the operations of each of the functional blocks 1, 2, and 3 are reset.

FIG. 7 shows input/output timings of the system reset 5, system clock 6, operation information signal 4a, processing signal 7a, and operation information signal 4b regarding the functional block 1.

As described above, according to the conventional example, the system clock is always input to each functional block and the logic elements constituting this functional block.

[0010] In recent years, with the demand for high-speed processing in devices, system clocks have become faster, and the amount of logic elements used in circuits has also increased, and the logic elements mounted on printed circuit boards are As they become smaller, they become more dense.

[0011]

One of the causes of malfunctions in other electronic devices is noise generated by current flowing when logic elements turn on and off. Since the system clock turns the logic element on and off when it is input to the logic element, noise is further increasing as the system clock becomes faster and the packaging density becomes higher.

Normally, the system clock is always supplied to most logic elements, but most logic elements
Since the logic element is not always involved in the operation processing in the circuit, the noise generated by the system clock supplied to the logic element when not involved in the operation processing has been a problem as unnecessary noise.

Similarly, the power consumed by the system clock supplied to the logic elements when not involved in the operation processing in the circuit has also been problematic as unnecessary power consumption.

[0014] Therefore, the present invention provides clock frequency control that can supply a system clock to logic elements only during times when they are required to operate, thereby minimizing noise and power consumption generated by the system clock. The purpose is to provide equipment.

[0015]

[Means for Solving the Problems] The present invention provides a logic circuit driving device that operates a plurality of logic circuits constituted by various logic elements in synchronization with a system clock signal, in which an operation information signal is input to each logic circuit. a plurality of status output means that output an operation start signal when the operation is completed, and output an operation end signal when the operation of each logic circuit is completed; and a corresponding logic circuit based on the operation start signal from each status output means. and clock supply control means for supplying a system clock signal to the logic circuit and stopping supply of the system clock signal to the corresponding logic circuit based on the operation completion signal from each status output means.

[0016]

In the present invention having such a structure, when an operation information signal is input to the logic circuit, an operation start signal is input from the status output means to the clock supply control means.

Then, the system clock signal is supplied from the clock supply means to the corresponding logic circuit.

The corresponding logic circuit performs an operation based on the operation information signal using the supplied system clock signal.

When the logic circuit finishes its operation based on the operation information signal, an operation end signal is output from the status output means.
The signal is input to the clock supply control means.

Then, the system clock signal being output to the corresponding logic circuit is stopped by the clock supply means.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, functional blocks 11, 12, and 13, which are a plurality of logic circuits, are provided, and operation information signals 14a, 14b are provided to each of these functional blocks 11 to 13, respectively.
, 14c are input. When the operational information signal 14a is input to the functional block 11, the operational information signal 14b is input from the functional block 11 to the functional block 12 at the next stage, and when the operational information signal 14b is further input to the functional block 12. , an operation information signal 14c is input from the functional block 12 to the functional block 13 at the next stage.

Status information signals 16a, 16b, and 16c consisting of a plurality of signals including status signals are input from the functional blocks 11 to 13 to a sequence controller 15 serving as clock supply control means.

Operation signals 17a and 17b each consisting of a plurality of signals including a system clock are sent from the sequence controller 15 to each of the functional blocks 11 to 13.
, 17c are input.

A system reset 18 is input to each of the functional blocks 11 to 13.

Operation signals 14a to 14c and operation signals 17a to 17c including the system clock are input, and each functional block 11 to 13 operates, and as a result of the operation, a processed signal 19a is output from each functional block 11 to 13.
, 19b, and 19c are output.

A system clock 20 is input to the sequence controller 15.

The functional block 11 and the sequence controller 15 are wired as shown in FIG.
The functional block 11 includes various logic elements, such as flip-flops 11a and 11e, gate circuits 11b and 11f.
, counters 11c, 11d, inverters 11g, 11h
The sequence controller 1
5 includes various logic elements for the functional block 11, such as flip-flops 15a and 15b, and an AND circuit 15.
It is composed of c.

The flip-flop 11a of the functional block 11 constitutes status output means. Although not shown, the other functional blocks 12 and 13 have similar circuit configurations, and the sequence controller 15
Similarly to the circuit configuration for the functional block 11, the functional blocks 12 and 13 also have a similar circuit configuration.

From the output terminal of the flip-flop 11a of the functional block 11 to the sequence controller 15
A status signal line 21 is connected to one input terminal of an AND circuit 15c. Note that this AND circuit 15c
A system clock 20 is input to the other input terminal of the . Then, from the output terminal of the AND circuit 15c to the counters 11c and 11d of the functional block 11,
A clock signal line 22 is connected to the LK (clock) terminal.

In this embodiment having such a configuration, when the operation information signals 14a to 14c are not input, the system clock is not supplied to the functional blocks 11 to 13.

Here, when the operation information signal 14a is input to the functional block 11, an operation start signal is output from the flip-flop 11a of the functional block 11 to the status signal line 21. Then, the system clock 20 is output from the AND circuit 15c to the clock signal line 22. This system clock 20 is supplied to the flip-flop 15b and the counters 11c, 11d, and the operation start signal on the status signal line 21 operates the counters 11c, 11d via the flip-flop 15b. As a result, the counter 11d outputs the operation information signal 14b to the next stage functional block 12, while the counter 11c outputs the processed signal 19a.

At this time, the processed signal 19a is input to the R (reset) terminal of the flip-flop 11a via the flip-flop 15a and the gate circuit 11b, and an operation end signal is output to the status signal line 21. Then, the system clock 20 that was being output from the AND circuit 15c to the clock signal line 22 is stopped.

Regarding the functional block 11 at this time,
It has been confirmed that the input/output timings of the system reset 18, system clock, operating information signal 14a, processed signal 19a, and operating information signal 14b are the same as those shown in FIG.

[0035] Of course, the above is true of function block 1.
2 and 13 operate similarly.

As described above, according to this embodiment, the supply of the system clock to the functional block can be started when the operation information signal is input, and can be stopped when the processing signal is output. Therefore, noise generated by the system clock can be prevented and power consumption can be minimized between the output of the processed signal and the input of the next operation information signal. Moreover,
In operation processing, the timing is the same as in the conventional system which always supplies the system clock, so no problems occur.

Next, another embodiment of the present invention will be described with reference to the drawings.

What is shown in FIG. 3 is an operation in which the functional blocks 31 and 32 are processed in parallel by the OR circuit 30, and the operation information signals 35c and 35d outputted from the functional blocks 31 and 32 are ORed to the functional block 33. It outputs an information signal 35e.

Functional block 31, which is a plurality of logic circuits;
32, 33, and 34 are provided, and each of these functional blocks 31
to 34 are operational information signals 35a, 35b, and 35e, respectively.
, 35f are input, and when the operation information signal 35a is input to the functional block 31, the operation information signal 35c is input from the function block 31 to one input terminal of the OR circuit 30, Further, when the operation information signal 35b is input to the functional block 32, the operation information signal 35d is input from the function block 32 to the remaining input terminal of the OR circuit 30.

The OR circuit 30 performs OR processing on the operation information signals 35c and 35d input to each input terminal, and the operation information signal 35e as a result of the processing is input to the function block 33 at the next stage. . When the operational information signal 35e is input to the functional block 33, the operational information signal 35f is sent from the functional block 33 to the functional block 34.
is now entered.

Status information signals 37a, 37b, 37c, which are composed of a plurality of signals including status signals, are sent from the functional blocks 31 to 34 to the sequence controller 36.
37d is input.

Operation signals 38a and 38b each consisting of a plurality of signals including a system clock are sent from the sequence controller 36 to each of the functional blocks 31 to 34.
, 38c, and 38d are input.

A system reset 39 is input to each of the functional blocks 31 to 34, and processed signals 40a, 40b, 40c,
40d is output, and the system clock 41 is input to the sequence controller 36.

In this embodiment having such a configuration, when each functional block 31 to 34 receives an operation information signal,
An operation start signal is output to the status signal included in the status information signal. Then the sequence controller 36
The system clock 41 is supplied to the corresponding functional block from the system clock 41.
performs the operation and outputs the processed signal. Then, an operation end signal is output as a status signal from the corresponding functional block to the system controller 36 according to the processed signal, and the system clock 41 from the sequence controller 36 is output.
supply will be stopped.

Even when the OR logic circuit 30 is used in this way, each of the functional blocks 31 to 34 is supplied with the system clock from the sequence controller 36 when the operation information signal is input, starts operating, and outputs the processed signal. When this happens, the system clock supply will be stopped.

[0046] Therefore, in this embodiment as well, the same effects as in the previous embodiment can be obtained.

Furthermore, what is shown in FIG. 4 is an AND logic circuit 50.
Process the function blocks 51 and 52 in parallel by
The functional block 53 outputs an operational information signal 55e obtained by ANDing operational information signals 55c and 55d output from the functional blocks 51 and 52.

Functional block 51, which is a plurality of logic circuits;
52, 53, and 54 are provided, and each of these functional blocks 51
to 54 are operational information signals 55a, 55b, and 55e, respectively.
, 55f are input, and when the operation information signal 55a is input to the functional block 51, the operation information signal 55c is input from the function block 51 to one input terminal of the AND logic circuit 50. , and when the operation information signal 55b is input to the functional block 52,
An operation information signal 55d is input from the functional block 52 to the remaining input terminal of the AND logic circuit 50.

The AND logic circuit 50 performs AND processing on the operation information signals 55c and 55d input to each input terminal, and the operation information signal 55e as a result of the processing is input to the function block 53 at the next stage. Ru. When the operational information signal 55e is input to the functional block 53, the operational information signal 55f is input from the functional block 53 to the functional block 54.

Status information signals 57a, 57b, 57c, which are composed of a plurality of signals including status signals, are sent from the functional blocks 51 to 54 to the sequence controller 56.
57d is input.

Operation signals 58a and 58b each consisting of a plurality of signals including a system clock are sent from the sequence controller 56 to each of the functional blocks 51 to 54.
, 58c, and 58d are input.

A system reset 59 is input to each of the functional blocks 51 to 54, and processed signals 60a, 60b, 60c,
60d is output, and the system clock 61 is input to the sequence controller 56.

In this embodiment having such a configuration, each of the functional blocks 51 to 54 inputs an operation information signal, and then receives the operation information signal.
An operation start signal is output to the status signal included in the status information signal. Then, the system clock 61 is supplied from the sequence controller 56 to the corresponding functional block, and the corresponding functional block operates based on the system clock 61 and outputs a processed signal. Then, an operation end signal is output as a status signal from the corresponding functional block to the system controller 56 in response to the processing signal, and the supply of the system clock 61 from the sequence controller 56 is stopped.

Even when the AND logic circuit 50 is used in this manner, each of the functional blocks 51 to 54 is supplied with a system clock from the sequence controller 56 when an operation information signal is input, starts operation, and outputs a processed signal. When this happens, the system clock supply will be stopped.

[0055] Therefore, in this embodiment, the same effects as in the previous embodiment can be obtained.

[0056]

[Effects of the Invention] As detailed above, according to the present invention,
A system clock can be supplied to logic elements only during the time when they are required to operate, thus providing a clock frequency control device that minimizes noise and power consumption caused by the system clock.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram showing an embodiment of the present invention.

FIG. 2 is a partial circuit diagram showing the same embodiment.

FIG. 3 is a circuit block diagram showing another embodiment of the invention.

FIG. 4 is a circuit block diagram showing another embodiment of the invention.

FIG. 5 is a circuit block diagram showing a conventional example.

FIG. 6 is a partial circuit diagram showing the conventional example.

[Figure 7] Diagram of input/output timing of each signal showing the conventional example

[Explanation of symbols]

11, 12, 13...Functional block, 14a, 14b, 1
4c...operation information signal, 15...sequence controller,
16a, 16b, 16c...Status information signal, 17a
, 17b, 17c...operation signal, 19a, 19b, 19
c...Processing signal, 20...System clock.

Claims (1)

[Claims] 1. In a logic circuit driving device that operates a plurality of logic circuits constituted by various logic elements in synchronization with a system clock signal, an operation start signal is generated when an operation information signal is input to each of the logic circuits. a plurality of status output means for outputting an operation end signal when the operation of each of the logic circuits is completed, and supplying a system clock signal to the corresponding logic circuit based on the operation start signal from each of the status output means. and clock supply control means for stopping supply of a system clock signal to a corresponding logic circuit based on an operation end signal from each of the status output means.