JPH0729261A - System for controlling drum servo - Google Patents

System for controlling drum servo

Info

Publication number
JPH0729261A
JPH0729261A JP5170171A JP17017193A JPH0729261A JP H0729261 A JPH0729261 A JP H0729261A JP 5170171 A JP5170171 A JP 5170171A JP 17017193 A JP17017193 A JP 17017193A JP H0729261 A JPH0729261 A JP H0729261A
Authority
JP
Japan
Prior art keywords
signal
drum
mask
circuit
reset
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5170171A
Other languages
Japanese (ja)
Other versions
JP2798870B2 (en
Inventor
Kinji Uno
欣治 宇野
Shigeru Kiyomiya
茂 清宮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP5170171A priority Critical patent/JP2798870B2/en
Publication of JPH0729261A publication Critical patent/JPH0729261A/en
Application granted granted Critical
Publication of JP2798870B2 publication Critical patent/JP2798870B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To reduce a maximum amount of an initial drum phase error at the time of switching to a VSYNC reference mode by supplying a first, a second set signals from first, second signal generation circuits to an AND circuit, generating a third set signal and controlling a switch circuit. CONSTITUTION:By the first signal generation circuit 5, counting is started making a vertical synchronizing signal a reset signal, and a mask signal PM1 falling by the reset signal and rising at eleventh count is outputted, and the first set signal PS1 is outputted after the period of the signal PM1. The second signal generation circuit 6 is reset when a PG signal PG1 is inputted, and the second set signal PS2 starting the counting from l, rising at tenth count and falling at twenty-twoth count is outputted. By the outputs of the circuits 5, 6, the third set signals PS3, PS'3 signals and a third mask signal PM3 are outputted through the AND circuit, and the switch 3 is turned on/off by the third set signals PS3, PS'3, and the vertical synchronizing signal is supplied to a drum control circuit 8 for the period of the signal PS, and the drum phase error is reduced.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はVTRのドラムサーボ制
御システムに関するものであり、特に外部から入力され
る垂直同期信号を1つおきにマスクする回路を備えたド
ラムサーボ制御システムに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a VTR drum servo control system, and more particularly to a drum servo control system having a circuit for masking every other vertical synchronizing signal input from the outside.

【0002】[0002]

【従来の技術】VTRのドラムサーボ制御回路では外部
から入力される50Hz又は60Hzの垂直同期信号を
1/2の周波数(25Hz又は30Hz)に成すために
垂直同期信号の入力路に、図4に示す如く、同期信号規
制回路50を設けて同期信号を1つおきにマスクするよ
うにしている。
2. Description of the Related Art In a drum servo control circuit of a VTR, a vertical synchronizing signal of 50 Hz or 60 Hz input from the outside is formed in a vertical synchronizing signal input path in order to form a half frequency (25 Hz or 30 Hz). As shown, a synchronization signal regulation circuit 50 is provided to mask every other synchronization signal.

【0003】同図において、51は外部からの垂直同期
信号の入力路であり、52はスイッチである。このスイ
ッチ52のON/OFFはスイッチ制御信号発生回路5
3の出力によって制御される。スイッチ制御信号発生回
路53はスイッチ52の出力の垂直同期信号「図5
(c)に示す(ハ)」をリセット信号として線路55を
通して与えられるドラムFG信号「図5(b)」をカウ
ントし、このリセット信号から20カウントまでの間、
ローレベルとし、20カウント以降をハイレベルにする
が、24カウント目で垂直同期信号(ホ)によりリセッ
トされるので、24カウント目以降をローレベルとする
信号「図5(d)」を出力する。
In the figure, reference numeral 51 is an input path for a vertical synchronizing signal from the outside, and 52 is a switch. This switch 52 is turned ON / OFF by the switch control signal generation circuit 5
3 output. The switch control signal generation circuit 53 uses the vertical synchronization signal output from the switch 52 as shown in FIG.
The drum FG signal “FIG. 5 (b)” given through the line 55 as a reset signal “(c)” in (c) is counted, and from the reset signal to 20 counts,
A low level is set and a high level is set for 20th and subsequent counts. However, since the vertical synchronization signal (e) is reset at the 24th count, a signal "FIG. 5 (d)" that sets the low level for the 24th count and thereafter is output. .

【0004】スイッチ52は、そのハイレベル期間のみ
ONとなり、ローレベル期間ではOFFとなる。このた
め図5(c)に示す、次の垂直同期信号(ニ)はマスク
される。(ホ)と(ヘ)は同様の動作の繰り返しによっ
て、(ホ)が許可され、(ヘ)はマスクされる。図5
(e)はスイッチ52の出力路54に生じる出力信号、
即ち25/30Hzの垂直同期信号を示している。
The switch 52 is turned on only during the high level period and turned off during the low level period. Therefore, the next vertical synchronizing signal (d) shown in FIG. 5C is masked. By repeating the same operation for (e) and (e), (e) is permitted and (e) is masked. Figure 5
(E) is an output signal generated on the output path 54 of the switch 52,
That is, the vertical synchronizing signal of 25/30 Hz is shown.

【0005】[0005]

【発明が解決しようとする課題】ところで、VTRにお
いて、録画をする時のドラムAPC(自動位相制御)は
レファレンス信号を基準とするモード(D-REF基準
モード)から垂直同期信号を基準とするモード(VSY
NC基準モード)へ切り換えられるが、この基準モード
切り換え時に、上記従来例の同期信号規制回路では、D
-REF基準モードの時にヘッド切り換え信号「図5
(a)」に対して任意の位置にあった垂直同期信号を基
準にして前記マスク期間の切り換え設定を行うことにな
るため、VSYNC基準モードに切り換えた時の最初の
垂直同期信号とヘッド切り換え信号(a)間の位相と、
ドラムAPCの目標値(位相)との差(以下「ドラム位
相誤差」という)が大きくなる場合があった。そして、
この大きなドラム位相誤差が生じると、目標値へ引き込
むまでの時間が長くかかってしまう。これは、明らかに
録画開始時の画質劣化を招く。
By the way, in the VTR, the drum APC (automatic phase control) at the time of recording is changed from the mode based on the reference signal (D-REF reference mode) to the mode based on the vertical synchronization signal. (VSY
NC reference mode), but when the reference mode is switched, the synchronization signal regulating circuit of the above-mentioned conventional example uses D
-Head switching signal in REF standard mode
Since the mask period switching setting is performed with reference to the vertical sync signal at an arbitrary position with respect to (a), the first vertical sync signal and head switching signal when switching to the VSYNC reference mode. The phase between (a) and
In some cases, the difference from the target value (phase) of the drum APC (hereinafter referred to as "drum phase error") becomes large. And
When this large drum phase error occurs, it takes a long time to pull in the target value. This obviously causes deterioration of image quality at the start of recording.

【0006】本発明はこのような点に鑑みなされたもの
であって、VSYNC基準モードへの切り換え時の最初
のドラム位相誤差の最大量を小さくするように工夫した
新規なドラムサーボ制御システムを提供することを目的
とする。
The present invention has been made in view of the above circumstances, and provides a novel drum servo control system devised so as to reduce the maximum amount of the first drum phase error at the time of switching to the VSYNC reference mode. The purpose is to do.

【0007】[0007]

【課題を解決するための手段】上記の目的を達成するた
め本発明のドラムサーボ制御システムは、VTRのドラ
ムサーボ制御回路と、外部から入力される垂直同期信号
を前記ドラムサーボ制御回路へ入力する入力路に設けら
れたスイッチ手段と、前記ドラムサーボ制御回路へ入力
される垂直同期信号をリセット信号とし該リセット信号
からドラムFG信号をカウントして所定カウント値まで
の時間に対応する幅の第1マスク信号を生じるととも
に、該第1マスク信号期間以外は第1セット信号を生じ
る第1の信号発生手段と、ドラムPG信号をリセット信
号とし該リセット信号からドラムFG信号をカウントし
て第1のカウント値と第2のカウント値で決まる幅の第
2セット信号を生じるとともに、該第2セット信号以外
は第2マスク信号を生じる第2の信号発生手段と、前記
第1、第2セット信号が共に存在する期間の幅の第3セ
ット信号を出力するとともに、該第3セット信号期間以
外は第3マスク信号を生じ、前記第3セット信号によっ
て前記スイッチ手段をONさせ、第3マスク信号によっ
て前記スイッチ手段をOFFさせるように前記スイッチ
手段を制御する論理手段とを備えている。
In order to achieve the above object, a drum servo control system of the present invention inputs a drum servo control circuit of a VTR and a vertical synchronizing signal input from the outside to the drum servo control circuit. A switch means provided in the input path and a vertical synchronizing signal input to the drum servo control circuit as a reset signal, the drum FG signal is counted from the reset signal, and a first width having a width corresponding to a time up to a predetermined count value is obtained. First signal generating means for generating a mask signal and for generating a first set signal except during the first mask signal period, and a drum FG signal is counted from the reset signal by using the drum PG signal as a reset signal, and a first count is performed. A second mask signal having a width determined by the value and the second count value is generated, and a second mask signal is generated except for the second mask signal. And a second signal generating means for outputting a third set signal having a width of a period in which both the first and second set signals are present, and a third mask signal is generated in a period other than the third set signal period. Logic means for controlling the switch means so that the switch means is turned on by the third set signal and the switch means is turned off by the third mask signal.

【0008】[0008]

【作用】このような構成によると、第2マスク信号はス
イッチ手段を通過した垂直同期信号によって生じ、この
垂直同期信号の次の垂直同期信号は論理手段から得られ
る第3セット信号の期間に入らないので、スイッチ手段
を通過できずマスクされることになる。第2セット信号
はドラム位相目標をその第2セット信号の略中央に位置
するような関係にセットでき、この第2セット信号と第
1セット信号の論理積出力でスイッチ手段を制御するこ
とにより、そのドラム位相目標の前と後に位置する垂直
同期信号のいずれか一方が取り出され、他方がマスクさ
れる。従って、取り出された垂直同期信号とドラムの位
置目標との差は小さく抑えられることになる。
According to this structure, the second mask signal is generated by the vertical synchronizing signal which has passed through the switch means, and the vertical synchronizing signal next to this vertical synchronizing signal is within the period of the third set signal obtained from the logic means. Since it does not exist, it cannot pass through the switch means and is masked. The second set signal can set the drum phase target in a relationship such that the drum phase target is located approximately in the center of the second set signal, and by controlling the switch means by the logical product output of the second set signal and the first set signal, One of the vertical synchronizing signals positioned before and after the drum phase target is taken out and the other is masked. Therefore, the difference between the extracted vertical synchronizing signal and the drum position target can be kept small.

【0009】[0009]

【実施例】本発明を実施した図1において、1は同期信
号規制回路であり、この回路1は外部回路からの垂直同
期信号を伝送する入力路2に設けられたスイッチ3と、
このスイッチ3の出力側の線路4に出力される垂直同期
信号(25/30Hzの垂直同期信号)をリセット信号
としてドラムFG信号をカウントし、第1マスク信号を
発生するとともに第1マスク信号期間以外は第1セット
信号を発生する第1の信号発生回路5と、ドラムPG信
号をリセット信号としてドラムPG信号をカウントし、
第2セット信号を発生するとともに第2セット信号以外
の期間は第2マスク信号を発生する第2の信号発生回路
6と、第1、第2の信号発生回路5、6からの信号の論
理積をとり、その出力によってスイッチ4のON/OF
Fを制御するAND回路7とから成っている。線路4の
25/30Hzの垂直同期信号はドラムサーボ回路8へ
与えられる。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In FIG. 1 embodying the present invention, reference numeral 1 is a synchronizing signal regulating circuit, which is a switch 3 provided on an input path 2 for transmitting a vertical synchronizing signal from an external circuit,
A vertical sync signal (vertical sync signal of 25/30 Hz) output to the line 4 on the output side of the switch 3 is used as a reset signal to count the drum FG signal, generate a first mask signal, and generate a signal other than the first mask signal period. Is a first signal generation circuit 5 that generates a first set signal, and counts the drum PG signal using the drum PG signal as a reset signal,
A logical product of the second signal generating circuit 6 that generates the second set signal and the second mask signal during periods other than the second set signal and the signals from the first and second signal generating circuits 5 and 6 Is taken, and the output of the switch turns ON / OFF.
It is composed of an AND circuit 7 for controlling F. The 25/30 Hz vertical synchronizing signal on the line 4 is supplied to the drum servo circuit 8.

【0010】第2の信号発生回路6は、図2のに示す
ドラムPG信号PG1が入力されると、リセットされ、
カウントを1から開始し、10カウント目で立ち上が
り、22カウント目で立ち下がる第2セット信号PS2
を出力する。この第2セット信号PS2の略中央にドラ
ムの位相目標が位置する。第2の信号発生回路6は前記
第2セット信号以外の期間は第2マスク信号PM2を出
力する。この第2の信号発生回路6は次のドラムPG信
号PG2がくると、再びリセットされ、同じような動作
を繰り返す。
The second signal generation circuit 6 is reset when the drum PG signal PG 1 shown in FIG. 2 is input,
The second set signal PS 2 starts counting from 1, rises at the 10th count, and falls at the 22nd count
Is output. The phase target of the drum is located substantially in the center of the second set signal PS 2 . The second signal generation circuit 6 outputs the second mask signal PM 2 during the period other than the second set signal. The second signal generating circuit 6 is reset again when the next drum PG signal PG 2 comes, and the same operation is repeated.

【0011】一方、第1の信号発生回路5は図2ので
示す垂直同期信号(イ)をリセット信号としてカウント
を開始し、リセット信号[従って、垂直同期信号
(イ)]で立ち下がり、11カウント目で立ち上がる第
1マスク信号PM1を出力するとともに、第1マスク信
号PM1の期間以外は第1セット信号PS1を出力する。
On the other hand, the first signal generating circuit 5 starts counting by using the vertical synchronizing signal (a) shown in FIG. 2 as a reset signal, falls by the reset signal [hence, vertical synchronizing signal (a)], and counts 11 The first mask signal PM 1 that rises visually is output, and the first set signal PS 1 is output except during the period of the first mask signal PM 1 .

【0012】前記第1、第2の信号発生回路5、6の出
力を入力するAND回路7は図2のに示すように、第
3セット信号PS3、PS3'と第3マスク信号PM3を出
力する。第3セット信号PS3、PS3'は第1、第2セ
ット信号PS1、PS2の同時存在に基いて生じる。
The AND circuit 7 for inputting the outputs of the first and second signal generating circuits 5 and 6 has the third set signals PS 3 and PS 3 ′ and the third mask signal PM 3 as shown in FIG. Is output. The third set signals PS 3 and PS 3 ′ are generated due to the simultaneous presence of the first and second set signals PS 1 and PS 2 .

【0013】スイッチ3はAND回路7から与えられる
電圧がハイレベルのときONで、ローレベルのときOF
Fになるように構成されている。従って、第3セット信
号PS3、PS3'の期間はONする。このとき、PS3
期間に垂直同期信号(イ)がドラムサーボ制御回路8へ
供給されるが、PS3'の期間に垂直同期信号(ロ)は位
置していないので、スイッチ3を通過することはでき
ず、マスクされる。この図2の信号関係の場合、最大の
ドラム位相誤差Wは図5の従来例のそれに比して小さく
なっている。
The switch 3 is ON when the voltage applied from the AND circuit 7 is at high level, and OF when it is at low level.
It is configured to be F. Therefore, it is turned on during the period of the third set signals PS 3 and PS 3 ′. At this time, the vertical synchronizing signal in a period of PS 3 (b) is supplied to the drum servo control circuit 8, the vertical synchronizing signal period PS 3 '(ii) does not located, passing through the switch 3 Can not be masked. In the case of the signal relationship of FIG. 2, the maximum drum phase error W is smaller than that of the conventional example of FIG.

【0014】次に図3は、垂直同期信号(イ)(ロ)・・
・が図2の場合に対し左側へ少しずれている場合におけ
る図1の回路による動作波形を示している。この信号関
係の場合は、垂直同期信号(イ)がマスクされ、垂直同
期信号(ロ)が通過される。この場合も最大のドラム位
相誤差Wは図5の従来例に比して小さくなっている。
Next, FIG. 3 shows a vertical synchronizing signal (a) (b) ...
Shows the operation waveforms by the circuit of FIG. 1 when the symbol .smallcircle. In the case of this signal relationship, the vertical synchronizing signal (a) is masked and the vertical synchronizing signal (b) is passed. Also in this case, the maximum drum phase error W is smaller than that in the conventional example of FIG.

【0015】[0015]

【発明の効果】以上説明したように本発明によれば、V
TRにおいてVSYNC基準モードへの切り換え時の最
初のドラム位相誤差の最大量を小さくできるので、ドラ
ムサーボ制御回路でドラム位相誤差を目標値へ引き込む
までの時間が短時間で済み、VSYNC基準モードへの
切り換え時の画質の劣化を実質的に抑えることができ
る。
As described above, according to the present invention, V
In TR, the maximum amount of the first drum phase error at the time of switching to the VSYNC standard mode can be reduced, so that the drum servo control circuit takes a short time to pull the drum phase error to the target value, and the VSYNC standard mode can be changed. It is possible to substantially suppress the deterioration of the image quality at the time of switching.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明を実施したVTRのドラムサーボ制御シ
ステムの同期信号規制回路部分を示す回路図。
FIG. 1 is a circuit diagram showing a sync signal regulation circuit portion of a drum servo control system of a VTR embodying the present invention.

【図2】その動作説明波形図。FIG. 2 is a waveform diagram for explaining the operation.

【図3】同じく、垂直同期信号が図2の場合に対しずれ
たときの、その動作説明波形図。
3 is a waveform diagram for explaining the operation when the vertical synchronizing signal is deviated from the case of FIG.

【図4】従来例の回路図。FIG. 4 is a circuit diagram of a conventional example.

【図5】従来例の動作説明波形図。FIG. 5 is a waveform diagram for explaining the operation of the conventional example.

【符号の説明】[Explanation of symbols]

1 同期信号規制回路 2 垂直同期信号入力路 3 スイッチ 4 スイッチの出力側の線路 5 第1の信号発生回路 6 第2の信号発生回路 7 AND回路 8 ドラムサーボ回路 1 sync signal regulation circuit 2 vertical sync signal input path 3 switch 4 switch output line 5 first signal generation circuit 6 second signal generation circuit 7 AND circuit 8 drum servo circuit

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】VTRのドラムサーボ制御回路と、 外部から入力される垂直同期信号を前記ドラムサーボ制
御回路へ入力する入力路に設けられたスイッチ手段と、 前記ドラムサーボ制御回路へ入力される垂直同期信号を
リセット信号とし該リセット信号からドラムFG信号を
カウントして所定カウント値までの時間に対応する幅の
第1マスク信号を生じるとともに、該第1マスク信号期
間以外は第1セット信号を生じる第1の信号発生手段
と、 ドラムPG信号をリセット信号とし該リセット信号から
ドラムFG信号をカウントして第1のカウント値と第2
のカウント値で決まる幅の第2セット信号を生じるとと
もに、該第2セット信号以外は第2マスク信号を生じる
第2の信号発生手段と、 前記第1、第2セット信号が共に存在する期間の幅の第
3セット信号を出力するとともに、該第3セット信号期
間以外は第3マスク信号を生じ、前記第3セット信号に
よって前記スイッチ手段をONさせ、第3マスク信号に
よって前記スイッチ手段をOFFさせるように前記スイ
ッチ手段を制御する論理手段と、 を備えるドラムサーボ制御システム。
1. A drum servo control circuit of a VTR, a switch means provided in an input path for inputting a vertical synchronizing signal input from the outside to the drum servo control circuit, and a vertical input to the drum servo control circuit. Using the synchronization signal as a reset signal, the drum FG signal is counted from the reset signal to generate a first mask signal having a width corresponding to the time up to a predetermined count value, and a first set signal is generated except during the first mask signal period. A first signal generating means, a drum PG signal is used as a reset signal, and the drum FG signal is counted from the reset signal to obtain a first count value and a second count value.
Of the second signal generating means for generating a second mask signal having a width determined by the count value of the second mask signal and a second mask signal other than the second mask signal, and a period during which both the first and second mask signal are present. The third set signal of the width is output, and the third mask signal is generated except during the third set signal period, the switch means is turned on by the third set signal, and the switch means is turned off by the third mask signal. And a logic means for controlling the switch means, the drum servo control system.
JP5170171A 1993-07-09 1993-07-09 Drum servo control system Expired - Lifetime JP2798870B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5170171A JP2798870B2 (en) 1993-07-09 1993-07-09 Drum servo control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5170171A JP2798870B2 (en) 1993-07-09 1993-07-09 Drum servo control system

Publications (2)

Publication Number Publication Date
JPH0729261A true JPH0729261A (en) 1995-01-31
JP2798870B2 JP2798870B2 (en) 1998-09-17

Family

ID=15900010

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5170171A Expired - Lifetime JP2798870B2 (en) 1993-07-09 1993-07-09 Drum servo control system

Country Status (1)

Country Link
JP (1) JP2798870B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6203303B1 (en) 1998-12-11 2001-03-20 Toyoda Koki Kabushiki Kaisha Vane pump

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60223054A (en) * 1985-03-25 1985-11-07 Hitachi Ltd Servo control circuit of magnetic recording and reproducing device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60223054A (en) * 1985-03-25 1985-11-07 Hitachi Ltd Servo control circuit of magnetic recording and reproducing device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6203303B1 (en) 1998-12-11 2001-03-20 Toyoda Koki Kabushiki Kaisha Vane pump

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JP2798870B2 (en) 1998-09-17

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