JPH04299386A - Driving circuit for active matrix type liquid crystal display panel - Google Patents

Abstract

PURPOSE:To provide the driving circuit for the active matrix type liquid crystal display panel which hardly increases in the number of line connections even when the number of display gradations is increased and easily integrated. CONSTITUTION:The driving circuit for the active matrix type liquid crystal display panel consists of a serial/parallel converting shift register 11 which is stored with a binary digital gradation display signal consisting of plural bits, a latch circuit 12 which stores the output signal of the serial/parallel converting shift register 11 for one horizontal scanning period, a counter circuit 13 which divides one horizontal scanning period by the optional number of gradation displays or more with time, a comparing circuit 14 which compares the output signal of the latch circuit 12 with the output signal of the counter circuit 13 and detects their coincidence to output a coincidence signal, and two sample holding circuits 15 and 16.

Description

[Detailed description of the invention]

[Object of the invention]

0002

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit for an active matrix liquid crystal display panel, which generates a driving signal voltage for displaying a liquid crystal display panel with a limited number of gray levels or less.

0003

[Prior Art] When displaying images using an active matrix type liquid crystal display panel, when displaying television images, the number of display gradations is not particularly limited, and analog display signals are amplified to the liquid crystal drive voltage. When displaying computer data rather than television images, generally used methods are to limit the number of gradations that can be displayed to 8 or 16 gradations. .

In the case of the latter method, especially 8 gradations or 1
Display data of 6 gradations is input to the drive circuit group as a binary 3-bit or 4-bit digital signal, and based on the digital display signal, it is converted into an analog display signal voltage of 8 gradations or 16 gradations. FIG. 3 shows the configuration of the drive circuit for the 8-gradation or 16-gradation display, which stores M-bit (3 or 4-bit) display data synchronized with clock pulses for one horizontal scanning line period. When input to the serial input/parallel output type, ie, serial/parallel conversion shift register 20, M-bit display data signals are output to outputs 1 to N of the serial/parallel conversion shift register 20, respectively. The output signals of these serial-to-parallel conversion shift registers 20 are further stored in a latch circuit 21 as latch pulses input in one horizontal scanning line period, and the output signals of the latch circuit 21 are updated every one horizontal scanning line period. .

Furthermore, the output signal of the latch circuit 21 is input to a decoder circuit 22, where the binary M-bit display signal is converted to a hexadecimal number and sent to the analog switch circuit SW.
Controls connection switching of 1 to SWN. Analog signals V1 to Vn (n=8 or 16) for 8 or 16 gradations are input to each analog switch circuit SW1 to SWN, and the output signal of the decoder circuit 22 causes the analog signals V1 to One of Vn will be selected and output. In a drive circuit with such a configuration, the problem is that the number of switch contacts and analog voltage types of the analog switch circuits SW1 to SWN must be prepared for the number of gradations to be displayed. When attempting to display gradations, eight times as many analog voltages and switches are required as compared to eight-gradation display, which increases the number of circuits and makes it difficult to integrate.

[0006]

[Problems to be Solved by the Invention] In the conventional drive circuit described above, it is necessary to prepare the number of switch contacts of the analog switch circuit and the types of analog voltages corresponding to the number of gradations to be displayed. When trying to display gradations, eight times as many types of analog voltages and the number of switch contacts are required as compared to eight-gradation display, which increases the number of circuits and makes it difficult to integrate them.

The present invention has been made in order to eliminate these conventional drawbacks, and provides an active matrix liquid crystal that can be easily integrated, with almost no increase in the number of circuit connections even when the number of display gradations is increased. The purpose of the present invention is to provide a display panel drive circuit.

[Configuration of the invention]

[0009]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a driving signal for displaying a liquid crystal display panel having a structure in which switching elements are arranged in a matrix in a manner limited to a specific number of gradations or less. In an active matrix liquid crystal display panel drive circuit that generates voltage, there is a shift register that stores digital gradation display data consisting of multiple bits for one scanning line period, and an output signal of the shift register that is transferred to the next horizontal scanning line. a latch circuit for storing a period; a time division circuit for time division of one horizontal scanning line period into a number equal to or greater than the specific number of gradations; an output signal of the shift register; A comparison circuit that compares output signals and outputs matching data; and a different analog signal is input for each division period of the time division circuit within one horizontal scanning line period, and an output of the comparison circuit that outputs the matching data. The present invention is characterized in that it includes a first sample-and-hold circuit that performs a sampling operation based on a signal, and a second sample-and-hold circuit that further stores the output of the first sample-and-hold circuit for one horizontal scanning line period.

0010

[Operation] In the present invention, the shift register and the latch circuit operate in the same manner as in the conventional one, but include a time division circuit that time-divides one horizontal scanning line period, a comparison circuit, and two sets of first and second circuits. By having a sample and hold circuit of By time-dividing within the horizontal scanning line period and supplying one gradation worth of analog signal voltage to the sample and hold circuit in each time-division unit period, the number of analog voltage connections can be reduced to one. Therefore, it is possible to reduce the number of input signal voltages when integrated into an integrated circuit.

[0011]

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of a drive circuit according to the present invention, and shows an example of 8-gradation display. This drive circuit has three sets of serial-parallel conversion shift registers with serial input and parallel output to store display data consisting of 3 binary bits synchronized with clock pulses for one horizontal scanning line when performing 8-gradation display. 11, a latch circuit 12 that stores the output signal (each output consists of 3-bit data) of the serial/parallel conversion shift register 11 at the same time as the input of the latch pulse, and a clock pulse and a latch pulse (1) for one horizontal scanning line period. The counter circuit 13 time-divides into eight parts based on the output signal of the latch circuit 12, each consisting of 3 bits, and the binary 3 output signal from the counter circuit 13.
A comparator circuit 14 compares the bit divided address data, detects and outputs matching data, and samples the analog signal voltage that is time-divided (divided into 8) and inputted within one horizontal scanning line period using the matching data output signal. The first thing to remember
, a second sample and hold circuit 16 for further storing the analog output signal of the sample and hold circuit 15 for one horizontal scanning line period, and a current amplification circuit 17.

The operation of this drive circuit will be explained using FIG. 2. The display data (8 gradations, 3-bit binary data) that changes during the rising period of the clock pulse is sequentially read into the serial/parallel conversion shift register 11 during the falling period of the clock pulse, and the display data for one horizontal scanning line period is read into the serial/parallel conversion shift register 11. Immediately after the last display data (Nth) within one horizontal scanning line period is stored in the serial-to-parallel conversion shift register 11, the latch pulse (1) is input to the latch circuit 12, and the latch pulse (1) During the rising period of , all output signals (3 bits each×N) of the serial/parallel conversion shift register 11 are collectively transferred and stored in the latch circuit 12 . At this time, the clock pulse and latch pulse (1) are also input to the counter circuit 13. In the counter circuit 13, one horizontal scanning line period is divided into eight, and as shown in FIG.
bits) are sequentially output within one horizontal scanning line period. The output signal is input to the comparator circuit 14.

On the other hand, all output signals of the latch circuit 12 (each 2
3 bits) is also input to the comparator circuit 14. Comparison circuit 1
4 compares the values of two types of input signals, that is, the total output signal of the latch circuit 12 and the output signal of the counter circuit 13, and when the values of the two types of input signals match, the switch element of the sample and hold circuit 15 is activated. Outputs a signal at the level necessary to turn on. At this time, the coincidence signal is output at one of eight divided periods within one horizontal scanning line period. For example, when the display data is black, the address data of the counter circuit 13 shown in FIG. "0"
A match signal is output within the period of , or when the address data is white, within the period of "7". Each switch element of the sample and hold circuit 15 is turned on by the matching signal.
By doing so, one of the eight gray scale analog signal voltages is stored in the sample and hold circuit 15. This memorized analog voltage is sent to the sample and hold circuit 16 all at once by inputting the latch pulse (2) to yet another set of sample and hold circuits 16 and turning on the switch element of the sample and hold circuit 16. transferred and stored. An arbitrary analog signal voltage among the eight gradations stored in the sample and hold circuit 16 is sent to the current amplification circuit 17.
The signal is then applied to the display data signal input electrode of the active matrix liquid crystal panel.

According to this embodiment, the analog voltages required for gradation display can be time-divided and input to the drive circuit within one horizontal scanning line period, which reduces the number of input analog voltage connections compared to the conventional configuration. This makes it possible to reduce the number of lines to one, making it easier to integrate the circuit.

[0015] A drive circuit configured to use two sets of sample and hold circuits is used for displaying television images in which the number of display gradations is not particularly limited, but the operating frequency of the sample and hold circuits in this case is equal to the frequency of the television signal. band,
For example, about 4 MHz is required, but the sample and hold circuit of the present invention can handle one horizontal scanning frequency (15 to 30 kHz).
The operating frequency (for example, about 0.5 MHz) can be multiple times the number of display gradations (for example, about 0.5 MHz), the speed of the sample and hold circuit 15 can be made lower than that for television display, and the scale of the sample and hold circuit can also be reduced.

[0016]

[Effects of the Invention] As explained above, according to the present invention,
By making it possible to time-divide input the analog voltage required for gradation display over one horizontal scanning line period, the number of analog voltage connections can be reduced to one, making it easier to integrate the drive circuit. Become.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of a drive circuit according to an embodiment of the present invention.

FIG. 2 is a time chart showing the operation of a drive circuit according to an embodiment of the present invention.

FIG. 3 is a circuit diagram showing the configuration of a conventional drive circuit.

[Explanation of symbols]

11……Serial-to-parallel conversion shift register 12...Latch circuit 13……Counter circuit 14……Comparison circuit 15, 16...sample hold circuit

Claims (1)

[Claims] 1. A drive circuit for an active matrix type liquid crystal display panel that generates a drive signal voltage for displaying a liquid crystal display panel having a structure in which switching elements are arranged in a matrix in a manner limited to a specific number of gradations or less, comprising:
a shift register for storing digital gradation display data consisting of a plurality of bits for one scanning line period; a latch circuit for storing the output signal of the shift register for the next one horizontal scanning line period; a time division circuit that divides time into a number equal to or greater than the specific number of gradations; a comparison circuit that compares the output signal of the shift register with the output signal of the time division circuit and outputs matching data; a first sample hold circuit which receives a different analog signal for each division period of the time division circuit within a horizontal scanning line period and performs a sampling operation based on an output signal of the comparison circuit that outputs the coincidence data; 1. A drive circuit for an active matrix liquid crystal display panel, comprising a second sample and hold circuit that further stores the output of the first sample and hold circuit for one horizontal scanning line period.